From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
"Sergey Fedorov" <serge.fdrv@gmail.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
"QEMU Developers" <qemu-devel@nongnu.org>,
"Alexander Graf" <agraf@suse.de>
Subject: Re: [Qemu-devel] [PATCH v3 11/15] target-arm: Add CNTVOFF_EL2
Date: Tue, 2 Jun 2015 11:45:41 +1000 [thread overview]
Message-ID: <20150602014541.GG30952@toto> (raw)
In-Reply-To: <CAFEAcA9c64+nSzPoBV9puNGMW9PV2FZ-sr-ehbHLLyCLKYwStw@mail.gmail.com>
On Mon, Jun 01, 2015 at 05:09:29PM +0100, Peter Maydell wrote:
> On 29 May 2015 at 07:43, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote:
> > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> >
> > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> > ---
> > target-arm/cpu.h | 1 +
> > target-arm/helper.c | 47 +++++++++++++++++++++++++++++++++++++++++------
> > 2 files changed, 42 insertions(+), 6 deletions(-)
> >
> > diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> > index 21b5b8e..1a66aa4 100644
> > --- a/target-arm/cpu.h
> > +++ b/target-arm/cpu.h
> > @@ -355,6 +355,7 @@ typedef struct CPUARMState {
> > };
> > uint64_t c14_cntfrq; /* Counter Frequency register */
> > uint64_t c14_cntkctl; /* Timer Control register */
> > + uint64_t cntvoff_el2; /* Counter Virtual Offset register */
> > ARMGenericTimer c14_timer[NUM_GTIMERS];
> > uint32_t c15_cpar; /* XScale Coprocessor Access Register */
> > uint32_t c15_ticonfig; /* TI925T configuration byte. */
> > diff --git a/target-arm/helper.c b/target-arm/helper.c
> > index a5c0363..f5579fc 100644
> > --- a/target-arm/helper.c
> > +++ b/target-arm/helper.c
> > @@ -1216,9 +1216,11 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
> > /* Timer enabled: calculate and set current ISTATUS, irq, and
> > * reset timer to when ISTATUS next has to change
> > */
> > + uint64_t offset = timeridx == GTIMER_VIRT ?
> > + cpu->env.cp15.cntvoff_el2 : 0;
> > uint64_t count = gt_get_countervalue(&cpu->env);
> > /* Note that this must be unsigned 64 bit arithmetic: */
> > - int istatus = count >= gt->cval;
> > + int istatus = (int64_t) (count - offset - gt->cval) >= 0;
>
> The comment says "must be unsigned" and your change is adding
> a cast to force signed comparison -- one of them must be wrong.
>
> I'm going to apply patches 1..10 to target-arm.next; this is
> where I ran out of time to review.
Thanks Peter,
The manual (Operation of the CompareValue views of the timers) says:
EventTriggered = (((Counter[63:0] – Offset[63:0])[63:0] - CompareValue[63:0]) >= 0)
It also says:
In this view of a timer, Counter , Offset , and CompareValue are all 64-bit unsigned values.
My interpretation is that the arithmetics are done unsigned but the compare (>= 0) has to be signed (if not it is always true).
Does that make sense?
I can modify the comment to make that clear.
Thanks,
Edgar
next prev parent reply other threads:[~2015-06-02 1:49 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-29 6:43 [Qemu-devel] [PATCH v3 00/15] arm: Steps towards EL2 support round 3 Edgar E. Iglesias
2015-05-29 6:43 ` [Qemu-devel] [PATCH v3 01/15] target-arm: Correct check for non-EL3 Edgar E. Iglesias
2015-06-01 20:10 ` John Snow
2015-06-01 20:26 ` Peter Maydell
2015-06-01 20:31 ` John Snow
2015-06-02 12:55 ` Peter Maydell
2015-05-29 6:43 ` [Qemu-devel] [PATCH v3 02/15] target-arm: Break down TLB_LOCKDOWN Edgar E. Iglesias
2015-05-29 6:43 ` [Qemu-devel] [PATCH v3 03/15] target-arm: Add MAIR_EL2 Edgar E. Iglesias
2015-05-29 6:43 ` [Qemu-devel] [PATCH v3 04/15] target-arm: Add TCR_EL2 Edgar E. Iglesias
2015-05-29 6:43 ` [Qemu-devel] [PATCH v3 05/15] target-arm: Add SCTLR_EL2 Edgar E. Iglesias
2015-05-29 6:43 ` [Qemu-devel] [PATCH v3 06/15] target-arm: Add TPIDR_EL2 Edgar E. Iglesias
2015-06-01 15:16 ` Peter Maydell
2015-05-29 6:43 ` [Qemu-devel] [PATCH v3 07/15] target-arm: Add TTBR0_EL2 Edgar E. Iglesias
2015-06-01 15:30 ` Peter Maydell
2015-05-29 6:43 ` [Qemu-devel] [PATCH v3 08/15] target-arm: Add TLBI_ALLE1{IS} Edgar E. Iglesias
2015-06-01 15:32 ` Peter Maydell
2015-05-29 6:43 ` [Qemu-devel] [PATCH v3 09/15] target-arm: Add TLBI_ALLE2 Edgar E. Iglesias
2015-06-01 15:34 ` Peter Maydell
2015-05-29 6:43 ` [Qemu-devel] [PATCH v3 10/15] target-arm: Add TLBI_VAE2{IS} Edgar E. Iglesias
2015-05-29 6:43 ` [Qemu-devel] [PATCH v3 11/15] target-arm: Add CNTVOFF_EL2 Edgar E. Iglesias
2015-06-01 16:09 ` Peter Maydell
2015-06-02 1:45 ` Edgar E. Iglesias [this message]
2015-05-29 6:43 ` [Qemu-devel] [PATCH v3 12/15] target-arm: Add CNTHCTL_EL2 Edgar E. Iglesias
2015-05-29 6:43 ` [Qemu-devel] [PATCH v3 13/15] target-arm: Pass timeridx as argument to various timer functions Edgar E. Iglesias
2015-05-29 6:43 ` [Qemu-devel] [PATCH v3 14/15] target-arm: Add HYP timer Edgar E. Iglesias
2015-05-29 6:43 ` [Qemu-devel] [PATCH v3 15/15] hw/arm/virt: Connect the Hypervisor timer Edgar E. Iglesias
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