diff for duplicates of <20150603233200.6017.91687@quantum> diff --git a/a/1.txt b/N1/1.txt index 0c9ccf5..01aacba 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,8 +1,7 @@ Quoting Paul Burton (2015-05-24 08:11:40) > Add support for the clocks provided by the CGU in the Ingenic JZ4780 > SoC, making use of the SoC-agnostic CGU code to do the heavy lifting. -> = - +> > Signed-off-by: Paul Burton <paul.burton@imgtec.com> > Co-authored-by: Paul Cercueil <paul@crapouillou.net> > Cc: Lars-Peter Clausen <lars@metafoo.de> @@ -23,15 +22,13 @@ Regards, Mike > --- -> = - +> > Changes in v5: > - Declare jz4780_otg_phy_ops static. > - Drop setting the parent of the UHC clock during probe - USB isn't > supported as of this patchset anyway, so it can be dealt with in > whatever's deemed the best way later. -> = - +> > Changes in v4: > - Return on ingenic_cgu_new or ingenic_cgu_register_clocks failure. > - Initialise all unused clock parent fields to -1. Zero initialisation @@ -41,33 +38,27 @@ Mike > to the clock description (which is hopefully OK). Initialising to -1 > makes sense for resilience should the latter ever not be the case, > and to avoid that bit of implicit magic knowledge. -> = - +> > Changes in v3: > - Rebase. -> = - +> > Changes in v2: > - Remove FSF address per checkpatch (ZubairLK). -> = - +> > drivers/clk/ingenic/Makefile | 1 + -> drivers/clk/ingenic/jz4780-cgu.c | 733 +++++++++++++++++++++++++++++++++= -++++++ +> drivers/clk/ingenic/jz4780-cgu.c | 733 +++++++++++++++++++++++++++++++++++++++ > 2 files changed, 734 insertions(+) > create mode 100644 drivers/clk/ingenic/jz4780-cgu.c -> = - +> > diff --git a/drivers/clk/ingenic/Makefile b/drivers/clk/ingenic/Makefile > index e6db7da..cd47b06 100644 > --- a/drivers/clk/ingenic/Makefile > +++ b/drivers/clk/ingenic/Makefile > @@ -1,2 +1,3 @@ -> obj-y +=3D cgu.o -> obj-$(CONFIG_MACH_JZ4740) +=3D jz4740-cgu.o -> +obj-$(CONFIG_MACH_JZ4780) +=3D jz4780-cgu.o -> diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz478= -0-cgu.c +> obj-y += cgu.o +> obj-$(CONFIG_MACH_JZ4740) += jz4740-cgu.o +> +obj-$(CONFIG_MACH_JZ4780) += jz4780-cgu.o +> diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c > new file mode 100644 > index 0000000..431f962 > --- /dev/null @@ -188,10 +179,10 @@ Mike > + > + spin_lock_irqsave(&cgu->lock, flags); > + -> + usbpcr1 =3D readl(cgu->base + CGU_REG_USBPCR1); -> + usbpcr1 &=3D ~USBPCR1_REFCLKSEL_MASK; +> + usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); +> + usbpcr1 &= ~USBPCR1_REFCLKSEL_MASK; > + /* we only use CLKCORE */ -> + usbpcr1 |=3D USBPCR1_REFCLKSEL_CORE; +> + usbpcr1 |= USBPCR1_REFCLKSEL_CORE; > + writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); > + > + spin_unlock_irqrestore(&cgu->lock, flags); @@ -204,8 +195,8 @@ Mike > + u32 usbpcr1; > + unsigned refclk_div; > + -> + usbpcr1 =3D readl(cgu->base + CGU_REG_USBPCR1); -> + refclk_div =3D usbpcr1 & USBPCR1_REFCLKDIV_MASK; +> + usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); +> + refclk_div = usbpcr1 & USBPCR1_REFCLKDIV_MASK; > + > + switch (refclk_div) { > + case USBPCR1_REFCLKDIV_12: @@ -225,8 +216,7 @@ Mike > + return parent_rate; > +} > + -> +static long jz4780_otg_phy_round_rate(struct clk_hw *hw, unsigned long r= -eq_rate, +> +static long jz4780_otg_phy_round_rate(struct clk_hw *hw, unsigned long req_rate, > + unsigned long *parent_rate) > +{ > + if (req_rate < 15600000) @@ -241,8 +231,7 @@ eq_rate, > + return 48000000; > +} > + -> +static int jz4780_otg_phy_set_rate(struct clk_hw *hw, unsigned long req_= -rate, +> +static int jz4780_otg_phy_set_rate(struct clk_hw *hw, unsigned long req_rate, > + unsigned long parent_rate) > +{ > + unsigned long flags; @@ -250,19 +239,19 @@ rate, > + > + switch (req_rate) { > + case 12000000: -> + div_bits =3D USBPCR1_REFCLKDIV_12; +> + div_bits = USBPCR1_REFCLKDIV_12; > + break; > + > + case 19200000: -> + div_bits =3D USBPCR1_REFCLKDIV_19_2; +> + div_bits = USBPCR1_REFCLKDIV_19_2; > + break; > + > + case 24000000: -> + div_bits =3D USBPCR1_REFCLKDIV_24; +> + div_bits = USBPCR1_REFCLKDIV_24; > + break; > + > + case 48000000: -> + div_bits =3D USBPCR1_REFCLKDIV_48; +> + div_bits = USBPCR1_REFCLKDIV_48; > + break; > + > + default: @@ -271,529 +260,521 @@ rate, > + > + spin_lock_irqsave(&cgu->lock, flags); > + -> + usbpcr1 =3D readl(cgu->base + CGU_REG_USBPCR1); -> + usbpcr1 &=3D ~USBPCR1_REFCLKDIV_MASK; -> + usbpcr1 |=3D div_bits; +> + usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); +> + usbpcr1 &= ~USBPCR1_REFCLKDIV_MASK; +> + usbpcr1 |= div_bits; > + writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); > + > + spin_unlock_irqrestore(&cgu->lock, flags); > + return 0; > +} > + -> +static struct clk_ops jz4780_otg_phy_ops =3D { -> + .get_parent =3D jz4780_otg_phy_get_parent, -> + .set_parent =3D jz4780_otg_phy_set_parent, +> +static struct clk_ops jz4780_otg_phy_ops = { +> + .get_parent = jz4780_otg_phy_get_parent, +> + .set_parent = jz4780_otg_phy_set_parent, > + -> + .recalc_rate =3D jz4780_otg_phy_recalc_rate, -> + .round_rate =3D jz4780_otg_phy_round_rate, -> + .set_rate =3D jz4780_otg_phy_set_rate, +> + .recalc_rate = jz4780_otg_phy_recalc_rate, +> + .round_rate = jz4780_otg_phy_round_rate, +> + .set_rate = jz4780_otg_phy_set_rate, > +}; > + -> +static const s8 pll_od_encoding[16] =3D { +> +static const s8 pll_od_encoding[16] = { > + 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, > + 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, > +}; > + -> +static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] =3D { +> +static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = { > + > + /* External clocks */ > + -> + [JZ4780_CLK_EXCLK] =3D { "ext", CGU_CLK_EXT }, -> + [JZ4780_CLK_RTCLK] =3D { "rtc", CGU_CLK_EXT }, +> + [JZ4780_CLK_EXCLK] = { "ext", CGU_CLK_EXT }, +> + [JZ4780_CLK_RTCLK] = { "rtc", CGU_CLK_EXT }, > + > + /* PLLs */ > + > +#define DEF_PLL(name) { \ -> + .reg =3D CGU_REG_ ## name, \ -> + .m_shift =3D 19, \ -> + .m_bits =3D 13, \ -> + .m_offset =3D 1, \ -> + .n_shift =3D 13, \ -> + .n_bits =3D 6, \ -> + .n_offset =3D 1, \ -> + .od_shift =3D 9, \ -> + .od_bits =3D 4, \ -> + .od_max =3D 16, \ -> + .od_encoding =3D pll_od_encoding, \ -> + .stable_bit =3D 6, \ -> + .bypass_bit =3D 1, \ -> + .enable_bit =3D 0, \ +> + .reg = CGU_REG_ ## name, \ +> + .m_shift = 19, \ +> + .m_bits = 13, \ +> + .m_offset = 1, \ +> + .n_shift = 13, \ +> + .n_bits = 6, \ +> + .n_offset = 1, \ +> + .od_shift = 9, \ +> + .od_bits = 4, \ +> + .od_max = 16, \ +> + .od_encoding = pll_od_encoding, \ +> + .stable_bit = 6, \ +> + .bypass_bit = 1, \ +> + .enable_bit = 0, \ > +} > + -> + [JZ4780_CLK_APLL] =3D { +> + [JZ4780_CLK_APLL] = { > + "apll", CGU_CLK_PLL, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .pll =3D DEF_PLL(APLL), +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .pll = DEF_PLL(APLL), > + }, > + -> + [JZ4780_CLK_MPLL] =3D { +> + [JZ4780_CLK_MPLL] = { > + "mpll", CGU_CLK_PLL, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .pll =3D DEF_PLL(MPLL), +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .pll = DEF_PLL(MPLL), > + }, > + -> + [JZ4780_CLK_EPLL] =3D { +> + [JZ4780_CLK_EPLL] = { > + "epll", CGU_CLK_PLL, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .pll =3D DEF_PLL(EPLL), +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .pll = DEF_PLL(EPLL), > + }, > + -> + [JZ4780_CLK_VPLL] =3D { +> + [JZ4780_CLK_VPLL] = { > + "vpll", CGU_CLK_PLL, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .pll =3D DEF_PLL(VPLL), +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .pll = DEF_PLL(VPLL), > + }, > + > +#undef DEF_PLL > + > + /* Custom (SoC-specific) OTG PHY */ > + -> + [JZ4780_CLK_OTGPHY] =3D { +> + [JZ4780_CLK_OTGPHY] = { > + "otg_phy", CGU_CLK_CUSTOM, -> + .parents =3D { -1, -1, JZ4780_CLK_EXCLK, -1 }, -> + .custom =3D { &jz4780_otg_phy_ops }, +> + .parents = { -1, -1, JZ4780_CLK_EXCLK, -1 }, +> + .custom = { &jz4780_otg_phy_ops }, > + }, > + > + /* Muxes & dividers */ > + -> + [JZ4780_CLK_SCLKA] =3D { +> + [JZ4780_CLK_SCLKA] = { > + "sclk_a", CGU_CLK_MUX, -> + .parents =3D { -1, JZ4780_CLK_APLL, JZ4780_CLK_EXCLK, +> + .parents = { -1, JZ4780_CLK_APLL, JZ4780_CLK_EXCLK, > + JZ4780_CLK_RTCLK }, -> + .mux =3D { CGU_REG_CLOCKCONTROL, 30, 2 }, +> + .mux = { CGU_REG_CLOCKCONTROL, 30, 2 }, > + }, > + -> + [JZ4780_CLK_CPUMUX] =3D { +> + [JZ4780_CLK_CPUMUX] = { > + "cpumux", CGU_CLK_MUX, -> + .parents =3D { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, +> + .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, > + JZ4780_CLK_EPLL }, -> + .mux =3D { CGU_REG_CLOCKCONTROL, 28, 2 }, +> + .mux = { CGU_REG_CLOCKCONTROL, 28, 2 }, > + }, > + -> + [JZ4780_CLK_CPU] =3D { +> + [JZ4780_CLK_CPU] = { > + "cpu", CGU_CLK_DIV, -> + .parents =3D { JZ4780_CLK_CPUMUX, -1, -1, -1 }, -> + .div =3D { CGU_REG_CLOCKCONTROL, 0, 4, 22, -1, -1 }, +> + .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 }, +> + .div = { CGU_REG_CLOCKCONTROL, 0, 4, 22, -1, -1 }, > + }, > + -> + [JZ4780_CLK_L2CACHE] =3D { +> + [JZ4780_CLK_L2CACHE] = { > + "l2cache", CGU_CLK_DIV, -> + .parents =3D { JZ4780_CLK_CPUMUX, -1, -1, -1 }, -> + .div =3D { CGU_REG_CLOCKCONTROL, 4, 4, -1, -1, -1 }, +> + .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 }, +> + .div = { CGU_REG_CLOCKCONTROL, 4, 4, -1, -1, -1 }, > + }, > + -> + [JZ4780_CLK_AHB0] =3D { +> + [JZ4780_CLK_AHB0] = { > + "ahb0", CGU_CLK_MUX | CGU_CLK_DIV, -> + .parents =3D { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, +> + .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, > + JZ4780_CLK_EPLL }, -> + .mux =3D { CGU_REG_CLOCKCONTROL, 26, 2 }, -> + .div =3D { CGU_REG_CLOCKCONTROL, 8, 4, 21, -1, -1 }, +> + .mux = { CGU_REG_CLOCKCONTROL, 26, 2 }, +> + .div = { CGU_REG_CLOCKCONTROL, 8, 4, 21, -1, -1 }, > + }, > + -> + [JZ4780_CLK_AHB2PMUX] =3D { +> + [JZ4780_CLK_AHB2PMUX] = { > + "ahb2_apb_mux", CGU_CLK_MUX, -> + .parents =3D { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, +> + .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, > + JZ4780_CLK_RTCLK }, -> + .mux =3D { CGU_REG_CLOCKCONTROL, 24, 2 }, +> + .mux = { CGU_REG_CLOCKCONTROL, 24, 2 }, > + }, > + -> + [JZ4780_CLK_AHB2] =3D { +> + [JZ4780_CLK_AHB2] = { > + "ahb2", CGU_CLK_DIV, -> + .parents =3D { JZ4780_CLK_AHB2PMUX, -1, -1, -1 }, -> + .div =3D { CGU_REG_CLOCKCONTROL, 12, 4, 20, -1, -1 }, +> + .parents = { JZ4780_CLK_AHB2PMUX, -1, -1, -1 }, +> + .div = { CGU_REG_CLOCKCONTROL, 12, 4, 20, -1, -1 }, > + }, > + -> + [JZ4780_CLK_PCLK] =3D { +> + [JZ4780_CLK_PCLK] = { > + "pclk", CGU_CLK_DIV, -> + .parents =3D { JZ4780_CLK_AHB2PMUX, -1, -1, -1 }, -> + .div =3D { CGU_REG_CLOCKCONTROL, 16, 4, 20, -1, -1 }, +> + .parents = { JZ4780_CLK_AHB2PMUX, -1, -1, -1 }, +> + .div = { CGU_REG_CLOCKCONTROL, 16, 4, 20, -1, -1 }, > + }, > + -> + [JZ4780_CLK_DDR] =3D { +> + [JZ4780_CLK_DDR] = { > + "ddr", CGU_CLK_MUX | CGU_CLK_DIV, -> + .parents =3D { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 = -}, -> + .mux =3D { CGU_REG_DDRCDR, 30, 2 }, -> + .div =3D { CGU_REG_DDRCDR, 0, 4, 29, 28, 27 }, +> + .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 }, +> + .mux = { CGU_REG_DDRCDR, 30, 2 }, +> + .div = { CGU_REG_DDRCDR, 0, 4, 29, 28, 27 }, > + }, > + -> + [JZ4780_CLK_VPU] =3D { +> + [JZ4780_CLK_VPU] = { > + "vpu", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, +> + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, > + JZ4780_CLK_EPLL, -1 }, -> + .mux =3D { CGU_REG_VPUCDR, 30, 2 }, -> + .div =3D { CGU_REG_VPUCDR, 0, 4, 29, 28, 27 }, -> + .gate =3D { CGU_REG_CLKGR1, 2 }, +> + .mux = { CGU_REG_VPUCDR, 30, 2 }, +> + .div = { CGU_REG_VPUCDR, 0, 4, 29, 28, 27 }, +> + .gate = { CGU_REG_CLKGR1, 2 }, > + }, > + -> + [JZ4780_CLK_I2SPLL] =3D { +> + [JZ4780_CLK_I2SPLL] = { > + "i2s_pll", CGU_CLK_MUX | CGU_CLK_DIV, -> + .parents =3D { JZ4780_CLK_SCLKA, JZ4780_CLK_EPLL, -1, -1 = -}, -> + .mux =3D { CGU_REG_I2SCDR, 30, 1 }, -> + .div =3D { CGU_REG_I2SCDR, 0, 8, 29, 28, 27 }, +> + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_EPLL, -1, -1 }, +> + .mux = { CGU_REG_I2SCDR, 30, 1 }, +> + .div = { CGU_REG_I2SCDR, 0, 8, 29, 28, 27 }, > + }, > + -> + [JZ4780_CLK_I2S] =3D { +> + [JZ4780_CLK_I2S] = { > + "i2s", CGU_CLK_MUX, -> + .parents =3D { JZ4780_CLK_EXCLK, JZ4780_CLK_I2SPLL, -1, -= -1 }, -> + .mux =3D { CGU_REG_I2SCDR, 31, 1 }, +> + .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_I2SPLL, -1, -1 }, +> + .mux = { CGU_REG_I2SCDR, 31, 1 }, > + }, > + -> + [JZ4780_CLK_LCD0PIXCLK] =3D { +> + [JZ4780_CLK_LCD0PIXCLK] = { > + "lcd0pixclk", CGU_CLK_MUX | CGU_CLK_DIV, -> + .parents =3D { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, +> + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, > + JZ4780_CLK_VPLL, -1 }, -> + .mux =3D { CGU_REG_LP0CDR, 30, 2 }, -> + .div =3D { CGU_REG_LP0CDR, 0, 8, 28, 27, 26 }, +> + .mux = { CGU_REG_LP0CDR, 30, 2 }, +> + .div = { CGU_REG_LP0CDR, 0, 8, 28, 27, 26 }, > + }, > + -> + [JZ4780_CLK_LCD1PIXCLK] =3D { +> + [JZ4780_CLK_LCD1PIXCLK] = { > + "lcd1pixclk", CGU_CLK_MUX | CGU_CLK_DIV, -> + .parents =3D { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, +> + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, > + JZ4780_CLK_VPLL, -1 }, -> + .mux =3D { CGU_REG_LP1CDR, 30, 2 }, -> + .div =3D { CGU_REG_LP1CDR, 0, 8, 28, 27, 26 }, +> + .mux = { CGU_REG_LP1CDR, 30, 2 }, +> + .div = { CGU_REG_LP1CDR, 0, 8, 28, 27, 26 }, > + }, > + -> + [JZ4780_CLK_MSCMUX] =3D { +> + [JZ4780_CLK_MSCMUX] = { > + "msc_mux", CGU_CLK_MUX, -> + .parents =3D { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 = -}, -> + .mux =3D { CGU_REG_MSC0CDR, 30, 2 }, +> + .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 }, +> + .mux = { CGU_REG_MSC0CDR, 30, 2 }, > + }, > + -> + [JZ4780_CLK_MSC0] =3D { +> + [JZ4780_CLK_MSC0] = { > + "msc0", CGU_CLK_DIV | CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_MSCMUX, -1, -1, -1 }, -> + .div =3D { CGU_REG_MSC0CDR, 0, 8, 29, 28, 27 }, -> + .gate =3D { CGU_REG_CLKGR0, 3 }, +> + .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 }, +> + .div = { CGU_REG_MSC0CDR, 0, 8, 29, 28, 27 }, +> + .gate = { CGU_REG_CLKGR0, 3 }, > + }, > + -> + [JZ4780_CLK_MSC1] =3D { +> + [JZ4780_CLK_MSC1] = { > + "msc1", CGU_CLK_DIV | CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_MSCMUX, -1, -1, -1 }, -> + .div =3D { CGU_REG_MSC1CDR, 0, 8, 29, 28, 27 }, -> + .gate =3D { CGU_REG_CLKGR0, 11 }, +> + .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 }, +> + .div = { CGU_REG_MSC1CDR, 0, 8, 29, 28, 27 }, +> + .gate = { CGU_REG_CLKGR0, 11 }, > + }, > + -> + [JZ4780_CLK_MSC2] =3D { +> + [JZ4780_CLK_MSC2] = { > + "msc2", CGU_CLK_DIV | CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_MSCMUX, -1, -1, -1 }, -> + .div =3D { CGU_REG_MSC2CDR, 0, 8, 29, 28, 27 }, -> + .gate =3D { CGU_REG_CLKGR0, 12 }, +> + .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 }, +> + .div = { CGU_REG_MSC2CDR, 0, 8, 29, 28, 27 }, +> + .gate = { CGU_REG_CLKGR0, 12 }, > + }, > + -> + [JZ4780_CLK_UHC] =3D { +> + [JZ4780_CLK_UHC] = { > + "uhc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, +> + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, > + JZ4780_CLK_EPLL, JZ4780_CLK_OTGPHY }, -> + .mux =3D { CGU_REG_UHCCDR, 30, 2 }, -> + .div =3D { CGU_REG_UHCCDR, 0, 8, 29, 28, 27 }, -> + .gate =3D { CGU_REG_CLKGR0, 24 }, +> + .mux = { CGU_REG_UHCCDR, 30, 2 }, +> + .div = { CGU_REG_UHCCDR, 0, 8, 29, 28, 27 }, +> + .gate = { CGU_REG_CLKGR0, 24 }, > + }, > + -> + [JZ4780_CLK_SSIPLL] =3D { +> + [JZ4780_CLK_SSIPLL] = { > + "ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV, -> + .parents =3D { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 = -}, -> + .mux =3D { CGU_REG_SSICDR, 30, 1 }, -> + .div =3D { CGU_REG_SSICDR, 0, 8, 29, 28, 27 }, +> + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 }, +> + .mux = { CGU_REG_SSICDR, 30, 1 }, +> + .div = { CGU_REG_SSICDR, 0, 8, 29, 28, 27 }, > + }, > + -> + [JZ4780_CLK_SSI] =3D { +> + [JZ4780_CLK_SSI] = { > + "ssi", CGU_CLK_MUX, -> + .parents =3D { JZ4780_CLK_EXCLK, JZ4780_CLK_SSIPLL, -1, -= -1 }, -> + .mux =3D { CGU_REG_SSICDR, 31, 1 }, +> + .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_SSIPLL, -1, -1 }, +> + .mux = { CGU_REG_SSICDR, 31, 1 }, > + }, > + -> + [JZ4780_CLK_CIMMCLK] =3D { +> + [JZ4780_CLK_CIMMCLK] = { > + "cim_mclk", CGU_CLK_MUX | CGU_CLK_DIV, -> + .parents =3D { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 = -}, -> + .mux =3D { CGU_REG_CIMCDR, 31, 1 }, -> + .div =3D { CGU_REG_CIMCDR, 0, 8, 30, 29, 28 }, +> + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 }, +> + .mux = { CGU_REG_CIMCDR, 31, 1 }, +> + .div = { CGU_REG_CIMCDR, 0, 8, 30, 29, 28 }, > + }, > + -> + [JZ4780_CLK_PCMPLL] =3D { +> + [JZ4780_CLK_PCMPLL] = { > + "pcm_pll", CGU_CLK_MUX | CGU_CLK_DIV, -> + .parents =3D { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, +> + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, > + JZ4780_CLK_EPLL, JZ4780_CLK_VPLL }, -> + .mux =3D { CGU_REG_PCMCDR, 29, 2 }, -> + .div =3D { CGU_REG_PCMCDR, 0, 8, 28, 27, 26 }, +> + .mux = { CGU_REG_PCMCDR, 29, 2 }, +> + .div = { CGU_REG_PCMCDR, 0, 8, 28, 27, 26 }, > + }, > + -> + [JZ4780_CLK_PCM] =3D { +> + [JZ4780_CLK_PCM] = { > + "pcm", CGU_CLK_MUX | CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, JZ4780_CLK_PCMPLL, -1, -= -1 }, -> + .mux =3D { CGU_REG_PCMCDR, 31, 1 }, -> + .gate =3D { CGU_REG_CLKGR1, 3 }, +> + .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_PCMPLL, -1, -1 }, +> + .mux = { CGU_REG_PCMCDR, 31, 1 }, +> + .gate = { CGU_REG_CLKGR1, 3 }, > + }, > + -> + [JZ4780_CLK_GPU] =3D { +> + [JZ4780_CLK_GPU] = { > + "gpu", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, -> + .parents =3D { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, +> + .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, > + JZ4780_CLK_EPLL }, -> + .mux =3D { CGU_REG_GPUCDR, 30, 2 }, -> + .div =3D { CGU_REG_GPUCDR, 0, 4, 29, 28, 27 }, -> + .gate =3D { CGU_REG_CLKGR1, 4 }, +> + .mux = { CGU_REG_GPUCDR, 30, 2 }, +> + .div = { CGU_REG_GPUCDR, 0, 4, 29, 28, 27 }, +> + .gate = { CGU_REG_CLKGR1, 4 }, > + }, > + -> + [JZ4780_CLK_HDMI] =3D { +> + [JZ4780_CLK_HDMI] = { > + "hdmi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, +> + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, > + JZ4780_CLK_VPLL, -1 }, -> + .mux =3D { CGU_REG_HDMICDR, 30, 2 }, -> + .div =3D { CGU_REG_HDMICDR, 0, 8, 29, 28, 26 }, -> + .gate =3D { CGU_REG_CLKGR1, 9 }, +> + .mux = { CGU_REG_HDMICDR, 30, 2 }, +> + .div = { CGU_REG_HDMICDR, 0, 8, 29, 28, 26 }, +> + .gate = { CGU_REG_CLKGR1, 9 }, > + }, > + -> + [JZ4780_CLK_BCH] =3D { +> + [JZ4780_CLK_BCH] = { > + "bch", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, -> + .parents =3D { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, +> + .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, > + JZ4780_CLK_EPLL }, -> + .mux =3D { CGU_REG_BCHCDR, 30, 2 }, -> + .div =3D { CGU_REG_BCHCDR, 0, 4, 29, 28, 27 }, -> + .gate =3D { CGU_REG_CLKGR0, 1 }, +> + .mux = { CGU_REG_BCHCDR, 30, 2 }, +> + .div = { CGU_REG_BCHCDR, 0, 4, 29, 28, 27 }, +> + .gate = { CGU_REG_CLKGR0, 1 }, > + }, > + > + /* Gate-only clocks */ > + -> + [JZ4780_CLK_NEMC] =3D { +> + [JZ4780_CLK_NEMC] = { > + "nemc", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_AHB2, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 0 }, +> + .parents = { JZ4780_CLK_AHB2, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 0 }, > + }, > + -> + [JZ4780_CLK_OTG0] =3D { +> + [JZ4780_CLK_OTG0] = { > + "otg0", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 2 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 2 }, > + }, > + -> + [JZ4780_CLK_SSI0] =3D { +> + [JZ4780_CLK_SSI0] = { > + "ssi0", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_SSI, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 4 }, +> + .parents = { JZ4780_CLK_SSI, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 4 }, > + }, > + -> + [JZ4780_CLK_SMB0] =3D { +> + [JZ4780_CLK_SMB0] = { > + "smb0", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_PCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 5 }, +> + .parents = { JZ4780_CLK_PCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 5 }, > + }, > + -> + [JZ4780_CLK_SMB1] =3D { +> + [JZ4780_CLK_SMB1] = { > + "smb1", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_PCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 6 }, +> + .parents = { JZ4780_CLK_PCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 6 }, > + }, > + -> + [JZ4780_CLK_SCC] =3D { +> + [JZ4780_CLK_SCC] = { > + "scc", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 7 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 7 }, > + }, > + -> + [JZ4780_CLK_AIC] =3D { +> + [JZ4780_CLK_AIC] = { > + "aic", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 8 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 8 }, > + }, > + -> + [JZ4780_CLK_TSSI0] =3D { +> + [JZ4780_CLK_TSSI0] = { > + "tssi0", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 9 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 9 }, > + }, > + -> + [JZ4780_CLK_OWI] =3D { +> + [JZ4780_CLK_OWI] = { > + "owi", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 10 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 10 }, > + }, > + -> + [JZ4780_CLK_KBC] =3D { +> + [JZ4780_CLK_KBC] = { > + "kbc", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 13 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 13 }, > + }, > + -> + [JZ4780_CLK_SADC] =3D { +> + [JZ4780_CLK_SADC] = { > + "sadc", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 14 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 14 }, > + }, > + -> + [JZ4780_CLK_UART0] =3D { +> + [JZ4780_CLK_UART0] = { > + "uart0", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 15 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 15 }, > + }, > + -> + [JZ4780_CLK_UART1] =3D { +> + [JZ4780_CLK_UART1] = { > + "uart1", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 16 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 16 }, > + }, > + -> + [JZ4780_CLK_UART2] =3D { +> + [JZ4780_CLK_UART2] = { > + "uart2", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 17 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 17 }, > + }, > + -> + [JZ4780_CLK_UART3] =3D { +> + [JZ4780_CLK_UART3] = { > + "uart3", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 18 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 18 }, > + }, > + -> + [JZ4780_CLK_SSI1] =3D { +> + [JZ4780_CLK_SSI1] = { > + "ssi1", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_SSI, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 19 }, +> + .parents = { JZ4780_CLK_SSI, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 19 }, > + }, > + -> + [JZ4780_CLK_SSI2] =3D { +> + [JZ4780_CLK_SSI2] = { > + "ssi2", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_SSI, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 20 }, +> + .parents = { JZ4780_CLK_SSI, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 20 }, > + }, > + -> + [JZ4780_CLK_PDMA] =3D { +> + [JZ4780_CLK_PDMA] = { > + "pdma", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 21 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 21 }, > + }, > + -> + [JZ4780_CLK_GPS] =3D { +> + [JZ4780_CLK_GPS] = { > + "gps", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 22 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 22 }, > + }, > + -> + [JZ4780_CLK_MAC] =3D { +> + [JZ4780_CLK_MAC] = { > + "mac", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 23 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 23 }, > + }, > + -> + [JZ4780_CLK_SMB2] =3D { +> + [JZ4780_CLK_SMB2] = { > + "smb2", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_PCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 24 }, +> + .parents = { JZ4780_CLK_PCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 24 }, > + }, > + -> + [JZ4780_CLK_CIM] =3D { +> + [JZ4780_CLK_CIM] = { > + "cim", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 26 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 26 }, > + }, > + -> + [JZ4780_CLK_LCD] =3D { +> + [JZ4780_CLK_LCD] = { > + "lcd", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 28 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 28 }, > + }, > + -> + [JZ4780_CLK_TVE] =3D { +> + [JZ4780_CLK_TVE] = { > + "tve", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_LCD, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 27 }, +> + .parents = { JZ4780_CLK_LCD, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 27 }, > + }, > + -> + [JZ4780_CLK_IPU] =3D { +> + [JZ4780_CLK_IPU] = { > + "ipu", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 29 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 29 }, > + }, > + -> + [JZ4780_CLK_DDR0] =3D { +> + [JZ4780_CLK_DDR0] = { > + "ddr0", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_DDR, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 30 }, +> + .parents = { JZ4780_CLK_DDR, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 30 }, > + }, > + -> + [JZ4780_CLK_DDR1] =3D { +> + [JZ4780_CLK_DDR1] = { > + "ddr1", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_DDR, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 31 }, +> + .parents = { JZ4780_CLK_DDR, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 31 }, > + }, > + -> + [JZ4780_CLK_SMB3] =3D { +> + [JZ4780_CLK_SMB3] = { > + "smb3", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_PCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR1, 0 }, +> + .parents = { JZ4780_CLK_PCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR1, 0 }, > + }, > + -> + [JZ4780_CLK_TSSI1] =3D { +> + [JZ4780_CLK_TSSI1] = { > + "tssi1", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR1, 1 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR1, 1 }, > + }, > + -> + [JZ4780_CLK_COMPRESS] =3D { +> + [JZ4780_CLK_COMPRESS] = { > + "compress", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR1, 5 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR1, 5 }, > + }, > + -> + [JZ4780_CLK_AIC1] =3D { +> + [JZ4780_CLK_AIC1] = { > + "aic1", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR1, 6 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR1, 6 }, > + }, > + -> + [JZ4780_CLK_GPVLC] =3D { +> + [JZ4780_CLK_GPVLC] = { > + "gpvlc", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR1, 7 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR1, 7 }, > + }, > + -> + [JZ4780_CLK_OTG1] =3D { +> + [JZ4780_CLK_OTG1] = { > + "otg1", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR1, 8 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR1, 8 }, > + }, > + -> + [JZ4780_CLK_UART4] =3D { +> + [JZ4780_CLK_UART4] = { > + "uart4", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR1, 10 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR1, 10 }, > + }, > + -> + [JZ4780_CLK_AHBMON] =3D { +> + [JZ4780_CLK_AHBMON] = { > + "ahb_mon", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR1, 11 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR1, 11 }, > + }, > + -> + [JZ4780_CLK_SMB4] =3D { +> + [JZ4780_CLK_SMB4] = { > + "smb4", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_PCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR1, 12 }, +> + .parents = { JZ4780_CLK_PCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR1, 12 }, > + }, > + -> + [JZ4780_CLK_DES] =3D { +> + [JZ4780_CLK_DES] = { > + "des", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR1, 13 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR1, 13 }, > + }, > + -> + [JZ4780_CLK_X2D] =3D { +> + [JZ4780_CLK_X2D] = { > + "x2d", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR1, 14 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR1, 14 }, > + }, > + -> + [JZ4780_CLK_CORE1] =3D { +> + [JZ4780_CLK_CORE1] = { > + "core1", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_CPU, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR1, 15 }, +> + .parents = { JZ4780_CLK_CPU, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR1, 15 }, > + }, > + > +}; @@ -802,21 +783,20 @@ rate, > +{ > + int retval; > + -> + cgu =3D ingenic_cgu_new(jz4780_cgu_clocks, +> + cgu = ingenic_cgu_new(jz4780_cgu_clocks, > + ARRAY_SIZE(jz4780_cgu_clocks), np); > + if (!cgu) { > + pr_err("%s: failed to initialise CGU\n", __func__); > + return; > + } > + -> + retval =3D ingenic_cgu_register_clocks(cgu); +> + retval = ingenic_cgu_register_clocks(cgu); > + if (retval) { > + pr_err("%s: failed to register CGU Clocks\n", __func__); > + return; > + } > +} > +CLK_OF_DECLARE(jz4780_cgu, "ingenic,jz4780-cgu", jz4780_cgu_init); -> -- = - +> -- > 2.4.1 ->=20 +> diff --git a/a/content_digest b/N1/content_digest index 6dc895d..9edfe5f 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -16,8 +16,7 @@ "Quoting Paul Burton (2015-05-24 08:11:40)\n" "> Add support for the clocks provided by the CGU in the Ingenic JZ4780\n" "> SoC, making use of the SoC-agnostic CGU code to do the heavy lifting.\n" - "> =\n" - "\n" + "> \n" "> Signed-off-by: Paul Burton <paul.burton@imgtec.com>\n" "> Co-authored-by: Paul Cercueil <paul@crapouillou.net>\n" "> Cc: Lars-Peter Clausen <lars@metafoo.de>\n" @@ -38,15 +37,13 @@ "Mike\n" "\n" "> ---\n" - "> =\n" - "\n" + "> \n" "> Changes in v5:\n" "> - Declare jz4780_otg_phy_ops static.\n" "> - Drop setting the parent of the UHC clock during probe - USB isn't\n" "> supported as of this patchset anyway, so it can be dealt with in\n" "> whatever's deemed the best way later.\n" - "> =\n" - "\n" + "> \n" "> Changes in v4:\n" "> - Return on ingenic_cgu_new or ingenic_cgu_register_clocks failure.\n" "> - Initialise all unused clock parent fields to -1. Zero initialisation\n" @@ -56,33 +53,27 @@ "> to the clock description (which is hopefully OK). Initialising to -1\n" "> makes sense for resilience should the latter ever not be the case,\n" "> and to avoid that bit of implicit magic knowledge.\n" - "> =\n" - "\n" + "> \n" "> Changes in v3:\n" "> - Rebase.\n" - "> =\n" - "\n" + "> \n" "> Changes in v2:\n" "> - Remove FSF address per checkpatch (ZubairLK).\n" - "> =\n" - "\n" + "> \n" "> drivers/clk/ingenic/Makefile | 1 +\n" - "> drivers/clk/ingenic/jz4780-cgu.c | 733 +++++++++++++++++++++++++++++++++=\n" - "++++++\n" + "> drivers/clk/ingenic/jz4780-cgu.c | 733 +++++++++++++++++++++++++++++++++++++++\n" "> 2 files changed, 734 insertions(+)\n" "> create mode 100644 drivers/clk/ingenic/jz4780-cgu.c\n" - "> =\n" - "\n" + "> \n" "> diff --git a/drivers/clk/ingenic/Makefile b/drivers/clk/ingenic/Makefile\n" "> index e6db7da..cd47b06 100644\n" "> --- a/drivers/clk/ingenic/Makefile\n" "> +++ b/drivers/clk/ingenic/Makefile\n" "> @@ -1,2 +1,3 @@\n" - "> obj-y +=3D cgu.o\n" - "> obj-$(CONFIG_MACH_JZ4740) +=3D jz4740-cgu.o\n" - "> +obj-$(CONFIG_MACH_JZ4780) +=3D jz4780-cgu.o\n" - "> diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz478=\n" - "0-cgu.c\n" + "> obj-y += cgu.o\n" + "> obj-$(CONFIG_MACH_JZ4740) += jz4740-cgu.o\n" + "> +obj-$(CONFIG_MACH_JZ4780) += jz4780-cgu.o\n" + "> diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c\n" "> new file mode 100644\n" "> index 0000000..431f962\n" "> --- /dev/null\n" @@ -203,10 +194,10 @@ "> +\n" "> + spin_lock_irqsave(&cgu->lock, flags);\n" "> +\n" - "> + usbpcr1 =3D readl(cgu->base + CGU_REG_USBPCR1);\n" - "> + usbpcr1 &=3D ~USBPCR1_REFCLKSEL_MASK;\n" + "> + usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1);\n" + "> + usbpcr1 &= ~USBPCR1_REFCLKSEL_MASK;\n" "> + /* we only use CLKCORE */\n" - "> + usbpcr1 |=3D USBPCR1_REFCLKSEL_CORE;\n" + "> + usbpcr1 |= USBPCR1_REFCLKSEL_CORE;\n" "> + writel(usbpcr1, cgu->base + CGU_REG_USBPCR1);\n" "> +\n" "> + spin_unlock_irqrestore(&cgu->lock, flags);\n" @@ -219,8 +210,8 @@ "> + u32 usbpcr1;\n" "> + unsigned refclk_div;\n" "> +\n" - "> + usbpcr1 =3D readl(cgu->base + CGU_REG_USBPCR1);\n" - "> + refclk_div =3D usbpcr1 & USBPCR1_REFCLKDIV_MASK;\n" + "> + usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1);\n" + "> + refclk_div = usbpcr1 & USBPCR1_REFCLKDIV_MASK;\n" "> +\n" "> + switch (refclk_div) {\n" "> + case USBPCR1_REFCLKDIV_12:\n" @@ -240,8 +231,7 @@ "> + return parent_rate;\n" "> +}\n" "> +\n" - "> +static long jz4780_otg_phy_round_rate(struct clk_hw *hw, unsigned long r=\n" - "eq_rate,\n" + "> +static long jz4780_otg_phy_round_rate(struct clk_hw *hw, unsigned long req_rate,\n" "> + unsigned long *parent_rate)\n" "> +{\n" "> + if (req_rate < 15600000)\n" @@ -256,8 +246,7 @@ "> + return 48000000;\n" "> +}\n" "> +\n" - "> +static int jz4780_otg_phy_set_rate(struct clk_hw *hw, unsigned long req_=\n" - "rate,\n" + "> +static int jz4780_otg_phy_set_rate(struct clk_hw *hw, unsigned long req_rate,\n" "> + unsigned long parent_rate)\n" "> +{\n" "> + unsigned long flags;\n" @@ -265,19 +254,19 @@ "> +\n" "> + switch (req_rate) {\n" "> + case 12000000:\n" - "> + div_bits =3D USBPCR1_REFCLKDIV_12;\n" + "> + div_bits = USBPCR1_REFCLKDIV_12;\n" "> + break;\n" "> +\n" "> + case 19200000:\n" - "> + div_bits =3D USBPCR1_REFCLKDIV_19_2;\n" + "> + div_bits = USBPCR1_REFCLKDIV_19_2;\n" "> + break;\n" "> +\n" "> + case 24000000:\n" - "> + div_bits =3D USBPCR1_REFCLKDIV_24;\n" + "> + div_bits = USBPCR1_REFCLKDIV_24;\n" "> + break;\n" "> +\n" "> + case 48000000:\n" - "> + div_bits =3D USBPCR1_REFCLKDIV_48;\n" + "> + div_bits = USBPCR1_REFCLKDIV_48;\n" "> + break;\n" "> +\n" "> + default:\n" @@ -286,529 +275,521 @@ "> +\n" "> + spin_lock_irqsave(&cgu->lock, flags);\n" "> +\n" - "> + usbpcr1 =3D readl(cgu->base + CGU_REG_USBPCR1);\n" - "> + usbpcr1 &=3D ~USBPCR1_REFCLKDIV_MASK;\n" - "> + usbpcr1 |=3D div_bits;\n" + "> + usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1);\n" + "> + usbpcr1 &= ~USBPCR1_REFCLKDIV_MASK;\n" + "> + usbpcr1 |= div_bits;\n" "> + writel(usbpcr1, cgu->base + CGU_REG_USBPCR1);\n" "> +\n" "> + spin_unlock_irqrestore(&cgu->lock, flags);\n" "> + return 0;\n" "> +}\n" "> +\n" - "> +static struct clk_ops jz4780_otg_phy_ops =3D {\n" - "> + .get_parent =3D jz4780_otg_phy_get_parent,\n" - "> + .set_parent =3D jz4780_otg_phy_set_parent,\n" + "> +static struct clk_ops jz4780_otg_phy_ops = {\n" + "> + .get_parent = jz4780_otg_phy_get_parent,\n" + "> + .set_parent = jz4780_otg_phy_set_parent,\n" "> +\n" - "> + .recalc_rate =3D jz4780_otg_phy_recalc_rate,\n" - "> + .round_rate =3D jz4780_otg_phy_round_rate,\n" - "> + .set_rate =3D jz4780_otg_phy_set_rate,\n" + "> + .recalc_rate = jz4780_otg_phy_recalc_rate,\n" + "> + .round_rate = jz4780_otg_phy_round_rate,\n" + "> + .set_rate = jz4780_otg_phy_set_rate,\n" "> +};\n" "> +\n" - "> +static const s8 pll_od_encoding[16] =3D {\n" + "> +static const s8 pll_od_encoding[16] = {\n" "> + 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7,\n" "> + 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,\n" "> +};\n" "> +\n" - "> +static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] =3D {\n" + "> +static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = {\n" "> +\n" "> + /* External clocks */\n" "> +\n" - "> + [JZ4780_CLK_EXCLK] =3D { \"ext\", CGU_CLK_EXT },\n" - "> + [JZ4780_CLK_RTCLK] =3D { \"rtc\", CGU_CLK_EXT },\n" + "> + [JZ4780_CLK_EXCLK] = { \"ext\", CGU_CLK_EXT },\n" + "> + [JZ4780_CLK_RTCLK] = { \"rtc\", CGU_CLK_EXT },\n" "> +\n" "> + /* PLLs */\n" "> +\n" "> +#define DEF_PLL(name) { \\\n" - "> + .reg =3D CGU_REG_ ## name, \\\n" - "> + .m_shift =3D 19, \\\n" - "> + .m_bits =3D 13, \\\n" - "> + .m_offset =3D 1, \\\n" - "> + .n_shift =3D 13, \\\n" - "> + .n_bits =3D 6, \\\n" - "> + .n_offset =3D 1, \\\n" - "> + .od_shift =3D 9, \\\n" - "> + .od_bits =3D 4, \\\n" - "> + .od_max =3D 16, \\\n" - "> + .od_encoding =3D pll_od_encoding, \\\n" - "> + .stable_bit =3D 6, \\\n" - "> + .bypass_bit =3D 1, \\\n" - "> + .enable_bit =3D 0, \\\n" + "> + .reg = CGU_REG_ ## name, \\\n" + "> + .m_shift = 19, \\\n" + "> + .m_bits = 13, \\\n" + "> + .m_offset = 1, \\\n" + "> + .n_shift = 13, \\\n" + "> + .n_bits = 6, \\\n" + "> + .n_offset = 1, \\\n" + "> + .od_shift = 9, \\\n" + "> + .od_bits = 4, \\\n" + "> + .od_max = 16, \\\n" + "> + .od_encoding = pll_od_encoding, \\\n" + "> + .stable_bit = 6, \\\n" + "> + .bypass_bit = 1, \\\n" + "> + .enable_bit = 0, \\\n" "> +}\n" "> +\n" - "> + [JZ4780_CLK_APLL] =3D {\n" + "> + [JZ4780_CLK_APLL] = {\n" "> + \"apll\", CGU_CLK_PLL,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .pll =3D DEF_PLL(APLL),\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .pll = DEF_PLL(APLL),\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_MPLL] =3D {\n" + "> + [JZ4780_CLK_MPLL] = {\n" "> + \"mpll\", CGU_CLK_PLL,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .pll =3D DEF_PLL(MPLL),\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .pll = DEF_PLL(MPLL),\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_EPLL] =3D {\n" + "> + [JZ4780_CLK_EPLL] = {\n" "> + \"epll\", CGU_CLK_PLL,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .pll =3D DEF_PLL(EPLL),\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .pll = DEF_PLL(EPLL),\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_VPLL] =3D {\n" + "> + [JZ4780_CLK_VPLL] = {\n" "> + \"vpll\", CGU_CLK_PLL,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .pll =3D DEF_PLL(VPLL),\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .pll = DEF_PLL(VPLL),\n" "> + },\n" "> +\n" "> +#undef DEF_PLL\n" "> +\n" "> + /* Custom (SoC-specific) OTG PHY */\n" "> +\n" - "> + [JZ4780_CLK_OTGPHY] =3D {\n" + "> + [JZ4780_CLK_OTGPHY] = {\n" "> + \"otg_phy\", CGU_CLK_CUSTOM,\n" - "> + .parents =3D { -1, -1, JZ4780_CLK_EXCLK, -1 },\n" - "> + .custom =3D { &jz4780_otg_phy_ops },\n" + "> + .parents = { -1, -1, JZ4780_CLK_EXCLK, -1 },\n" + "> + .custom = { &jz4780_otg_phy_ops },\n" "> + },\n" "> +\n" "> + /* Muxes & dividers */\n" "> +\n" - "> + [JZ4780_CLK_SCLKA] =3D {\n" + "> + [JZ4780_CLK_SCLKA] = {\n" "> + \"sclk_a\", CGU_CLK_MUX,\n" - "> + .parents =3D { -1, JZ4780_CLK_APLL, JZ4780_CLK_EXCLK,\n" + "> + .parents = { -1, JZ4780_CLK_APLL, JZ4780_CLK_EXCLK,\n" "> + JZ4780_CLK_RTCLK },\n" - "> + .mux =3D { CGU_REG_CLOCKCONTROL, 30, 2 },\n" + "> + .mux = { CGU_REG_CLOCKCONTROL, 30, 2 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_CPUMUX] =3D {\n" + "> + [JZ4780_CLK_CPUMUX] = {\n" "> + \"cpumux\", CGU_CLK_MUX,\n" - "> + .parents =3D { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" + "> + .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" "> + JZ4780_CLK_EPLL },\n" - "> + .mux =3D { CGU_REG_CLOCKCONTROL, 28, 2 },\n" + "> + .mux = { CGU_REG_CLOCKCONTROL, 28, 2 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_CPU] =3D {\n" + "> + [JZ4780_CLK_CPU] = {\n" "> + \"cpu\", CGU_CLK_DIV,\n" - "> + .parents =3D { JZ4780_CLK_CPUMUX, -1, -1, -1 },\n" - "> + .div =3D { CGU_REG_CLOCKCONTROL, 0, 4, 22, -1, -1 },\n" + "> + .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },\n" + "> + .div = { CGU_REG_CLOCKCONTROL, 0, 4, 22, -1, -1 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_L2CACHE] =3D {\n" + "> + [JZ4780_CLK_L2CACHE] = {\n" "> + \"l2cache\", CGU_CLK_DIV,\n" - "> + .parents =3D { JZ4780_CLK_CPUMUX, -1, -1, -1 },\n" - "> + .div =3D { CGU_REG_CLOCKCONTROL, 4, 4, -1, -1, -1 },\n" + "> + .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },\n" + "> + .div = { CGU_REG_CLOCKCONTROL, 4, 4, -1, -1, -1 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_AHB0] =3D {\n" + "> + [JZ4780_CLK_AHB0] = {\n" "> + \"ahb0\", CGU_CLK_MUX | CGU_CLK_DIV,\n" - "> + .parents =3D { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" + "> + .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" "> + JZ4780_CLK_EPLL },\n" - "> + .mux =3D { CGU_REG_CLOCKCONTROL, 26, 2 },\n" - "> + .div =3D { CGU_REG_CLOCKCONTROL, 8, 4, 21, -1, -1 },\n" + "> + .mux = { CGU_REG_CLOCKCONTROL, 26, 2 },\n" + "> + .div = { CGU_REG_CLOCKCONTROL, 8, 4, 21, -1, -1 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_AHB2PMUX] =3D {\n" + "> + [JZ4780_CLK_AHB2PMUX] = {\n" "> + \"ahb2_apb_mux\", CGU_CLK_MUX,\n" - "> + .parents =3D { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" + "> + .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" "> + JZ4780_CLK_RTCLK },\n" - "> + .mux =3D { CGU_REG_CLOCKCONTROL, 24, 2 },\n" + "> + .mux = { CGU_REG_CLOCKCONTROL, 24, 2 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_AHB2] =3D {\n" + "> + [JZ4780_CLK_AHB2] = {\n" "> + \"ahb2\", CGU_CLK_DIV,\n" - "> + .parents =3D { JZ4780_CLK_AHB2PMUX, -1, -1, -1 },\n" - "> + .div =3D { CGU_REG_CLOCKCONTROL, 12, 4, 20, -1, -1 },\n" + "> + .parents = { JZ4780_CLK_AHB2PMUX, -1, -1, -1 },\n" + "> + .div = { CGU_REG_CLOCKCONTROL, 12, 4, 20, -1, -1 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_PCLK] =3D {\n" + "> + [JZ4780_CLK_PCLK] = {\n" "> + \"pclk\", CGU_CLK_DIV,\n" - "> + .parents =3D { JZ4780_CLK_AHB2PMUX, -1, -1, -1 },\n" - "> + .div =3D { CGU_REG_CLOCKCONTROL, 16, 4, 20, -1, -1 },\n" + "> + .parents = { JZ4780_CLK_AHB2PMUX, -1, -1, -1 },\n" + "> + .div = { CGU_REG_CLOCKCONTROL, 16, 4, 20, -1, -1 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_DDR] =3D {\n" + "> + [JZ4780_CLK_DDR] = {\n" "> + \"ddr\", CGU_CLK_MUX | CGU_CLK_DIV,\n" - "> + .parents =3D { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 =\n" - "},\n" - "> + .mux =3D { CGU_REG_DDRCDR, 30, 2 },\n" - "> + .div =3D { CGU_REG_DDRCDR, 0, 4, 29, 28, 27 },\n" + "> + .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 },\n" + "> + .mux = { CGU_REG_DDRCDR, 30, 2 },\n" + "> + .div = { CGU_REG_DDRCDR, 0, 4, 29, 28, 27 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_VPU] =3D {\n" + "> + [JZ4780_CLK_VPU] = {\n" "> + \"vpu\", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" + "> + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" "> + JZ4780_CLK_EPLL, -1 },\n" - "> + .mux =3D { CGU_REG_VPUCDR, 30, 2 },\n" - "> + .div =3D { CGU_REG_VPUCDR, 0, 4, 29, 28, 27 },\n" - "> + .gate =3D { CGU_REG_CLKGR1, 2 },\n" + "> + .mux = { CGU_REG_VPUCDR, 30, 2 },\n" + "> + .div = { CGU_REG_VPUCDR, 0, 4, 29, 28, 27 },\n" + "> + .gate = { CGU_REG_CLKGR1, 2 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_I2SPLL] =3D {\n" + "> + [JZ4780_CLK_I2SPLL] = {\n" "> + \"i2s_pll\", CGU_CLK_MUX | CGU_CLK_DIV,\n" - "> + .parents =3D { JZ4780_CLK_SCLKA, JZ4780_CLK_EPLL, -1, -1 =\n" - "},\n" - "> + .mux =3D { CGU_REG_I2SCDR, 30, 1 },\n" - "> + .div =3D { CGU_REG_I2SCDR, 0, 8, 29, 28, 27 },\n" + "> + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_EPLL, -1, -1 },\n" + "> + .mux = { CGU_REG_I2SCDR, 30, 1 },\n" + "> + .div = { CGU_REG_I2SCDR, 0, 8, 29, 28, 27 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_I2S] =3D {\n" + "> + [JZ4780_CLK_I2S] = {\n" "> + \"i2s\", CGU_CLK_MUX,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, JZ4780_CLK_I2SPLL, -1, -=\n" - "1 },\n" - "> + .mux =3D { CGU_REG_I2SCDR, 31, 1 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_I2SPLL, -1, -1 },\n" + "> + .mux = { CGU_REG_I2SCDR, 31, 1 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_LCD0PIXCLK] =3D {\n" + "> + [JZ4780_CLK_LCD0PIXCLK] = {\n" "> + \"lcd0pixclk\", CGU_CLK_MUX | CGU_CLK_DIV,\n" - "> + .parents =3D { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" + "> + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" "> + JZ4780_CLK_VPLL, -1 },\n" - "> + .mux =3D { CGU_REG_LP0CDR, 30, 2 },\n" - "> + .div =3D { CGU_REG_LP0CDR, 0, 8, 28, 27, 26 },\n" + "> + .mux = { CGU_REG_LP0CDR, 30, 2 },\n" + "> + .div = { CGU_REG_LP0CDR, 0, 8, 28, 27, 26 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_LCD1PIXCLK] =3D {\n" + "> + [JZ4780_CLK_LCD1PIXCLK] = {\n" "> + \"lcd1pixclk\", CGU_CLK_MUX | CGU_CLK_DIV,\n" - "> + .parents =3D { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" + "> + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" "> + JZ4780_CLK_VPLL, -1 },\n" - "> + .mux =3D { CGU_REG_LP1CDR, 30, 2 },\n" - "> + .div =3D { CGU_REG_LP1CDR, 0, 8, 28, 27, 26 },\n" + "> + .mux = { CGU_REG_LP1CDR, 30, 2 },\n" + "> + .div = { CGU_REG_LP1CDR, 0, 8, 28, 27, 26 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_MSCMUX] =3D {\n" + "> + [JZ4780_CLK_MSCMUX] = {\n" "> + \"msc_mux\", CGU_CLK_MUX,\n" - "> + .parents =3D { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 =\n" - "},\n" - "> + .mux =3D { CGU_REG_MSC0CDR, 30, 2 },\n" + "> + .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 },\n" + "> + .mux = { CGU_REG_MSC0CDR, 30, 2 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_MSC0] =3D {\n" + "> + [JZ4780_CLK_MSC0] = {\n" "> + \"msc0\", CGU_CLK_DIV | CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_MSCMUX, -1, -1, -1 },\n" - "> + .div =3D { CGU_REG_MSC0CDR, 0, 8, 29, 28, 27 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 3 },\n" + "> + .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 },\n" + "> + .div = { CGU_REG_MSC0CDR, 0, 8, 29, 28, 27 },\n" + "> + .gate = { CGU_REG_CLKGR0, 3 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_MSC1] =3D {\n" + "> + [JZ4780_CLK_MSC1] = {\n" "> + \"msc1\", CGU_CLK_DIV | CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_MSCMUX, -1, -1, -1 },\n" - "> + .div =3D { CGU_REG_MSC1CDR, 0, 8, 29, 28, 27 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 11 },\n" + "> + .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 },\n" + "> + .div = { CGU_REG_MSC1CDR, 0, 8, 29, 28, 27 },\n" + "> + .gate = { CGU_REG_CLKGR0, 11 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_MSC2] =3D {\n" + "> + [JZ4780_CLK_MSC2] = {\n" "> + \"msc2\", CGU_CLK_DIV | CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_MSCMUX, -1, -1, -1 },\n" - "> + .div =3D { CGU_REG_MSC2CDR, 0, 8, 29, 28, 27 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 12 },\n" + "> + .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 },\n" + "> + .div = { CGU_REG_MSC2CDR, 0, 8, 29, 28, 27 },\n" + "> + .gate = { CGU_REG_CLKGR0, 12 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_UHC] =3D {\n" + "> + [JZ4780_CLK_UHC] = {\n" "> + \"uhc\", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" + "> + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" "> + JZ4780_CLK_EPLL, JZ4780_CLK_OTGPHY },\n" - "> + .mux =3D { CGU_REG_UHCCDR, 30, 2 },\n" - "> + .div =3D { CGU_REG_UHCCDR, 0, 8, 29, 28, 27 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 24 },\n" + "> + .mux = { CGU_REG_UHCCDR, 30, 2 },\n" + "> + .div = { CGU_REG_UHCCDR, 0, 8, 29, 28, 27 },\n" + "> + .gate = { CGU_REG_CLKGR0, 24 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_SSIPLL] =3D {\n" + "> + [JZ4780_CLK_SSIPLL] = {\n" "> + \"ssi_pll\", CGU_CLK_MUX | CGU_CLK_DIV,\n" - "> + .parents =3D { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 =\n" - "},\n" - "> + .mux =3D { CGU_REG_SSICDR, 30, 1 },\n" - "> + .div =3D { CGU_REG_SSICDR, 0, 8, 29, 28, 27 },\n" + "> + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 },\n" + "> + .mux = { CGU_REG_SSICDR, 30, 1 },\n" + "> + .div = { CGU_REG_SSICDR, 0, 8, 29, 28, 27 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_SSI] =3D {\n" + "> + [JZ4780_CLK_SSI] = {\n" "> + \"ssi\", CGU_CLK_MUX,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, JZ4780_CLK_SSIPLL, -1, -=\n" - "1 },\n" - "> + .mux =3D { CGU_REG_SSICDR, 31, 1 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_SSIPLL, -1, -1 },\n" + "> + .mux = { CGU_REG_SSICDR, 31, 1 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_CIMMCLK] =3D {\n" + "> + [JZ4780_CLK_CIMMCLK] = {\n" "> + \"cim_mclk\", CGU_CLK_MUX | CGU_CLK_DIV,\n" - "> + .parents =3D { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 =\n" - "},\n" - "> + .mux =3D { CGU_REG_CIMCDR, 31, 1 },\n" - "> + .div =3D { CGU_REG_CIMCDR, 0, 8, 30, 29, 28 },\n" + "> + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 },\n" + "> + .mux = { CGU_REG_CIMCDR, 31, 1 },\n" + "> + .div = { CGU_REG_CIMCDR, 0, 8, 30, 29, 28 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_PCMPLL] =3D {\n" + "> + [JZ4780_CLK_PCMPLL] = {\n" "> + \"pcm_pll\", CGU_CLK_MUX | CGU_CLK_DIV,\n" - "> + .parents =3D { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" + "> + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" "> + JZ4780_CLK_EPLL, JZ4780_CLK_VPLL },\n" - "> + .mux =3D { CGU_REG_PCMCDR, 29, 2 },\n" - "> + .div =3D { CGU_REG_PCMCDR, 0, 8, 28, 27, 26 },\n" + "> + .mux = { CGU_REG_PCMCDR, 29, 2 },\n" + "> + .div = { CGU_REG_PCMCDR, 0, 8, 28, 27, 26 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_PCM] =3D {\n" + "> + [JZ4780_CLK_PCM] = {\n" "> + \"pcm\", CGU_CLK_MUX | CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, JZ4780_CLK_PCMPLL, -1, -=\n" - "1 },\n" - "> + .mux =3D { CGU_REG_PCMCDR, 31, 1 },\n" - "> + .gate =3D { CGU_REG_CLKGR1, 3 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_PCMPLL, -1, -1 },\n" + "> + .mux = { CGU_REG_PCMCDR, 31, 1 },\n" + "> + .gate = { CGU_REG_CLKGR1, 3 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_GPU] =3D {\n" + "> + [JZ4780_CLK_GPU] = {\n" "> + \"gpu\", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,\n" - "> + .parents =3D { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" + "> + .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" "> + JZ4780_CLK_EPLL },\n" - "> + .mux =3D { CGU_REG_GPUCDR, 30, 2 },\n" - "> + .div =3D { CGU_REG_GPUCDR, 0, 4, 29, 28, 27 },\n" - "> + .gate =3D { CGU_REG_CLKGR1, 4 },\n" + "> + .mux = { CGU_REG_GPUCDR, 30, 2 },\n" + "> + .div = { CGU_REG_GPUCDR, 0, 4, 29, 28, 27 },\n" + "> + .gate = { CGU_REG_CLKGR1, 4 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_HDMI] =3D {\n" + "> + [JZ4780_CLK_HDMI] = {\n" "> + \"hdmi\", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" + "> + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" "> + JZ4780_CLK_VPLL, -1 },\n" - "> + .mux =3D { CGU_REG_HDMICDR, 30, 2 },\n" - "> + .div =3D { CGU_REG_HDMICDR, 0, 8, 29, 28, 26 },\n" - "> + .gate =3D { CGU_REG_CLKGR1, 9 },\n" + "> + .mux = { CGU_REG_HDMICDR, 30, 2 },\n" + "> + .div = { CGU_REG_HDMICDR, 0, 8, 29, 28, 26 },\n" + "> + .gate = { CGU_REG_CLKGR1, 9 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_BCH] =3D {\n" + "> + [JZ4780_CLK_BCH] = {\n" "> + \"bch\", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,\n" - "> + .parents =3D { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" + "> + .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" "> + JZ4780_CLK_EPLL },\n" - "> + .mux =3D { CGU_REG_BCHCDR, 30, 2 },\n" - "> + .div =3D { CGU_REG_BCHCDR, 0, 4, 29, 28, 27 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 1 },\n" + "> + .mux = { CGU_REG_BCHCDR, 30, 2 },\n" + "> + .div = { CGU_REG_BCHCDR, 0, 4, 29, 28, 27 },\n" + "> + .gate = { CGU_REG_CLKGR0, 1 },\n" "> + },\n" "> +\n" "> + /* Gate-only clocks */\n" "> +\n" - "> + [JZ4780_CLK_NEMC] =3D {\n" + "> + [JZ4780_CLK_NEMC] = {\n" "> + \"nemc\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_AHB2, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 0 },\n" + "> + .parents = { JZ4780_CLK_AHB2, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 0 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_OTG0] =3D {\n" + "> + [JZ4780_CLK_OTG0] = {\n" "> + \"otg0\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 2 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 2 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_SSI0] =3D {\n" + "> + [JZ4780_CLK_SSI0] = {\n" "> + \"ssi0\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_SSI, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 4 },\n" + "> + .parents = { JZ4780_CLK_SSI, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 4 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_SMB0] =3D {\n" + "> + [JZ4780_CLK_SMB0] = {\n" "> + \"smb0\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_PCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 5 },\n" + "> + .parents = { JZ4780_CLK_PCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 5 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_SMB1] =3D {\n" + "> + [JZ4780_CLK_SMB1] = {\n" "> + \"smb1\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_PCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 6 },\n" + "> + .parents = { JZ4780_CLK_PCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 6 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_SCC] =3D {\n" + "> + [JZ4780_CLK_SCC] = {\n" "> + \"scc\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 7 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 7 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_AIC] =3D {\n" + "> + [JZ4780_CLK_AIC] = {\n" "> + \"aic\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 8 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 8 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_TSSI0] =3D {\n" + "> + [JZ4780_CLK_TSSI0] = {\n" "> + \"tssi0\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 9 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 9 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_OWI] =3D {\n" + "> + [JZ4780_CLK_OWI] = {\n" "> + \"owi\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 10 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 10 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_KBC] =3D {\n" + "> + [JZ4780_CLK_KBC] = {\n" "> + \"kbc\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 13 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 13 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_SADC] =3D {\n" + "> + [JZ4780_CLK_SADC] = {\n" "> + \"sadc\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 14 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 14 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_UART0] =3D {\n" + "> + [JZ4780_CLK_UART0] = {\n" "> + \"uart0\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 15 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 15 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_UART1] =3D {\n" + "> + [JZ4780_CLK_UART1] = {\n" "> + \"uart1\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 16 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 16 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_UART2] =3D {\n" + "> + [JZ4780_CLK_UART2] = {\n" "> + \"uart2\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 17 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 17 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_UART3] =3D {\n" + "> + [JZ4780_CLK_UART3] = {\n" "> + \"uart3\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 18 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 18 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_SSI1] =3D {\n" + "> + [JZ4780_CLK_SSI1] = {\n" "> + \"ssi1\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_SSI, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 19 },\n" + "> + .parents = { JZ4780_CLK_SSI, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 19 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_SSI2] =3D {\n" + "> + [JZ4780_CLK_SSI2] = {\n" "> + \"ssi2\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_SSI, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 20 },\n" + "> + .parents = { JZ4780_CLK_SSI, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 20 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_PDMA] =3D {\n" + "> + [JZ4780_CLK_PDMA] = {\n" "> + \"pdma\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 21 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 21 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_GPS] =3D {\n" + "> + [JZ4780_CLK_GPS] = {\n" "> + \"gps\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 22 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 22 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_MAC] =3D {\n" + "> + [JZ4780_CLK_MAC] = {\n" "> + \"mac\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 23 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 23 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_SMB2] =3D {\n" + "> + [JZ4780_CLK_SMB2] = {\n" "> + \"smb2\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_PCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 24 },\n" + "> + .parents = { JZ4780_CLK_PCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 24 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_CIM] =3D {\n" + "> + [JZ4780_CLK_CIM] = {\n" "> + \"cim\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 26 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 26 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_LCD] =3D {\n" + "> + [JZ4780_CLK_LCD] = {\n" "> + \"lcd\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 28 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 28 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_TVE] =3D {\n" + "> + [JZ4780_CLK_TVE] = {\n" "> + \"tve\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_LCD, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 27 },\n" + "> + .parents = { JZ4780_CLK_LCD, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 27 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_IPU] =3D {\n" + "> + [JZ4780_CLK_IPU] = {\n" "> + \"ipu\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 29 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 29 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_DDR0] =3D {\n" + "> + [JZ4780_CLK_DDR0] = {\n" "> + \"ddr0\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_DDR, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 30 },\n" + "> + .parents = { JZ4780_CLK_DDR, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 30 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_DDR1] =3D {\n" + "> + [JZ4780_CLK_DDR1] = {\n" "> + \"ddr1\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_DDR, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 31 },\n" + "> + .parents = { JZ4780_CLK_DDR, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 31 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_SMB3] =3D {\n" + "> + [JZ4780_CLK_SMB3] = {\n" "> + \"smb3\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_PCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR1, 0 },\n" + "> + .parents = { JZ4780_CLK_PCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR1, 0 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_TSSI1] =3D {\n" + "> + [JZ4780_CLK_TSSI1] = {\n" "> + \"tssi1\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR1, 1 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR1, 1 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_COMPRESS] =3D {\n" + "> + [JZ4780_CLK_COMPRESS] = {\n" "> + \"compress\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR1, 5 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR1, 5 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_AIC1] =3D {\n" + "> + [JZ4780_CLK_AIC1] = {\n" "> + \"aic1\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR1, 6 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR1, 6 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_GPVLC] =3D {\n" + "> + [JZ4780_CLK_GPVLC] = {\n" "> + \"gpvlc\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR1, 7 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR1, 7 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_OTG1] =3D {\n" + "> + [JZ4780_CLK_OTG1] = {\n" "> + \"otg1\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR1, 8 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR1, 8 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_UART4] =3D {\n" + "> + [JZ4780_CLK_UART4] = {\n" "> + \"uart4\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR1, 10 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR1, 10 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_AHBMON] =3D {\n" + "> + [JZ4780_CLK_AHBMON] = {\n" "> + \"ahb_mon\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR1, 11 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR1, 11 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_SMB4] =3D {\n" + "> + [JZ4780_CLK_SMB4] = {\n" "> + \"smb4\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_PCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR1, 12 },\n" + "> + .parents = { JZ4780_CLK_PCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR1, 12 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_DES] =3D {\n" + "> + [JZ4780_CLK_DES] = {\n" "> + \"des\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR1, 13 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR1, 13 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_X2D] =3D {\n" + "> + [JZ4780_CLK_X2D] = {\n" "> + \"x2d\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR1, 14 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR1, 14 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_CORE1] =3D {\n" + "> + [JZ4780_CLK_CORE1] = {\n" "> + \"core1\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_CPU, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR1, 15 },\n" + "> + .parents = { JZ4780_CLK_CPU, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR1, 15 },\n" "> + },\n" "> +\n" "> +};\n" @@ -817,23 +798,22 @@ "> +{\n" "> + int retval;\n" "> +\n" - "> + cgu =3D ingenic_cgu_new(jz4780_cgu_clocks,\n" + "> + cgu = ingenic_cgu_new(jz4780_cgu_clocks,\n" "> + ARRAY_SIZE(jz4780_cgu_clocks), np);\n" "> + if (!cgu) {\n" "> + pr_err(\"%s: failed to initialise CGU\\n\", __func__);\n" "> + return;\n" "> + }\n" "> +\n" - "> + retval =3D ingenic_cgu_register_clocks(cgu);\n" + "> + retval = ingenic_cgu_register_clocks(cgu);\n" "> + if (retval) {\n" "> + pr_err(\"%s: failed to register CGU Clocks\\n\", __func__);\n" "> + return;\n" "> + }\n" "> +}\n" "> +CLK_OF_DECLARE(jz4780_cgu, \"ingenic,jz4780-cgu\", jz4780_cgu_init);\n" - "> -- =\n" - "\n" + "> -- \n" "> 2.4.1\n" - >=20 + > -2be9843f9d9e5a56ce9e5035a73c987f91050d5e02b9cd1d06b4efc7dcfe6c09 +c4feb42acbe7e6286705a27c75cf4d8bae7c4365fe168af1a6c0aa3463b7a434
diff --git a/a/1.txt b/N2/1.txt index 0c9ccf5..01aacba 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,8 +1,7 @@ Quoting Paul Burton (2015-05-24 08:11:40) > Add support for the clocks provided by the CGU in the Ingenic JZ4780 > SoC, making use of the SoC-agnostic CGU code to do the heavy lifting. -> = - +> > Signed-off-by: Paul Burton <paul.burton@imgtec.com> > Co-authored-by: Paul Cercueil <paul@crapouillou.net> > Cc: Lars-Peter Clausen <lars@metafoo.de> @@ -23,15 +22,13 @@ Regards, Mike > --- -> = - +> > Changes in v5: > - Declare jz4780_otg_phy_ops static. > - Drop setting the parent of the UHC clock during probe - USB isn't > supported as of this patchset anyway, so it can be dealt with in > whatever's deemed the best way later. -> = - +> > Changes in v4: > - Return on ingenic_cgu_new or ingenic_cgu_register_clocks failure. > - Initialise all unused clock parent fields to -1. Zero initialisation @@ -41,33 +38,27 @@ Mike > to the clock description (which is hopefully OK). Initialising to -1 > makes sense for resilience should the latter ever not be the case, > and to avoid that bit of implicit magic knowledge. -> = - +> > Changes in v3: > - Rebase. -> = - +> > Changes in v2: > - Remove FSF address per checkpatch (ZubairLK). -> = - +> > drivers/clk/ingenic/Makefile | 1 + -> drivers/clk/ingenic/jz4780-cgu.c | 733 +++++++++++++++++++++++++++++++++= -++++++ +> drivers/clk/ingenic/jz4780-cgu.c | 733 +++++++++++++++++++++++++++++++++++++++ > 2 files changed, 734 insertions(+) > create mode 100644 drivers/clk/ingenic/jz4780-cgu.c -> = - +> > diff --git a/drivers/clk/ingenic/Makefile b/drivers/clk/ingenic/Makefile > index e6db7da..cd47b06 100644 > --- a/drivers/clk/ingenic/Makefile > +++ b/drivers/clk/ingenic/Makefile > @@ -1,2 +1,3 @@ -> obj-y +=3D cgu.o -> obj-$(CONFIG_MACH_JZ4740) +=3D jz4740-cgu.o -> +obj-$(CONFIG_MACH_JZ4780) +=3D jz4780-cgu.o -> diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz478= -0-cgu.c +> obj-y += cgu.o +> obj-$(CONFIG_MACH_JZ4740) += jz4740-cgu.o +> +obj-$(CONFIG_MACH_JZ4780) += jz4780-cgu.o +> diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c > new file mode 100644 > index 0000000..431f962 > --- /dev/null @@ -188,10 +179,10 @@ Mike > + > + spin_lock_irqsave(&cgu->lock, flags); > + -> + usbpcr1 =3D readl(cgu->base + CGU_REG_USBPCR1); -> + usbpcr1 &=3D ~USBPCR1_REFCLKSEL_MASK; +> + usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); +> + usbpcr1 &= ~USBPCR1_REFCLKSEL_MASK; > + /* we only use CLKCORE */ -> + usbpcr1 |=3D USBPCR1_REFCLKSEL_CORE; +> + usbpcr1 |= USBPCR1_REFCLKSEL_CORE; > + writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); > + > + spin_unlock_irqrestore(&cgu->lock, flags); @@ -204,8 +195,8 @@ Mike > + u32 usbpcr1; > + unsigned refclk_div; > + -> + usbpcr1 =3D readl(cgu->base + CGU_REG_USBPCR1); -> + refclk_div =3D usbpcr1 & USBPCR1_REFCLKDIV_MASK; +> + usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); +> + refclk_div = usbpcr1 & USBPCR1_REFCLKDIV_MASK; > + > + switch (refclk_div) { > + case USBPCR1_REFCLKDIV_12: @@ -225,8 +216,7 @@ Mike > + return parent_rate; > +} > + -> +static long jz4780_otg_phy_round_rate(struct clk_hw *hw, unsigned long r= -eq_rate, +> +static long jz4780_otg_phy_round_rate(struct clk_hw *hw, unsigned long req_rate, > + unsigned long *parent_rate) > +{ > + if (req_rate < 15600000) @@ -241,8 +231,7 @@ eq_rate, > + return 48000000; > +} > + -> +static int jz4780_otg_phy_set_rate(struct clk_hw *hw, unsigned long req_= -rate, +> +static int jz4780_otg_phy_set_rate(struct clk_hw *hw, unsigned long req_rate, > + unsigned long parent_rate) > +{ > + unsigned long flags; @@ -250,19 +239,19 @@ rate, > + > + switch (req_rate) { > + case 12000000: -> + div_bits =3D USBPCR1_REFCLKDIV_12; +> + div_bits = USBPCR1_REFCLKDIV_12; > + break; > + > + case 19200000: -> + div_bits =3D USBPCR1_REFCLKDIV_19_2; +> + div_bits = USBPCR1_REFCLKDIV_19_2; > + break; > + > + case 24000000: -> + div_bits =3D USBPCR1_REFCLKDIV_24; +> + div_bits = USBPCR1_REFCLKDIV_24; > + break; > + > + case 48000000: -> + div_bits =3D USBPCR1_REFCLKDIV_48; +> + div_bits = USBPCR1_REFCLKDIV_48; > + break; > + > + default: @@ -271,529 +260,521 @@ rate, > + > + spin_lock_irqsave(&cgu->lock, flags); > + -> + usbpcr1 =3D readl(cgu->base + CGU_REG_USBPCR1); -> + usbpcr1 &=3D ~USBPCR1_REFCLKDIV_MASK; -> + usbpcr1 |=3D div_bits; +> + usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); +> + usbpcr1 &= ~USBPCR1_REFCLKDIV_MASK; +> + usbpcr1 |= div_bits; > + writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); > + > + spin_unlock_irqrestore(&cgu->lock, flags); > + return 0; > +} > + -> +static struct clk_ops jz4780_otg_phy_ops =3D { -> + .get_parent =3D jz4780_otg_phy_get_parent, -> + .set_parent =3D jz4780_otg_phy_set_parent, +> +static struct clk_ops jz4780_otg_phy_ops = { +> + .get_parent = jz4780_otg_phy_get_parent, +> + .set_parent = jz4780_otg_phy_set_parent, > + -> + .recalc_rate =3D jz4780_otg_phy_recalc_rate, -> + .round_rate =3D jz4780_otg_phy_round_rate, -> + .set_rate =3D jz4780_otg_phy_set_rate, +> + .recalc_rate = jz4780_otg_phy_recalc_rate, +> + .round_rate = jz4780_otg_phy_round_rate, +> + .set_rate = jz4780_otg_phy_set_rate, > +}; > + -> +static const s8 pll_od_encoding[16] =3D { +> +static const s8 pll_od_encoding[16] = { > + 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, > + 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, > +}; > + -> +static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] =3D { +> +static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = { > + > + /* External clocks */ > + -> + [JZ4780_CLK_EXCLK] =3D { "ext", CGU_CLK_EXT }, -> + [JZ4780_CLK_RTCLK] =3D { "rtc", CGU_CLK_EXT }, +> + [JZ4780_CLK_EXCLK] = { "ext", CGU_CLK_EXT }, +> + [JZ4780_CLK_RTCLK] = { "rtc", CGU_CLK_EXT }, > + > + /* PLLs */ > + > +#define DEF_PLL(name) { \ -> + .reg =3D CGU_REG_ ## name, \ -> + .m_shift =3D 19, \ -> + .m_bits =3D 13, \ -> + .m_offset =3D 1, \ -> + .n_shift =3D 13, \ -> + .n_bits =3D 6, \ -> + .n_offset =3D 1, \ -> + .od_shift =3D 9, \ -> + .od_bits =3D 4, \ -> + .od_max =3D 16, \ -> + .od_encoding =3D pll_od_encoding, \ -> + .stable_bit =3D 6, \ -> + .bypass_bit =3D 1, \ -> + .enable_bit =3D 0, \ +> + .reg = CGU_REG_ ## name, \ +> + .m_shift = 19, \ +> + .m_bits = 13, \ +> + .m_offset = 1, \ +> + .n_shift = 13, \ +> + .n_bits = 6, \ +> + .n_offset = 1, \ +> + .od_shift = 9, \ +> + .od_bits = 4, \ +> + .od_max = 16, \ +> + .od_encoding = pll_od_encoding, \ +> + .stable_bit = 6, \ +> + .bypass_bit = 1, \ +> + .enable_bit = 0, \ > +} > + -> + [JZ4780_CLK_APLL] =3D { +> + [JZ4780_CLK_APLL] = { > + "apll", CGU_CLK_PLL, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .pll =3D DEF_PLL(APLL), +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .pll = DEF_PLL(APLL), > + }, > + -> + [JZ4780_CLK_MPLL] =3D { +> + [JZ4780_CLK_MPLL] = { > + "mpll", CGU_CLK_PLL, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .pll =3D DEF_PLL(MPLL), +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .pll = DEF_PLL(MPLL), > + }, > + -> + [JZ4780_CLK_EPLL] =3D { +> + [JZ4780_CLK_EPLL] = { > + "epll", CGU_CLK_PLL, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .pll =3D DEF_PLL(EPLL), +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .pll = DEF_PLL(EPLL), > + }, > + -> + [JZ4780_CLK_VPLL] =3D { +> + [JZ4780_CLK_VPLL] = { > + "vpll", CGU_CLK_PLL, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .pll =3D DEF_PLL(VPLL), +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .pll = DEF_PLL(VPLL), > + }, > + > +#undef DEF_PLL > + > + /* Custom (SoC-specific) OTG PHY */ > + -> + [JZ4780_CLK_OTGPHY] =3D { +> + [JZ4780_CLK_OTGPHY] = { > + "otg_phy", CGU_CLK_CUSTOM, -> + .parents =3D { -1, -1, JZ4780_CLK_EXCLK, -1 }, -> + .custom =3D { &jz4780_otg_phy_ops }, +> + .parents = { -1, -1, JZ4780_CLK_EXCLK, -1 }, +> + .custom = { &jz4780_otg_phy_ops }, > + }, > + > + /* Muxes & dividers */ > + -> + [JZ4780_CLK_SCLKA] =3D { +> + [JZ4780_CLK_SCLKA] = { > + "sclk_a", CGU_CLK_MUX, -> + .parents =3D { -1, JZ4780_CLK_APLL, JZ4780_CLK_EXCLK, +> + .parents = { -1, JZ4780_CLK_APLL, JZ4780_CLK_EXCLK, > + JZ4780_CLK_RTCLK }, -> + .mux =3D { CGU_REG_CLOCKCONTROL, 30, 2 }, +> + .mux = { CGU_REG_CLOCKCONTROL, 30, 2 }, > + }, > + -> + [JZ4780_CLK_CPUMUX] =3D { +> + [JZ4780_CLK_CPUMUX] = { > + "cpumux", CGU_CLK_MUX, -> + .parents =3D { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, +> + .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, > + JZ4780_CLK_EPLL }, -> + .mux =3D { CGU_REG_CLOCKCONTROL, 28, 2 }, +> + .mux = { CGU_REG_CLOCKCONTROL, 28, 2 }, > + }, > + -> + [JZ4780_CLK_CPU] =3D { +> + [JZ4780_CLK_CPU] = { > + "cpu", CGU_CLK_DIV, -> + .parents =3D { JZ4780_CLK_CPUMUX, -1, -1, -1 }, -> + .div =3D { CGU_REG_CLOCKCONTROL, 0, 4, 22, -1, -1 }, +> + .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 }, +> + .div = { CGU_REG_CLOCKCONTROL, 0, 4, 22, -1, -1 }, > + }, > + -> + [JZ4780_CLK_L2CACHE] =3D { +> + [JZ4780_CLK_L2CACHE] = { > + "l2cache", CGU_CLK_DIV, -> + .parents =3D { JZ4780_CLK_CPUMUX, -1, -1, -1 }, -> + .div =3D { CGU_REG_CLOCKCONTROL, 4, 4, -1, -1, -1 }, +> + .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 }, +> + .div = { CGU_REG_CLOCKCONTROL, 4, 4, -1, -1, -1 }, > + }, > + -> + [JZ4780_CLK_AHB0] =3D { +> + [JZ4780_CLK_AHB0] = { > + "ahb0", CGU_CLK_MUX | CGU_CLK_DIV, -> + .parents =3D { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, +> + .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, > + JZ4780_CLK_EPLL }, -> + .mux =3D { CGU_REG_CLOCKCONTROL, 26, 2 }, -> + .div =3D { CGU_REG_CLOCKCONTROL, 8, 4, 21, -1, -1 }, +> + .mux = { CGU_REG_CLOCKCONTROL, 26, 2 }, +> + .div = { CGU_REG_CLOCKCONTROL, 8, 4, 21, -1, -1 }, > + }, > + -> + [JZ4780_CLK_AHB2PMUX] =3D { +> + [JZ4780_CLK_AHB2PMUX] = { > + "ahb2_apb_mux", CGU_CLK_MUX, -> + .parents =3D { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, +> + .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, > + JZ4780_CLK_RTCLK }, -> + .mux =3D { CGU_REG_CLOCKCONTROL, 24, 2 }, +> + .mux = { CGU_REG_CLOCKCONTROL, 24, 2 }, > + }, > + -> + [JZ4780_CLK_AHB2] =3D { +> + [JZ4780_CLK_AHB2] = { > + "ahb2", CGU_CLK_DIV, -> + .parents =3D { JZ4780_CLK_AHB2PMUX, -1, -1, -1 }, -> + .div =3D { CGU_REG_CLOCKCONTROL, 12, 4, 20, -1, -1 }, +> + .parents = { JZ4780_CLK_AHB2PMUX, -1, -1, -1 }, +> + .div = { CGU_REG_CLOCKCONTROL, 12, 4, 20, -1, -1 }, > + }, > + -> + [JZ4780_CLK_PCLK] =3D { +> + [JZ4780_CLK_PCLK] = { > + "pclk", CGU_CLK_DIV, -> + .parents =3D { JZ4780_CLK_AHB2PMUX, -1, -1, -1 }, -> + .div =3D { CGU_REG_CLOCKCONTROL, 16, 4, 20, -1, -1 }, +> + .parents = { JZ4780_CLK_AHB2PMUX, -1, -1, -1 }, +> + .div = { CGU_REG_CLOCKCONTROL, 16, 4, 20, -1, -1 }, > + }, > + -> + [JZ4780_CLK_DDR] =3D { +> + [JZ4780_CLK_DDR] = { > + "ddr", CGU_CLK_MUX | CGU_CLK_DIV, -> + .parents =3D { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 = -}, -> + .mux =3D { CGU_REG_DDRCDR, 30, 2 }, -> + .div =3D { CGU_REG_DDRCDR, 0, 4, 29, 28, 27 }, +> + .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 }, +> + .mux = { CGU_REG_DDRCDR, 30, 2 }, +> + .div = { CGU_REG_DDRCDR, 0, 4, 29, 28, 27 }, > + }, > + -> + [JZ4780_CLK_VPU] =3D { +> + [JZ4780_CLK_VPU] = { > + "vpu", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, +> + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, > + JZ4780_CLK_EPLL, -1 }, -> + .mux =3D { CGU_REG_VPUCDR, 30, 2 }, -> + .div =3D { CGU_REG_VPUCDR, 0, 4, 29, 28, 27 }, -> + .gate =3D { CGU_REG_CLKGR1, 2 }, +> + .mux = { CGU_REG_VPUCDR, 30, 2 }, +> + .div = { CGU_REG_VPUCDR, 0, 4, 29, 28, 27 }, +> + .gate = { CGU_REG_CLKGR1, 2 }, > + }, > + -> + [JZ4780_CLK_I2SPLL] =3D { +> + [JZ4780_CLK_I2SPLL] = { > + "i2s_pll", CGU_CLK_MUX | CGU_CLK_DIV, -> + .parents =3D { JZ4780_CLK_SCLKA, JZ4780_CLK_EPLL, -1, -1 = -}, -> + .mux =3D { CGU_REG_I2SCDR, 30, 1 }, -> + .div =3D { CGU_REG_I2SCDR, 0, 8, 29, 28, 27 }, +> + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_EPLL, -1, -1 }, +> + .mux = { CGU_REG_I2SCDR, 30, 1 }, +> + .div = { CGU_REG_I2SCDR, 0, 8, 29, 28, 27 }, > + }, > + -> + [JZ4780_CLK_I2S] =3D { +> + [JZ4780_CLK_I2S] = { > + "i2s", CGU_CLK_MUX, -> + .parents =3D { JZ4780_CLK_EXCLK, JZ4780_CLK_I2SPLL, -1, -= -1 }, -> + .mux =3D { CGU_REG_I2SCDR, 31, 1 }, +> + .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_I2SPLL, -1, -1 }, +> + .mux = { CGU_REG_I2SCDR, 31, 1 }, > + }, > + -> + [JZ4780_CLK_LCD0PIXCLK] =3D { +> + [JZ4780_CLK_LCD0PIXCLK] = { > + "lcd0pixclk", CGU_CLK_MUX | CGU_CLK_DIV, -> + .parents =3D { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, +> + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, > + JZ4780_CLK_VPLL, -1 }, -> + .mux =3D { CGU_REG_LP0CDR, 30, 2 }, -> + .div =3D { CGU_REG_LP0CDR, 0, 8, 28, 27, 26 }, +> + .mux = { CGU_REG_LP0CDR, 30, 2 }, +> + .div = { CGU_REG_LP0CDR, 0, 8, 28, 27, 26 }, > + }, > + -> + [JZ4780_CLK_LCD1PIXCLK] =3D { +> + [JZ4780_CLK_LCD1PIXCLK] = { > + "lcd1pixclk", CGU_CLK_MUX | CGU_CLK_DIV, -> + .parents =3D { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, +> + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, > + JZ4780_CLK_VPLL, -1 }, -> + .mux =3D { CGU_REG_LP1CDR, 30, 2 }, -> + .div =3D { CGU_REG_LP1CDR, 0, 8, 28, 27, 26 }, +> + .mux = { CGU_REG_LP1CDR, 30, 2 }, +> + .div = { CGU_REG_LP1CDR, 0, 8, 28, 27, 26 }, > + }, > + -> + [JZ4780_CLK_MSCMUX] =3D { +> + [JZ4780_CLK_MSCMUX] = { > + "msc_mux", CGU_CLK_MUX, -> + .parents =3D { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 = -}, -> + .mux =3D { CGU_REG_MSC0CDR, 30, 2 }, +> + .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 }, +> + .mux = { CGU_REG_MSC0CDR, 30, 2 }, > + }, > + -> + [JZ4780_CLK_MSC0] =3D { +> + [JZ4780_CLK_MSC0] = { > + "msc0", CGU_CLK_DIV | CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_MSCMUX, -1, -1, -1 }, -> + .div =3D { CGU_REG_MSC0CDR, 0, 8, 29, 28, 27 }, -> + .gate =3D { CGU_REG_CLKGR0, 3 }, +> + .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 }, +> + .div = { CGU_REG_MSC0CDR, 0, 8, 29, 28, 27 }, +> + .gate = { CGU_REG_CLKGR0, 3 }, > + }, > + -> + [JZ4780_CLK_MSC1] =3D { +> + [JZ4780_CLK_MSC1] = { > + "msc1", CGU_CLK_DIV | CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_MSCMUX, -1, -1, -1 }, -> + .div =3D { CGU_REG_MSC1CDR, 0, 8, 29, 28, 27 }, -> + .gate =3D { CGU_REG_CLKGR0, 11 }, +> + .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 }, +> + .div = { CGU_REG_MSC1CDR, 0, 8, 29, 28, 27 }, +> + .gate = { CGU_REG_CLKGR0, 11 }, > + }, > + -> + [JZ4780_CLK_MSC2] =3D { +> + [JZ4780_CLK_MSC2] = { > + "msc2", CGU_CLK_DIV | CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_MSCMUX, -1, -1, -1 }, -> + .div =3D { CGU_REG_MSC2CDR, 0, 8, 29, 28, 27 }, -> + .gate =3D { CGU_REG_CLKGR0, 12 }, +> + .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 }, +> + .div = { CGU_REG_MSC2CDR, 0, 8, 29, 28, 27 }, +> + .gate = { CGU_REG_CLKGR0, 12 }, > + }, > + -> + [JZ4780_CLK_UHC] =3D { +> + [JZ4780_CLK_UHC] = { > + "uhc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, +> + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, > + JZ4780_CLK_EPLL, JZ4780_CLK_OTGPHY }, -> + .mux =3D { CGU_REG_UHCCDR, 30, 2 }, -> + .div =3D { CGU_REG_UHCCDR, 0, 8, 29, 28, 27 }, -> + .gate =3D { CGU_REG_CLKGR0, 24 }, +> + .mux = { CGU_REG_UHCCDR, 30, 2 }, +> + .div = { CGU_REG_UHCCDR, 0, 8, 29, 28, 27 }, +> + .gate = { CGU_REG_CLKGR0, 24 }, > + }, > + -> + [JZ4780_CLK_SSIPLL] =3D { +> + [JZ4780_CLK_SSIPLL] = { > + "ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV, -> + .parents =3D { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 = -}, -> + .mux =3D { CGU_REG_SSICDR, 30, 1 }, -> + .div =3D { CGU_REG_SSICDR, 0, 8, 29, 28, 27 }, +> + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 }, +> + .mux = { CGU_REG_SSICDR, 30, 1 }, +> + .div = { CGU_REG_SSICDR, 0, 8, 29, 28, 27 }, > + }, > + -> + [JZ4780_CLK_SSI] =3D { +> + [JZ4780_CLK_SSI] = { > + "ssi", CGU_CLK_MUX, -> + .parents =3D { JZ4780_CLK_EXCLK, JZ4780_CLK_SSIPLL, -1, -= -1 }, -> + .mux =3D { CGU_REG_SSICDR, 31, 1 }, +> + .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_SSIPLL, -1, -1 }, +> + .mux = { CGU_REG_SSICDR, 31, 1 }, > + }, > + -> + [JZ4780_CLK_CIMMCLK] =3D { +> + [JZ4780_CLK_CIMMCLK] = { > + "cim_mclk", CGU_CLK_MUX | CGU_CLK_DIV, -> + .parents =3D { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 = -}, -> + .mux =3D { CGU_REG_CIMCDR, 31, 1 }, -> + .div =3D { CGU_REG_CIMCDR, 0, 8, 30, 29, 28 }, +> + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 }, +> + .mux = { CGU_REG_CIMCDR, 31, 1 }, +> + .div = { CGU_REG_CIMCDR, 0, 8, 30, 29, 28 }, > + }, > + -> + [JZ4780_CLK_PCMPLL] =3D { +> + [JZ4780_CLK_PCMPLL] = { > + "pcm_pll", CGU_CLK_MUX | CGU_CLK_DIV, -> + .parents =3D { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, +> + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, > + JZ4780_CLK_EPLL, JZ4780_CLK_VPLL }, -> + .mux =3D { CGU_REG_PCMCDR, 29, 2 }, -> + .div =3D { CGU_REG_PCMCDR, 0, 8, 28, 27, 26 }, +> + .mux = { CGU_REG_PCMCDR, 29, 2 }, +> + .div = { CGU_REG_PCMCDR, 0, 8, 28, 27, 26 }, > + }, > + -> + [JZ4780_CLK_PCM] =3D { +> + [JZ4780_CLK_PCM] = { > + "pcm", CGU_CLK_MUX | CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, JZ4780_CLK_PCMPLL, -1, -= -1 }, -> + .mux =3D { CGU_REG_PCMCDR, 31, 1 }, -> + .gate =3D { CGU_REG_CLKGR1, 3 }, +> + .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_PCMPLL, -1, -1 }, +> + .mux = { CGU_REG_PCMCDR, 31, 1 }, +> + .gate = { CGU_REG_CLKGR1, 3 }, > + }, > + -> + [JZ4780_CLK_GPU] =3D { +> + [JZ4780_CLK_GPU] = { > + "gpu", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, -> + .parents =3D { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, +> + .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, > + JZ4780_CLK_EPLL }, -> + .mux =3D { CGU_REG_GPUCDR, 30, 2 }, -> + .div =3D { CGU_REG_GPUCDR, 0, 4, 29, 28, 27 }, -> + .gate =3D { CGU_REG_CLKGR1, 4 }, +> + .mux = { CGU_REG_GPUCDR, 30, 2 }, +> + .div = { CGU_REG_GPUCDR, 0, 4, 29, 28, 27 }, +> + .gate = { CGU_REG_CLKGR1, 4 }, > + }, > + -> + [JZ4780_CLK_HDMI] =3D { +> + [JZ4780_CLK_HDMI] = { > + "hdmi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, +> + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, > + JZ4780_CLK_VPLL, -1 }, -> + .mux =3D { CGU_REG_HDMICDR, 30, 2 }, -> + .div =3D { CGU_REG_HDMICDR, 0, 8, 29, 28, 26 }, -> + .gate =3D { CGU_REG_CLKGR1, 9 }, +> + .mux = { CGU_REG_HDMICDR, 30, 2 }, +> + .div = { CGU_REG_HDMICDR, 0, 8, 29, 28, 26 }, +> + .gate = { CGU_REG_CLKGR1, 9 }, > + }, > + -> + [JZ4780_CLK_BCH] =3D { +> + [JZ4780_CLK_BCH] = { > + "bch", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, -> + .parents =3D { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, +> + .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, > + JZ4780_CLK_EPLL }, -> + .mux =3D { CGU_REG_BCHCDR, 30, 2 }, -> + .div =3D { CGU_REG_BCHCDR, 0, 4, 29, 28, 27 }, -> + .gate =3D { CGU_REG_CLKGR0, 1 }, +> + .mux = { CGU_REG_BCHCDR, 30, 2 }, +> + .div = { CGU_REG_BCHCDR, 0, 4, 29, 28, 27 }, +> + .gate = { CGU_REG_CLKGR0, 1 }, > + }, > + > + /* Gate-only clocks */ > + -> + [JZ4780_CLK_NEMC] =3D { +> + [JZ4780_CLK_NEMC] = { > + "nemc", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_AHB2, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 0 }, +> + .parents = { JZ4780_CLK_AHB2, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 0 }, > + }, > + -> + [JZ4780_CLK_OTG0] =3D { +> + [JZ4780_CLK_OTG0] = { > + "otg0", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 2 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 2 }, > + }, > + -> + [JZ4780_CLK_SSI0] =3D { +> + [JZ4780_CLK_SSI0] = { > + "ssi0", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_SSI, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 4 }, +> + .parents = { JZ4780_CLK_SSI, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 4 }, > + }, > + -> + [JZ4780_CLK_SMB0] =3D { +> + [JZ4780_CLK_SMB0] = { > + "smb0", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_PCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 5 }, +> + .parents = { JZ4780_CLK_PCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 5 }, > + }, > + -> + [JZ4780_CLK_SMB1] =3D { +> + [JZ4780_CLK_SMB1] = { > + "smb1", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_PCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 6 }, +> + .parents = { JZ4780_CLK_PCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 6 }, > + }, > + -> + [JZ4780_CLK_SCC] =3D { +> + [JZ4780_CLK_SCC] = { > + "scc", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 7 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 7 }, > + }, > + -> + [JZ4780_CLK_AIC] =3D { +> + [JZ4780_CLK_AIC] = { > + "aic", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 8 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 8 }, > + }, > + -> + [JZ4780_CLK_TSSI0] =3D { +> + [JZ4780_CLK_TSSI0] = { > + "tssi0", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 9 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 9 }, > + }, > + -> + [JZ4780_CLK_OWI] =3D { +> + [JZ4780_CLK_OWI] = { > + "owi", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 10 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 10 }, > + }, > + -> + [JZ4780_CLK_KBC] =3D { +> + [JZ4780_CLK_KBC] = { > + "kbc", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 13 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 13 }, > + }, > + -> + [JZ4780_CLK_SADC] =3D { +> + [JZ4780_CLK_SADC] = { > + "sadc", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 14 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 14 }, > + }, > + -> + [JZ4780_CLK_UART0] =3D { +> + [JZ4780_CLK_UART0] = { > + "uart0", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 15 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 15 }, > + }, > + -> + [JZ4780_CLK_UART1] =3D { +> + [JZ4780_CLK_UART1] = { > + "uart1", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 16 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 16 }, > + }, > + -> + [JZ4780_CLK_UART2] =3D { +> + [JZ4780_CLK_UART2] = { > + "uart2", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 17 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 17 }, > + }, > + -> + [JZ4780_CLK_UART3] =3D { +> + [JZ4780_CLK_UART3] = { > + "uart3", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 18 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 18 }, > + }, > + -> + [JZ4780_CLK_SSI1] =3D { +> + [JZ4780_CLK_SSI1] = { > + "ssi1", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_SSI, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 19 }, +> + .parents = { JZ4780_CLK_SSI, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 19 }, > + }, > + -> + [JZ4780_CLK_SSI2] =3D { +> + [JZ4780_CLK_SSI2] = { > + "ssi2", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_SSI, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 20 }, +> + .parents = { JZ4780_CLK_SSI, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 20 }, > + }, > + -> + [JZ4780_CLK_PDMA] =3D { +> + [JZ4780_CLK_PDMA] = { > + "pdma", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 21 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 21 }, > + }, > + -> + [JZ4780_CLK_GPS] =3D { +> + [JZ4780_CLK_GPS] = { > + "gps", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 22 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 22 }, > + }, > + -> + [JZ4780_CLK_MAC] =3D { +> + [JZ4780_CLK_MAC] = { > + "mac", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 23 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 23 }, > + }, > + -> + [JZ4780_CLK_SMB2] =3D { +> + [JZ4780_CLK_SMB2] = { > + "smb2", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_PCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 24 }, +> + .parents = { JZ4780_CLK_PCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 24 }, > + }, > + -> + [JZ4780_CLK_CIM] =3D { +> + [JZ4780_CLK_CIM] = { > + "cim", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 26 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 26 }, > + }, > + -> + [JZ4780_CLK_LCD] =3D { +> + [JZ4780_CLK_LCD] = { > + "lcd", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 28 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 28 }, > + }, > + -> + [JZ4780_CLK_TVE] =3D { +> + [JZ4780_CLK_TVE] = { > + "tve", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_LCD, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 27 }, +> + .parents = { JZ4780_CLK_LCD, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 27 }, > + }, > + -> + [JZ4780_CLK_IPU] =3D { +> + [JZ4780_CLK_IPU] = { > + "ipu", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 29 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 29 }, > + }, > + -> + [JZ4780_CLK_DDR0] =3D { +> + [JZ4780_CLK_DDR0] = { > + "ddr0", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_DDR, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 30 }, +> + .parents = { JZ4780_CLK_DDR, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 30 }, > + }, > + -> + [JZ4780_CLK_DDR1] =3D { +> + [JZ4780_CLK_DDR1] = { > + "ddr1", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_DDR, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR0, 31 }, +> + .parents = { JZ4780_CLK_DDR, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR0, 31 }, > + }, > + -> + [JZ4780_CLK_SMB3] =3D { +> + [JZ4780_CLK_SMB3] = { > + "smb3", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_PCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR1, 0 }, +> + .parents = { JZ4780_CLK_PCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR1, 0 }, > + }, > + -> + [JZ4780_CLK_TSSI1] =3D { +> + [JZ4780_CLK_TSSI1] = { > + "tssi1", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR1, 1 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR1, 1 }, > + }, > + -> + [JZ4780_CLK_COMPRESS] =3D { +> + [JZ4780_CLK_COMPRESS] = { > + "compress", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR1, 5 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR1, 5 }, > + }, > + -> + [JZ4780_CLK_AIC1] =3D { +> + [JZ4780_CLK_AIC1] = { > + "aic1", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR1, 6 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR1, 6 }, > + }, > + -> + [JZ4780_CLK_GPVLC] =3D { +> + [JZ4780_CLK_GPVLC] = { > + "gpvlc", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR1, 7 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR1, 7 }, > + }, > + -> + [JZ4780_CLK_OTG1] =3D { +> + [JZ4780_CLK_OTG1] = { > + "otg1", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR1, 8 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR1, 8 }, > + }, > + -> + [JZ4780_CLK_UART4] =3D { +> + [JZ4780_CLK_UART4] = { > + "uart4", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR1, 10 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR1, 10 }, > + }, > + -> + [JZ4780_CLK_AHBMON] =3D { +> + [JZ4780_CLK_AHBMON] = { > + "ahb_mon", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR1, 11 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR1, 11 }, > + }, > + -> + [JZ4780_CLK_SMB4] =3D { +> + [JZ4780_CLK_SMB4] = { > + "smb4", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_PCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR1, 12 }, +> + .parents = { JZ4780_CLK_PCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR1, 12 }, > + }, > + -> + [JZ4780_CLK_DES] =3D { +> + [JZ4780_CLK_DES] = { > + "des", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR1, 13 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR1, 13 }, > + }, > + -> + [JZ4780_CLK_X2D] =3D { +> + [JZ4780_CLK_X2D] = { > + "x2d", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR1, 14 }, +> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR1, 14 }, > + }, > + -> + [JZ4780_CLK_CORE1] =3D { +> + [JZ4780_CLK_CORE1] = { > + "core1", CGU_CLK_GATE, -> + .parents =3D { JZ4780_CLK_CPU, -1, -1, -1 }, -> + .gate =3D { CGU_REG_CLKGR1, 15 }, +> + .parents = { JZ4780_CLK_CPU, -1, -1, -1 }, +> + .gate = { CGU_REG_CLKGR1, 15 }, > + }, > + > +}; @@ -802,21 +783,20 @@ rate, > +{ > + int retval; > + -> + cgu =3D ingenic_cgu_new(jz4780_cgu_clocks, +> + cgu = ingenic_cgu_new(jz4780_cgu_clocks, > + ARRAY_SIZE(jz4780_cgu_clocks), np); > + if (!cgu) { > + pr_err("%s: failed to initialise CGU\n", __func__); > + return; > + } > + -> + retval =3D ingenic_cgu_register_clocks(cgu); +> + retval = ingenic_cgu_register_clocks(cgu); > + if (retval) { > + pr_err("%s: failed to register CGU Clocks\n", __func__); > + return; > + } > +} > +CLK_OF_DECLARE(jz4780_cgu, "ingenic,jz4780-cgu", jz4780_cgu_init); -> -- = - +> -- > 2.4.1 ->=20 +> diff --git a/a/content_digest b/N2/content_digest index 6dc895d..17822b3 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -5,8 +5,7 @@ "Date\0Wed, 03 Jun 2015 16:32:00 -0700\0" "To\0Paul Burton <paul.burton@imgtec.com>" " linux-mips@linux-mips.org\0" - "Cc\0Paul Burton <paul.burton@imgtec.com>" - Lars-Peter Clausen <lars@metafoo.de> + "Cc\0Lars-Peter Clausen <lars@metafoo.de>" Ralf Baechle <ralf@linux-mips.org> Stephen Boyd <sboyd@codeaurora.org> linux-clk@vger.kernel.org @@ -16,8 +15,7 @@ "Quoting Paul Burton (2015-05-24 08:11:40)\n" "> Add support for the clocks provided by the CGU in the Ingenic JZ4780\n" "> SoC, making use of the SoC-agnostic CGU code to do the heavy lifting.\n" - "> =\n" - "\n" + "> \n" "> Signed-off-by: Paul Burton <paul.burton@imgtec.com>\n" "> Co-authored-by: Paul Cercueil <paul@crapouillou.net>\n" "> Cc: Lars-Peter Clausen <lars@metafoo.de>\n" @@ -38,15 +36,13 @@ "Mike\n" "\n" "> ---\n" - "> =\n" - "\n" + "> \n" "> Changes in v5:\n" "> - Declare jz4780_otg_phy_ops static.\n" "> - Drop setting the parent of the UHC clock during probe - USB isn't\n" "> supported as of this patchset anyway, so it can be dealt with in\n" "> whatever's deemed the best way later.\n" - "> =\n" - "\n" + "> \n" "> Changes in v4:\n" "> - Return on ingenic_cgu_new or ingenic_cgu_register_clocks failure.\n" "> - Initialise all unused clock parent fields to -1. Zero initialisation\n" @@ -56,33 +52,27 @@ "> to the clock description (which is hopefully OK). Initialising to -1\n" "> makes sense for resilience should the latter ever not be the case,\n" "> and to avoid that bit of implicit magic knowledge.\n" - "> =\n" - "\n" + "> \n" "> Changes in v3:\n" "> - Rebase.\n" - "> =\n" - "\n" + "> \n" "> Changes in v2:\n" "> - Remove FSF address per checkpatch (ZubairLK).\n" - "> =\n" - "\n" + "> \n" "> drivers/clk/ingenic/Makefile | 1 +\n" - "> drivers/clk/ingenic/jz4780-cgu.c | 733 +++++++++++++++++++++++++++++++++=\n" - "++++++\n" + "> drivers/clk/ingenic/jz4780-cgu.c | 733 +++++++++++++++++++++++++++++++++++++++\n" "> 2 files changed, 734 insertions(+)\n" "> create mode 100644 drivers/clk/ingenic/jz4780-cgu.c\n" - "> =\n" - "\n" + "> \n" "> diff --git a/drivers/clk/ingenic/Makefile b/drivers/clk/ingenic/Makefile\n" "> index e6db7da..cd47b06 100644\n" "> --- a/drivers/clk/ingenic/Makefile\n" "> +++ b/drivers/clk/ingenic/Makefile\n" "> @@ -1,2 +1,3 @@\n" - "> obj-y +=3D cgu.o\n" - "> obj-$(CONFIG_MACH_JZ4740) +=3D jz4740-cgu.o\n" - "> +obj-$(CONFIG_MACH_JZ4780) +=3D jz4780-cgu.o\n" - "> diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz478=\n" - "0-cgu.c\n" + "> obj-y += cgu.o\n" + "> obj-$(CONFIG_MACH_JZ4740) += jz4740-cgu.o\n" + "> +obj-$(CONFIG_MACH_JZ4780) += jz4780-cgu.o\n" + "> diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c\n" "> new file mode 100644\n" "> index 0000000..431f962\n" "> --- /dev/null\n" @@ -203,10 +193,10 @@ "> +\n" "> + spin_lock_irqsave(&cgu->lock, flags);\n" "> +\n" - "> + usbpcr1 =3D readl(cgu->base + CGU_REG_USBPCR1);\n" - "> + usbpcr1 &=3D ~USBPCR1_REFCLKSEL_MASK;\n" + "> + usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1);\n" + "> + usbpcr1 &= ~USBPCR1_REFCLKSEL_MASK;\n" "> + /* we only use CLKCORE */\n" - "> + usbpcr1 |=3D USBPCR1_REFCLKSEL_CORE;\n" + "> + usbpcr1 |= USBPCR1_REFCLKSEL_CORE;\n" "> + writel(usbpcr1, cgu->base + CGU_REG_USBPCR1);\n" "> +\n" "> + spin_unlock_irqrestore(&cgu->lock, flags);\n" @@ -219,8 +209,8 @@ "> + u32 usbpcr1;\n" "> + unsigned refclk_div;\n" "> +\n" - "> + usbpcr1 =3D readl(cgu->base + CGU_REG_USBPCR1);\n" - "> + refclk_div =3D usbpcr1 & USBPCR1_REFCLKDIV_MASK;\n" + "> + usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1);\n" + "> + refclk_div = usbpcr1 & USBPCR1_REFCLKDIV_MASK;\n" "> +\n" "> + switch (refclk_div) {\n" "> + case USBPCR1_REFCLKDIV_12:\n" @@ -240,8 +230,7 @@ "> + return parent_rate;\n" "> +}\n" "> +\n" - "> +static long jz4780_otg_phy_round_rate(struct clk_hw *hw, unsigned long r=\n" - "eq_rate,\n" + "> +static long jz4780_otg_phy_round_rate(struct clk_hw *hw, unsigned long req_rate,\n" "> + unsigned long *parent_rate)\n" "> +{\n" "> + if (req_rate < 15600000)\n" @@ -256,8 +245,7 @@ "> + return 48000000;\n" "> +}\n" "> +\n" - "> +static int jz4780_otg_phy_set_rate(struct clk_hw *hw, unsigned long req_=\n" - "rate,\n" + "> +static int jz4780_otg_phy_set_rate(struct clk_hw *hw, unsigned long req_rate,\n" "> + unsigned long parent_rate)\n" "> +{\n" "> + unsigned long flags;\n" @@ -265,19 +253,19 @@ "> +\n" "> + switch (req_rate) {\n" "> + case 12000000:\n" - "> + div_bits =3D USBPCR1_REFCLKDIV_12;\n" + "> + div_bits = USBPCR1_REFCLKDIV_12;\n" "> + break;\n" "> +\n" "> + case 19200000:\n" - "> + div_bits =3D USBPCR1_REFCLKDIV_19_2;\n" + "> + div_bits = USBPCR1_REFCLKDIV_19_2;\n" "> + break;\n" "> +\n" "> + case 24000000:\n" - "> + div_bits =3D USBPCR1_REFCLKDIV_24;\n" + "> + div_bits = USBPCR1_REFCLKDIV_24;\n" "> + break;\n" "> +\n" "> + case 48000000:\n" - "> + div_bits =3D USBPCR1_REFCLKDIV_48;\n" + "> + div_bits = USBPCR1_REFCLKDIV_48;\n" "> + break;\n" "> +\n" "> + default:\n" @@ -286,529 +274,521 @@ "> +\n" "> + spin_lock_irqsave(&cgu->lock, flags);\n" "> +\n" - "> + usbpcr1 =3D readl(cgu->base + CGU_REG_USBPCR1);\n" - "> + usbpcr1 &=3D ~USBPCR1_REFCLKDIV_MASK;\n" - "> + usbpcr1 |=3D div_bits;\n" + "> + usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1);\n" + "> + usbpcr1 &= ~USBPCR1_REFCLKDIV_MASK;\n" + "> + usbpcr1 |= div_bits;\n" "> + writel(usbpcr1, cgu->base + CGU_REG_USBPCR1);\n" "> +\n" "> + spin_unlock_irqrestore(&cgu->lock, flags);\n" "> + return 0;\n" "> +}\n" "> +\n" - "> +static struct clk_ops jz4780_otg_phy_ops =3D {\n" - "> + .get_parent =3D jz4780_otg_phy_get_parent,\n" - "> + .set_parent =3D jz4780_otg_phy_set_parent,\n" + "> +static struct clk_ops jz4780_otg_phy_ops = {\n" + "> + .get_parent = jz4780_otg_phy_get_parent,\n" + "> + .set_parent = jz4780_otg_phy_set_parent,\n" "> +\n" - "> + .recalc_rate =3D jz4780_otg_phy_recalc_rate,\n" - "> + .round_rate =3D jz4780_otg_phy_round_rate,\n" - "> + .set_rate =3D jz4780_otg_phy_set_rate,\n" + "> + .recalc_rate = jz4780_otg_phy_recalc_rate,\n" + "> + .round_rate = jz4780_otg_phy_round_rate,\n" + "> + .set_rate = jz4780_otg_phy_set_rate,\n" "> +};\n" "> +\n" - "> +static const s8 pll_od_encoding[16] =3D {\n" + "> +static const s8 pll_od_encoding[16] = {\n" "> + 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7,\n" "> + 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,\n" "> +};\n" "> +\n" - "> +static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] =3D {\n" + "> +static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = {\n" "> +\n" "> + /* External clocks */\n" "> +\n" - "> + [JZ4780_CLK_EXCLK] =3D { \"ext\", CGU_CLK_EXT },\n" - "> + [JZ4780_CLK_RTCLK] =3D { \"rtc\", CGU_CLK_EXT },\n" + "> + [JZ4780_CLK_EXCLK] = { \"ext\", CGU_CLK_EXT },\n" + "> + [JZ4780_CLK_RTCLK] = { \"rtc\", CGU_CLK_EXT },\n" "> +\n" "> + /* PLLs */\n" "> +\n" "> +#define DEF_PLL(name) { \\\n" - "> + .reg =3D CGU_REG_ ## name, \\\n" - "> + .m_shift =3D 19, \\\n" - "> + .m_bits =3D 13, \\\n" - "> + .m_offset =3D 1, \\\n" - "> + .n_shift =3D 13, \\\n" - "> + .n_bits =3D 6, \\\n" - "> + .n_offset =3D 1, \\\n" - "> + .od_shift =3D 9, \\\n" - "> + .od_bits =3D 4, \\\n" - "> + .od_max =3D 16, \\\n" - "> + .od_encoding =3D pll_od_encoding, \\\n" - "> + .stable_bit =3D 6, \\\n" - "> + .bypass_bit =3D 1, \\\n" - "> + .enable_bit =3D 0, \\\n" + "> + .reg = CGU_REG_ ## name, \\\n" + "> + .m_shift = 19, \\\n" + "> + .m_bits = 13, \\\n" + "> + .m_offset = 1, \\\n" + "> + .n_shift = 13, \\\n" + "> + .n_bits = 6, \\\n" + "> + .n_offset = 1, \\\n" + "> + .od_shift = 9, \\\n" + "> + .od_bits = 4, \\\n" + "> + .od_max = 16, \\\n" + "> + .od_encoding = pll_od_encoding, \\\n" + "> + .stable_bit = 6, \\\n" + "> + .bypass_bit = 1, \\\n" + "> + .enable_bit = 0, \\\n" "> +}\n" "> +\n" - "> + [JZ4780_CLK_APLL] =3D {\n" + "> + [JZ4780_CLK_APLL] = {\n" "> + \"apll\", CGU_CLK_PLL,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .pll =3D DEF_PLL(APLL),\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .pll = DEF_PLL(APLL),\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_MPLL] =3D {\n" + "> + [JZ4780_CLK_MPLL] = {\n" "> + \"mpll\", CGU_CLK_PLL,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .pll =3D DEF_PLL(MPLL),\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .pll = DEF_PLL(MPLL),\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_EPLL] =3D {\n" + "> + [JZ4780_CLK_EPLL] = {\n" "> + \"epll\", CGU_CLK_PLL,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .pll =3D DEF_PLL(EPLL),\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .pll = DEF_PLL(EPLL),\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_VPLL] =3D {\n" + "> + [JZ4780_CLK_VPLL] = {\n" "> + \"vpll\", CGU_CLK_PLL,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .pll =3D DEF_PLL(VPLL),\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .pll = DEF_PLL(VPLL),\n" "> + },\n" "> +\n" "> +#undef DEF_PLL\n" "> +\n" "> + /* Custom (SoC-specific) OTG PHY */\n" "> +\n" - "> + [JZ4780_CLK_OTGPHY] =3D {\n" + "> + [JZ4780_CLK_OTGPHY] = {\n" "> + \"otg_phy\", CGU_CLK_CUSTOM,\n" - "> + .parents =3D { -1, -1, JZ4780_CLK_EXCLK, -1 },\n" - "> + .custom =3D { &jz4780_otg_phy_ops },\n" + "> + .parents = { -1, -1, JZ4780_CLK_EXCLK, -1 },\n" + "> + .custom = { &jz4780_otg_phy_ops },\n" "> + },\n" "> +\n" "> + /* Muxes & dividers */\n" "> +\n" - "> + [JZ4780_CLK_SCLKA] =3D {\n" + "> + [JZ4780_CLK_SCLKA] = {\n" "> + \"sclk_a\", CGU_CLK_MUX,\n" - "> + .parents =3D { -1, JZ4780_CLK_APLL, JZ4780_CLK_EXCLK,\n" + "> + .parents = { -1, JZ4780_CLK_APLL, JZ4780_CLK_EXCLK,\n" "> + JZ4780_CLK_RTCLK },\n" - "> + .mux =3D { CGU_REG_CLOCKCONTROL, 30, 2 },\n" + "> + .mux = { CGU_REG_CLOCKCONTROL, 30, 2 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_CPUMUX] =3D {\n" + "> + [JZ4780_CLK_CPUMUX] = {\n" "> + \"cpumux\", CGU_CLK_MUX,\n" - "> + .parents =3D { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" + "> + .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" "> + JZ4780_CLK_EPLL },\n" - "> + .mux =3D { CGU_REG_CLOCKCONTROL, 28, 2 },\n" + "> + .mux = { CGU_REG_CLOCKCONTROL, 28, 2 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_CPU] =3D {\n" + "> + [JZ4780_CLK_CPU] = {\n" "> + \"cpu\", CGU_CLK_DIV,\n" - "> + .parents =3D { JZ4780_CLK_CPUMUX, -1, -1, -1 },\n" - "> + .div =3D { CGU_REG_CLOCKCONTROL, 0, 4, 22, -1, -1 },\n" + "> + .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },\n" + "> + .div = { CGU_REG_CLOCKCONTROL, 0, 4, 22, -1, -1 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_L2CACHE] =3D {\n" + "> + [JZ4780_CLK_L2CACHE] = {\n" "> + \"l2cache\", CGU_CLK_DIV,\n" - "> + .parents =3D { JZ4780_CLK_CPUMUX, -1, -1, -1 },\n" - "> + .div =3D { CGU_REG_CLOCKCONTROL, 4, 4, -1, -1, -1 },\n" + "> + .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },\n" + "> + .div = { CGU_REG_CLOCKCONTROL, 4, 4, -1, -1, -1 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_AHB0] =3D {\n" + "> + [JZ4780_CLK_AHB0] = {\n" "> + \"ahb0\", CGU_CLK_MUX | CGU_CLK_DIV,\n" - "> + .parents =3D { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" + "> + .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" "> + JZ4780_CLK_EPLL },\n" - "> + .mux =3D { CGU_REG_CLOCKCONTROL, 26, 2 },\n" - "> + .div =3D { CGU_REG_CLOCKCONTROL, 8, 4, 21, -1, -1 },\n" + "> + .mux = { CGU_REG_CLOCKCONTROL, 26, 2 },\n" + "> + .div = { CGU_REG_CLOCKCONTROL, 8, 4, 21, -1, -1 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_AHB2PMUX] =3D {\n" + "> + [JZ4780_CLK_AHB2PMUX] = {\n" "> + \"ahb2_apb_mux\", CGU_CLK_MUX,\n" - "> + .parents =3D { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" + "> + .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" "> + JZ4780_CLK_RTCLK },\n" - "> + .mux =3D { CGU_REG_CLOCKCONTROL, 24, 2 },\n" + "> + .mux = { CGU_REG_CLOCKCONTROL, 24, 2 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_AHB2] =3D {\n" + "> + [JZ4780_CLK_AHB2] = {\n" "> + \"ahb2\", CGU_CLK_DIV,\n" - "> + .parents =3D { JZ4780_CLK_AHB2PMUX, -1, -1, -1 },\n" - "> + .div =3D { CGU_REG_CLOCKCONTROL, 12, 4, 20, -1, -1 },\n" + "> + .parents = { JZ4780_CLK_AHB2PMUX, -1, -1, -1 },\n" + "> + .div = { CGU_REG_CLOCKCONTROL, 12, 4, 20, -1, -1 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_PCLK] =3D {\n" + "> + [JZ4780_CLK_PCLK] = {\n" "> + \"pclk\", CGU_CLK_DIV,\n" - "> + .parents =3D { JZ4780_CLK_AHB2PMUX, -1, -1, -1 },\n" - "> + .div =3D { CGU_REG_CLOCKCONTROL, 16, 4, 20, -1, -1 },\n" + "> + .parents = { JZ4780_CLK_AHB2PMUX, -1, -1, -1 },\n" + "> + .div = { CGU_REG_CLOCKCONTROL, 16, 4, 20, -1, -1 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_DDR] =3D {\n" + "> + [JZ4780_CLK_DDR] = {\n" "> + \"ddr\", CGU_CLK_MUX | CGU_CLK_DIV,\n" - "> + .parents =3D { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 =\n" - "},\n" - "> + .mux =3D { CGU_REG_DDRCDR, 30, 2 },\n" - "> + .div =3D { CGU_REG_DDRCDR, 0, 4, 29, 28, 27 },\n" + "> + .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 },\n" + "> + .mux = { CGU_REG_DDRCDR, 30, 2 },\n" + "> + .div = { CGU_REG_DDRCDR, 0, 4, 29, 28, 27 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_VPU] =3D {\n" + "> + [JZ4780_CLK_VPU] = {\n" "> + \"vpu\", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" + "> + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" "> + JZ4780_CLK_EPLL, -1 },\n" - "> + .mux =3D { CGU_REG_VPUCDR, 30, 2 },\n" - "> + .div =3D { CGU_REG_VPUCDR, 0, 4, 29, 28, 27 },\n" - "> + .gate =3D { CGU_REG_CLKGR1, 2 },\n" + "> + .mux = { CGU_REG_VPUCDR, 30, 2 },\n" + "> + .div = { CGU_REG_VPUCDR, 0, 4, 29, 28, 27 },\n" + "> + .gate = { CGU_REG_CLKGR1, 2 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_I2SPLL] =3D {\n" + "> + [JZ4780_CLK_I2SPLL] = {\n" "> + \"i2s_pll\", CGU_CLK_MUX | CGU_CLK_DIV,\n" - "> + .parents =3D { JZ4780_CLK_SCLKA, JZ4780_CLK_EPLL, -1, -1 =\n" - "},\n" - "> + .mux =3D { CGU_REG_I2SCDR, 30, 1 },\n" - "> + .div =3D { CGU_REG_I2SCDR, 0, 8, 29, 28, 27 },\n" + "> + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_EPLL, -1, -1 },\n" + "> + .mux = { CGU_REG_I2SCDR, 30, 1 },\n" + "> + .div = { CGU_REG_I2SCDR, 0, 8, 29, 28, 27 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_I2S] =3D {\n" + "> + [JZ4780_CLK_I2S] = {\n" "> + \"i2s\", CGU_CLK_MUX,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, JZ4780_CLK_I2SPLL, -1, -=\n" - "1 },\n" - "> + .mux =3D { CGU_REG_I2SCDR, 31, 1 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_I2SPLL, -1, -1 },\n" + "> + .mux = { CGU_REG_I2SCDR, 31, 1 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_LCD0PIXCLK] =3D {\n" + "> + [JZ4780_CLK_LCD0PIXCLK] = {\n" "> + \"lcd0pixclk\", CGU_CLK_MUX | CGU_CLK_DIV,\n" - "> + .parents =3D { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" + "> + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" "> + JZ4780_CLK_VPLL, -1 },\n" - "> + .mux =3D { CGU_REG_LP0CDR, 30, 2 },\n" - "> + .div =3D { CGU_REG_LP0CDR, 0, 8, 28, 27, 26 },\n" + "> + .mux = { CGU_REG_LP0CDR, 30, 2 },\n" + "> + .div = { CGU_REG_LP0CDR, 0, 8, 28, 27, 26 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_LCD1PIXCLK] =3D {\n" + "> + [JZ4780_CLK_LCD1PIXCLK] = {\n" "> + \"lcd1pixclk\", CGU_CLK_MUX | CGU_CLK_DIV,\n" - "> + .parents =3D { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" + "> + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" "> + JZ4780_CLK_VPLL, -1 },\n" - "> + .mux =3D { CGU_REG_LP1CDR, 30, 2 },\n" - "> + .div =3D { CGU_REG_LP1CDR, 0, 8, 28, 27, 26 },\n" + "> + .mux = { CGU_REG_LP1CDR, 30, 2 },\n" + "> + .div = { CGU_REG_LP1CDR, 0, 8, 28, 27, 26 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_MSCMUX] =3D {\n" + "> + [JZ4780_CLK_MSCMUX] = {\n" "> + \"msc_mux\", CGU_CLK_MUX,\n" - "> + .parents =3D { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 =\n" - "},\n" - "> + .mux =3D { CGU_REG_MSC0CDR, 30, 2 },\n" + "> + .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 },\n" + "> + .mux = { CGU_REG_MSC0CDR, 30, 2 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_MSC0] =3D {\n" + "> + [JZ4780_CLK_MSC0] = {\n" "> + \"msc0\", CGU_CLK_DIV | CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_MSCMUX, -1, -1, -1 },\n" - "> + .div =3D { CGU_REG_MSC0CDR, 0, 8, 29, 28, 27 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 3 },\n" + "> + .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 },\n" + "> + .div = { CGU_REG_MSC0CDR, 0, 8, 29, 28, 27 },\n" + "> + .gate = { CGU_REG_CLKGR0, 3 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_MSC1] =3D {\n" + "> + [JZ4780_CLK_MSC1] = {\n" "> + \"msc1\", CGU_CLK_DIV | CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_MSCMUX, -1, -1, -1 },\n" - "> + .div =3D { CGU_REG_MSC1CDR, 0, 8, 29, 28, 27 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 11 },\n" + "> + .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 },\n" + "> + .div = { CGU_REG_MSC1CDR, 0, 8, 29, 28, 27 },\n" + "> + .gate = { CGU_REG_CLKGR0, 11 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_MSC2] =3D {\n" + "> + [JZ4780_CLK_MSC2] = {\n" "> + \"msc2\", CGU_CLK_DIV | CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_MSCMUX, -1, -1, -1 },\n" - "> + .div =3D { CGU_REG_MSC2CDR, 0, 8, 29, 28, 27 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 12 },\n" + "> + .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 },\n" + "> + .div = { CGU_REG_MSC2CDR, 0, 8, 29, 28, 27 },\n" + "> + .gate = { CGU_REG_CLKGR0, 12 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_UHC] =3D {\n" + "> + [JZ4780_CLK_UHC] = {\n" "> + \"uhc\", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" + "> + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" "> + JZ4780_CLK_EPLL, JZ4780_CLK_OTGPHY },\n" - "> + .mux =3D { CGU_REG_UHCCDR, 30, 2 },\n" - "> + .div =3D { CGU_REG_UHCCDR, 0, 8, 29, 28, 27 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 24 },\n" + "> + .mux = { CGU_REG_UHCCDR, 30, 2 },\n" + "> + .div = { CGU_REG_UHCCDR, 0, 8, 29, 28, 27 },\n" + "> + .gate = { CGU_REG_CLKGR0, 24 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_SSIPLL] =3D {\n" + "> + [JZ4780_CLK_SSIPLL] = {\n" "> + \"ssi_pll\", CGU_CLK_MUX | CGU_CLK_DIV,\n" - "> + .parents =3D { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 =\n" - "},\n" - "> + .mux =3D { CGU_REG_SSICDR, 30, 1 },\n" - "> + .div =3D { CGU_REG_SSICDR, 0, 8, 29, 28, 27 },\n" + "> + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 },\n" + "> + .mux = { CGU_REG_SSICDR, 30, 1 },\n" + "> + .div = { CGU_REG_SSICDR, 0, 8, 29, 28, 27 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_SSI] =3D {\n" + "> + [JZ4780_CLK_SSI] = {\n" "> + \"ssi\", CGU_CLK_MUX,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, JZ4780_CLK_SSIPLL, -1, -=\n" - "1 },\n" - "> + .mux =3D { CGU_REG_SSICDR, 31, 1 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_SSIPLL, -1, -1 },\n" + "> + .mux = { CGU_REG_SSICDR, 31, 1 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_CIMMCLK] =3D {\n" + "> + [JZ4780_CLK_CIMMCLK] = {\n" "> + \"cim_mclk\", CGU_CLK_MUX | CGU_CLK_DIV,\n" - "> + .parents =3D { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 =\n" - "},\n" - "> + .mux =3D { CGU_REG_CIMCDR, 31, 1 },\n" - "> + .div =3D { CGU_REG_CIMCDR, 0, 8, 30, 29, 28 },\n" + "> + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 },\n" + "> + .mux = { CGU_REG_CIMCDR, 31, 1 },\n" + "> + .div = { CGU_REG_CIMCDR, 0, 8, 30, 29, 28 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_PCMPLL] =3D {\n" + "> + [JZ4780_CLK_PCMPLL] = {\n" "> + \"pcm_pll\", CGU_CLK_MUX | CGU_CLK_DIV,\n" - "> + .parents =3D { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" + "> + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" "> + JZ4780_CLK_EPLL, JZ4780_CLK_VPLL },\n" - "> + .mux =3D { CGU_REG_PCMCDR, 29, 2 },\n" - "> + .div =3D { CGU_REG_PCMCDR, 0, 8, 28, 27, 26 },\n" + "> + .mux = { CGU_REG_PCMCDR, 29, 2 },\n" + "> + .div = { CGU_REG_PCMCDR, 0, 8, 28, 27, 26 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_PCM] =3D {\n" + "> + [JZ4780_CLK_PCM] = {\n" "> + \"pcm\", CGU_CLK_MUX | CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, JZ4780_CLK_PCMPLL, -1, -=\n" - "1 },\n" - "> + .mux =3D { CGU_REG_PCMCDR, 31, 1 },\n" - "> + .gate =3D { CGU_REG_CLKGR1, 3 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_PCMPLL, -1, -1 },\n" + "> + .mux = { CGU_REG_PCMCDR, 31, 1 },\n" + "> + .gate = { CGU_REG_CLKGR1, 3 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_GPU] =3D {\n" + "> + [JZ4780_CLK_GPU] = {\n" "> + \"gpu\", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,\n" - "> + .parents =3D { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" + "> + .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" "> + JZ4780_CLK_EPLL },\n" - "> + .mux =3D { CGU_REG_GPUCDR, 30, 2 },\n" - "> + .div =3D { CGU_REG_GPUCDR, 0, 4, 29, 28, 27 },\n" - "> + .gate =3D { CGU_REG_CLKGR1, 4 },\n" + "> + .mux = { CGU_REG_GPUCDR, 30, 2 },\n" + "> + .div = { CGU_REG_GPUCDR, 0, 4, 29, 28, 27 },\n" + "> + .gate = { CGU_REG_CLKGR1, 4 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_HDMI] =3D {\n" + "> + [JZ4780_CLK_HDMI] = {\n" "> + \"hdmi\", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" + "> + .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" "> + JZ4780_CLK_VPLL, -1 },\n" - "> + .mux =3D { CGU_REG_HDMICDR, 30, 2 },\n" - "> + .div =3D { CGU_REG_HDMICDR, 0, 8, 29, 28, 26 },\n" - "> + .gate =3D { CGU_REG_CLKGR1, 9 },\n" + "> + .mux = { CGU_REG_HDMICDR, 30, 2 },\n" + "> + .div = { CGU_REG_HDMICDR, 0, 8, 29, 28, 26 },\n" + "> + .gate = { CGU_REG_CLKGR1, 9 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_BCH] =3D {\n" + "> + [JZ4780_CLK_BCH] = {\n" "> + \"bch\", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,\n" - "> + .parents =3D { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" + "> + .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,\n" "> + JZ4780_CLK_EPLL },\n" - "> + .mux =3D { CGU_REG_BCHCDR, 30, 2 },\n" - "> + .div =3D { CGU_REG_BCHCDR, 0, 4, 29, 28, 27 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 1 },\n" + "> + .mux = { CGU_REG_BCHCDR, 30, 2 },\n" + "> + .div = { CGU_REG_BCHCDR, 0, 4, 29, 28, 27 },\n" + "> + .gate = { CGU_REG_CLKGR0, 1 },\n" "> + },\n" "> +\n" "> + /* Gate-only clocks */\n" "> +\n" - "> + [JZ4780_CLK_NEMC] =3D {\n" + "> + [JZ4780_CLK_NEMC] = {\n" "> + \"nemc\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_AHB2, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 0 },\n" + "> + .parents = { JZ4780_CLK_AHB2, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 0 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_OTG0] =3D {\n" + "> + [JZ4780_CLK_OTG0] = {\n" "> + \"otg0\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 2 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 2 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_SSI0] =3D {\n" + "> + [JZ4780_CLK_SSI0] = {\n" "> + \"ssi0\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_SSI, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 4 },\n" + "> + .parents = { JZ4780_CLK_SSI, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 4 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_SMB0] =3D {\n" + "> + [JZ4780_CLK_SMB0] = {\n" "> + \"smb0\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_PCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 5 },\n" + "> + .parents = { JZ4780_CLK_PCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 5 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_SMB1] =3D {\n" + "> + [JZ4780_CLK_SMB1] = {\n" "> + \"smb1\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_PCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 6 },\n" + "> + .parents = { JZ4780_CLK_PCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 6 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_SCC] =3D {\n" + "> + [JZ4780_CLK_SCC] = {\n" "> + \"scc\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 7 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 7 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_AIC] =3D {\n" + "> + [JZ4780_CLK_AIC] = {\n" "> + \"aic\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 8 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 8 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_TSSI0] =3D {\n" + "> + [JZ4780_CLK_TSSI0] = {\n" "> + \"tssi0\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 9 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 9 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_OWI] =3D {\n" + "> + [JZ4780_CLK_OWI] = {\n" "> + \"owi\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 10 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 10 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_KBC] =3D {\n" + "> + [JZ4780_CLK_KBC] = {\n" "> + \"kbc\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 13 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 13 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_SADC] =3D {\n" + "> + [JZ4780_CLK_SADC] = {\n" "> + \"sadc\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 14 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 14 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_UART0] =3D {\n" + "> + [JZ4780_CLK_UART0] = {\n" "> + \"uart0\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 15 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 15 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_UART1] =3D {\n" + "> + [JZ4780_CLK_UART1] = {\n" "> + \"uart1\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 16 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 16 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_UART2] =3D {\n" + "> + [JZ4780_CLK_UART2] = {\n" "> + \"uart2\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 17 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 17 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_UART3] =3D {\n" + "> + [JZ4780_CLK_UART3] = {\n" "> + \"uart3\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 18 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 18 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_SSI1] =3D {\n" + "> + [JZ4780_CLK_SSI1] = {\n" "> + \"ssi1\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_SSI, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 19 },\n" + "> + .parents = { JZ4780_CLK_SSI, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 19 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_SSI2] =3D {\n" + "> + [JZ4780_CLK_SSI2] = {\n" "> + \"ssi2\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_SSI, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 20 },\n" + "> + .parents = { JZ4780_CLK_SSI, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 20 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_PDMA] =3D {\n" + "> + [JZ4780_CLK_PDMA] = {\n" "> + \"pdma\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 21 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 21 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_GPS] =3D {\n" + "> + [JZ4780_CLK_GPS] = {\n" "> + \"gps\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 22 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 22 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_MAC] =3D {\n" + "> + [JZ4780_CLK_MAC] = {\n" "> + \"mac\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 23 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 23 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_SMB2] =3D {\n" + "> + [JZ4780_CLK_SMB2] = {\n" "> + \"smb2\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_PCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 24 },\n" + "> + .parents = { JZ4780_CLK_PCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 24 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_CIM] =3D {\n" + "> + [JZ4780_CLK_CIM] = {\n" "> + \"cim\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 26 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 26 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_LCD] =3D {\n" + "> + [JZ4780_CLK_LCD] = {\n" "> + \"lcd\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 28 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 28 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_TVE] =3D {\n" + "> + [JZ4780_CLK_TVE] = {\n" "> + \"tve\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_LCD, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 27 },\n" + "> + .parents = { JZ4780_CLK_LCD, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 27 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_IPU] =3D {\n" + "> + [JZ4780_CLK_IPU] = {\n" "> + \"ipu\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 29 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 29 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_DDR0] =3D {\n" + "> + [JZ4780_CLK_DDR0] = {\n" "> + \"ddr0\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_DDR, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 30 },\n" + "> + .parents = { JZ4780_CLK_DDR, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 30 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_DDR1] =3D {\n" + "> + [JZ4780_CLK_DDR1] = {\n" "> + \"ddr1\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_DDR, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR0, 31 },\n" + "> + .parents = { JZ4780_CLK_DDR, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR0, 31 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_SMB3] =3D {\n" + "> + [JZ4780_CLK_SMB3] = {\n" "> + \"smb3\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_PCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR1, 0 },\n" + "> + .parents = { JZ4780_CLK_PCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR1, 0 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_TSSI1] =3D {\n" + "> + [JZ4780_CLK_TSSI1] = {\n" "> + \"tssi1\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR1, 1 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR1, 1 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_COMPRESS] =3D {\n" + "> + [JZ4780_CLK_COMPRESS] = {\n" "> + \"compress\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR1, 5 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR1, 5 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_AIC1] =3D {\n" + "> + [JZ4780_CLK_AIC1] = {\n" "> + \"aic1\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR1, 6 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR1, 6 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_GPVLC] =3D {\n" + "> + [JZ4780_CLK_GPVLC] = {\n" "> + \"gpvlc\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR1, 7 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR1, 7 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_OTG1] =3D {\n" + "> + [JZ4780_CLK_OTG1] = {\n" "> + \"otg1\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR1, 8 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR1, 8 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_UART4] =3D {\n" + "> + [JZ4780_CLK_UART4] = {\n" "> + \"uart4\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR1, 10 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR1, 10 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_AHBMON] =3D {\n" + "> + [JZ4780_CLK_AHBMON] = {\n" "> + \"ahb_mon\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR1, 11 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR1, 11 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_SMB4] =3D {\n" + "> + [JZ4780_CLK_SMB4] = {\n" "> + \"smb4\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_PCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR1, 12 },\n" + "> + .parents = { JZ4780_CLK_PCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR1, 12 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_DES] =3D {\n" + "> + [JZ4780_CLK_DES] = {\n" "> + \"des\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR1, 13 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR1, 13 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_X2D] =3D {\n" + "> + [JZ4780_CLK_X2D] = {\n" "> + \"x2d\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR1, 14 },\n" + "> + .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR1, 14 },\n" "> + },\n" "> +\n" - "> + [JZ4780_CLK_CORE1] =3D {\n" + "> + [JZ4780_CLK_CORE1] = {\n" "> + \"core1\", CGU_CLK_GATE,\n" - "> + .parents =3D { JZ4780_CLK_CPU, -1, -1, -1 },\n" - "> + .gate =3D { CGU_REG_CLKGR1, 15 },\n" + "> + .parents = { JZ4780_CLK_CPU, -1, -1, -1 },\n" + "> + .gate = { CGU_REG_CLKGR1, 15 },\n" "> + },\n" "> +\n" "> +};\n" @@ -817,23 +797,22 @@ "> +{\n" "> + int retval;\n" "> +\n" - "> + cgu =3D ingenic_cgu_new(jz4780_cgu_clocks,\n" + "> + cgu = ingenic_cgu_new(jz4780_cgu_clocks,\n" "> + ARRAY_SIZE(jz4780_cgu_clocks), np);\n" "> + if (!cgu) {\n" "> + pr_err(\"%s: failed to initialise CGU\\n\", __func__);\n" "> + return;\n" "> + }\n" "> +\n" - "> + retval =3D ingenic_cgu_register_clocks(cgu);\n" + "> + retval = ingenic_cgu_register_clocks(cgu);\n" "> + if (retval) {\n" "> + pr_err(\"%s: failed to register CGU Clocks\\n\", __func__);\n" "> + return;\n" "> + }\n" "> +}\n" "> +CLK_OF_DECLARE(jz4780_cgu, \"ingenic,jz4780-cgu\", jz4780_cgu_init);\n" - "> -- =\n" - "\n" + "> -- \n" "> 2.4.1\n" - >=20 + > -2be9843f9d9e5a56ce9e5035a73c987f91050d5e02b9cd1d06b4efc7dcfe6c09 +288aedaca9052e94b009048fe5cc74fab091518f8363e23d8d26123b4e90b903
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.