From: sboyd@codeaurora.org (Stephen Boyd)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 2/4] clk: zx: add clock support to zx296702
Date: Wed, 3 Jun 2015 16:50:21 -0700 [thread overview]
Message-ID: <20150603235021.GC490@codeaurora.org> (raw)
In-Reply-To: <1432867178-5913-1-git-send-email-jun.nie@linaro.org>
On 05/29, Jun Nie wrote:
> diff --git a/drivers/clk/zte/clk-pll.c b/drivers/clk/zte/clk-pll.c
> new file mode 100644
> index 0000000..422ef25
> --- /dev/null
> +++ b/drivers/clk/zte/clk-pll.c
> @@ -0,0 +1,184 @@
> +/*
> + * Copyright 2014 Linaro Ltd.
> + * Copyright (C) 2014 ZTE Corporation.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/clk.h>
Do you need this include?
> +#include <linux/clk-provider.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/slab.h>
> +#include <linux/spinlock.h>
[...]
> +
> +static int hw_to_idx(struct clk_zx_pll *zx_pll)
> +{
> + const struct zx_pll_config *config = zx_pll->lookup_table;
> + u32 hw_cfg0, hw_cfg1;
> + int i;
> +
> + hw_cfg0 = readl_relaxed(zx_pll->reg_base);
> + hw_cfg1 = readl_relaxed(zx_pll->reg_base + CFG0_CFG1_OFFSET);
> +
> + /* For matching the value in lookup table */
> + hw_cfg0 &= ~LOCK_FLAG;
> + hw_cfg0 |= POWER_DOWN;
> +
> + for (i = 0; i < zx_pll->count; i++) {
> + if (hw_cfg0 == config[i].cfg0 && hw_cfg1 == config[i].cfg1)
> + return i;
> + }
> +
> + return -1;
How about a real error code? -EINVAL?
> +}
> +
[...]
> +
> +static int zx_pll_enable(struct clk_hw *hw)
> +{
> + struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
> + unsigned long timeout = jiffies + msecs_to_jiffies(500);
> + u32 reg;
> +
> + reg = readl_relaxed(zx_pll->reg_base);
> + writel_relaxed(reg & ~POWER_DOWN, zx_pll->reg_base);
> +
> + return readl_relaxed_poll_timeout(zx_pll->reg_base, reg,
> + reg & LOCK_FLAG, 0, 100);
> +
This is odd. A return and then more code?
> + while (!(readl_relaxed(zx_pll->reg_base) & LOCK_FLAG)) {
> + if (time_after(jiffies, timeout)) {
> + pr_err("clk %s enable timeout\n",
> + __clk_get_name(hw->clk));
> + break;
> + }
> + }
> +
> + return 0;
> +}
> +
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2015-06-03 23:50 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-05-29 2:39 [PATCH v5 2/4] clk: zx: add clock support to zx296702 Jun Nie
2015-05-29 2:39 ` [PATCH v5 3/4] ARM: dts: zx: add an initial zx296702 dts and doc Jun Nie
2015-05-29 2:39 ` [PATCH v5 4/4] ARM: zx: Add basic defconfig support for ZX296702 Jun Nie
2015-05-29 2:41 ` [PATCH v5 2/4] clk: zx: add clock support to zx296702 Jun Nie
2015-06-03 23:51 ` Stephen Boyd
2015-06-04 3:16 ` Jun Nie
2015-06-03 23:50 ` Stephen Boyd [this message]
2015-06-04 3:15 ` Jun Nie
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20150603235021.GC490@codeaurora.org \
--to=sboyd@codeaurora.org \
--cc=linux-arm-kernel@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.