From: "Michael S. Tsirkin" <mst@redhat.com>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: lersek@redhat.com, qemu-devel@nongnu.org, kraxel@redhat.com
Subject: Re: [Qemu-devel] [PATCH v2 23/23] ich9: implement SMI_LOCK
Date: Thu, 4 Jun 2015 14:53:23 +0200 [thread overview]
Message-ID: <20150604145317-mutt-send-email-mst@redhat.com> (raw)
In-Reply-To: <1433351328-23326-24-git-send-email-pbonzini@redhat.com>
On Wed, Jun 03, 2015 at 07:08:48PM +0200, Paolo Bonzini wrote:
> From: Gerd Hoffmann <kraxel@redhat.com>
>
> Add write mask for the smi enable register, so we can disable write
> access to certain bits. Open all bits on reset. Disable write access
> to GBL_SMI_EN when SMI_LOCK (in ich9 lpc pci config space) is set.
> Write access to SMI_LOCK itself is disabled too.
>
> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
> ---
> hw/acpi/ich9.c | 4 +++-
> hw/isa/lpc_ich9.c | 19 +++++++++++++++++++
> include/hw/acpi/ich9.h | 1 +
> include/hw/i386/ich9.h | 6 ++++++
> 4 files changed, 29 insertions(+), 1 deletion(-)
>
> diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c
> index 84e5bb8..ec0e008 100644
> --- a/hw/acpi/ich9.c
> +++ b/hw/acpi/ich9.c
> @@ -94,7 +94,8 @@ static void ich9_smi_writel(void *opaque, hwaddr addr, uint64_t val,
> ICH9LPCPMRegs *pm = opaque;
> switch (addr) {
> case 0:
> - pm->smi_en = val;
> + pm->smi_en &= ~pm->smi_en_wmask;
> + pm->smi_en |= (val & pm->smi_en_wmask);
> break;
> }
> }
> @@ -198,6 +199,7 @@ static void pm_reset(void *opaque)
> * support SMM mode. */
> pm->smi_en |= ICH9_PMIO_SMI_EN_APMC_EN;
> }
> + pm->smi_en_wmask = ~0;
>
> acpi_update_sci(&pm->acpi_regs, pm->irq);
> }
> diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c
> index dba7585..0269cfe 100644
> --- a/hw/isa/lpc_ich9.c
> +++ b/hw/isa/lpc_ich9.c
> @@ -410,12 +410,28 @@ static void ich9_lpc_rcba_update(ICH9LPCState *lpc, uint32_t rbca_old)
> }
> }
>
> +/* config:GEN_PMCON* */
> +static void
> +ich9_lpc_pmcon_update(ICH9LPCState *lpc)
> +{
> + uint16_t gen_pmcon_1 = pci_get_word(lpc->d.config + ICH9_LPC_GEN_PMCON_1);
> + uint16_t wmask;
> +
> + if (gen_pmcon_1 & ICH9_LPC_GEN_PMCON_1_SMI_LOCK) {
> + wmask = pci_get_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1);
> + wmask &= ~ICH9_LPC_GEN_PMCON_1_SMI_LOCK;
> + pci_set_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1, wmask);
> + lpc->pm.smi_en_wmask &= ~1;
> + }
> +}
> +
> static int ich9_lpc_post_load(void *opaque, int version_id)
> {
> ICH9LPCState *lpc = opaque;
>
> ich9_lpc_pmbase_update(lpc);
> ich9_lpc_rcba_update(lpc, 0 /* disabled ICH9_LPC_RBCA_EN */);
> + ich9_lpc_pmcon_update(lpc);
> return 0;
> }
>
> @@ -438,6 +454,9 @@ static void ich9_lpc_config_write(PCIDevice *d,
> if (ranges_overlap(addr, len, ICH9_LPC_PIRQE_ROUT, 4)) {
> pci_bus_fire_intx_routing_notifier(lpc->d.bus);
> }
> + if (ranges_overlap(addr, len, ICH9_LPC_GEN_PMCON_1, 8)) {
> + ich9_lpc_pmcon_update(lpc);
> + }
> }
>
> static void ich9_lpc_reset(DeviceState *qdev)
> diff --git a/include/hw/acpi/ich9.h b/include/hw/acpi/ich9.h
> index c2d3dba..77cc65c 100644
> --- a/include/hw/acpi/ich9.h
> +++ b/include/hw/acpi/ich9.h
> @@ -39,6 +39,7 @@ typedef struct ICH9LPCPMRegs {
> MemoryRegion io_smi;
>
> uint32_t smi_en;
> + uint32_t smi_en_wmask;
> uint32_t smi_sts;
>
> qemu_irq irq; /* SCI */
> diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h
> index f4e522c..a2cc15c 100644
> --- a/include/hw/i386/ich9.h
> +++ b/include/hw/i386/ich9.h
> @@ -152,6 +152,12 @@ Object *ich9_lpc_find(void);
> #define ICH9_LPC_PIRQ_ROUT_MASK Q35_MASK(8, 3, 0)
> #define ICH9_LPC_PIRQ_ROUT_DEFAULT 0x80
>
> +#define ICH9_LPC_GEN_PMCON_1 0xa0
> +#define ICH9_LPC_GEN_PMCON_1_SMI_LOCK (1 << 4)
> +#define ICH9_LPC_GEN_PMCON_2 0xa2
> +#define ICH9_LPC_GEN_PMCON_3 0xa4
> +#define ICH9_LPC_GEN_PMCON_LOCK 0xa6
> +
> #define ICH9_LPC_RCBA 0xf0
> #define ICH9_LPC_RCBA_BA_MASK Q35_MASK(32, 31, 14)
> #define ICH9_LPC_RCBA_EN 0x1
> --
> 2.4.1
next prev parent reply other threads:[~2015-06-04 12:53 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-03 17:08 [Qemu-devel] [PATCH v2 00/23] SMM improvements (chipset and TCG parts) Paolo Bonzini
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 01/23] target-i386: introduce cpu_get_mem_attrs Paolo Bonzini
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 02/23] target-i386: Use correct memory attributes for memory accesses Paolo Bonzini
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 03/23] target-i386: Use correct memory attributes for ioport accesses Paolo Bonzini
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 04/23] target-i386: mask NMIs on entry to SMM Paolo Bonzini
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 05/23] target-i386: set G=1 in SMM big real mode selectors Paolo Bonzini
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 06/23] target-i386: wake up processors that receive an SMI Paolo Bonzini
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 07/23] pflash_cfi01: change big-endian property to BIT type Paolo Bonzini
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 08/23] pflash_cfi01: change to new-style MMIO accessors Paolo Bonzini
2015-06-04 6:19 ` Peter Crosthwaite
2015-06-04 8:02 ` Paolo Bonzini
2015-06-04 12:51 ` Laszlo Ersek
2015-06-09 18:08 ` Richard Henderson
2015-06-09 18:47 ` Michael S. Tsirkin
2015-06-17 7:56 ` Paolo Bonzini
2015-06-17 8:22 ` Markus Armbruster
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 09/23] pflash_cfi01: add secure property Paolo Bonzini
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 10/23] vl: allow full-blown QemuOpts syntax for -global Paolo Bonzini
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 11/23] qom: add object_property_add_const_link Paolo Bonzini
2015-06-04 6:33 ` Peter Crosthwaite
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 12/23] vl: run "late" notifiers immediately Paolo Bonzini
2015-06-04 6:39 ` Peter Crosthwaite
2015-06-04 8:03 ` Paolo Bonzini
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 13/23] target-i386: create a separate AddressSpace for each CPU Paolo Bonzini
2015-06-03 17:58 ` Peter Crosthwaite
2015-06-04 8:02 ` Paolo Bonzini
2015-06-04 12:48 ` Laszlo Ersek
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 14/23] hw/i386: add a separate region that tracks the SMRAME bit Paolo Bonzini
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 15/23] target-i386: use memory API to implement SMRAM Paolo Bonzini
2015-06-04 7:19 ` Peter Crosthwaite
2015-06-04 8:05 ` Paolo Bonzini
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 16/23] hw/i386: remove smram_update Paolo Bonzini
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 17/23] q35: implement high SMRAM Paolo Bonzini
2015-06-04 12:50 ` Michael S. Tsirkin
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 18/23] q35: fix ESMRAMC default Paolo Bonzini
2015-06-04 12:51 ` Michael S. Tsirkin
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 19/23] q35: add config space wmask for SMRAM and ESMRAMC Paolo Bonzini
2015-06-04 12:51 ` Michael S. Tsirkin
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 20/23] q35: implement SMRAM.D_LCK Paolo Bonzini
2015-06-04 12:51 ` Michael S. Tsirkin
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 21/23] q35: add test for SMRAM.D_LCK Paolo Bonzini
2015-06-04 12:52 ` Michael S. Tsirkin
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 22/23] q35: implement TSEG Paolo Bonzini
2015-06-04 12:53 ` Michael S. Tsirkin
2015-06-03 17:08 ` [Qemu-devel] [PATCH v2 23/23] ich9: implement SMI_LOCK Paolo Bonzini
2015-06-04 12:53 ` Michael S. Tsirkin [this message]
2015-06-03 17:41 ` [Qemu-devel] [PATCH v2 00/23] SMM improvements (chipset and TCG parts) Laszlo Ersek
2015-06-03 17:44 ` Paolo Bonzini
2015-06-04 12:54 ` Michael S. Tsirkin
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