From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39531) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0o8x-0003xJ-5i for qemu-devel@nongnu.org; Fri, 05 Jun 2015 05:42:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z0o8v-0007yd-Sk for qemu-devel@nongnu.org; Fri, 05 Jun 2015 05:42:27 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:101::1]:48366) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0o8v-0007yK-Mb for qemu-devel@nongnu.org; Fri, 05 Jun 2015 05:42:25 -0400 Date: Fri, 5 Jun 2015 11:42:22 +0200 From: Aurelien Jarno Message-ID: <20150605094222.GA12018@aurel32.net> References: <1433433631-5322-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1433433631-5322-1-git-send-email-leon.alrae@imgtec.com> Subject: Re: [Qemu-devel] [PATCH] target-mips: add ERETNC instruction and Config5.LLB bit List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Leon Alrae Cc: qemu-devel@nongnu.org On 2015-06-04 17:00, Leon Alrae wrote: > ERETNC is identical to ERET except that an ERETNC will not clear the LLbit > that is set by execution of an LL instruction, and thus when placed between > an LL and SC sequence, will never cause the SC to fail. > > Presence of ERETNC is denoted by the Config5.LLB. > > Signed-off-by: Leon Alrae > --- > disas/mips.c | 1 + > target-mips/cpu.h | 1 + > target-mips/helper.h | 1 + > target-mips/op_helper.c | 12 +++++++++++- > target-mips/translate.c | 20 +++++++++++++++----- > target-mips/translate_init.c | 4 +++- > 6 files changed, 32 insertions(+), 7 deletions(-) Reviewed-by: Aurelien Jarno As a side note, I have seen that you have added a check for MIPS2 to the ERET instruction. This is correct, but given in practice we don't emulate any MIPS1 CPU, I do wonder if it's not the time to make MIPS2 the basic instruction set and remove all MIPS2 checks. -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://www.aurel32.net