From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/3] drm/i915: Enable resource streamer bits on MI_BATCH_BUFFER_START
Date: Mon, 8 Jun 2015 19:10:34 +0300 [thread overview]
Message-ID: <20150608161034.GD5176@intel.com> (raw)
In-Reply-To: <1433757849-3139-2-git-send-email-abdiel.janulgue@linux.intel.com>
On Mon, Jun 08, 2015 at 01:04:07PM +0300, Abdiel Janulgue wrote:
> Adds support for executing the resource streamer on BDW and HSW
>
> v2: Add support for Execlists (Minu Mathai <minu.mathai@intel.com>)
>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_lrc.c | 4 +++-
> drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++++--
> drivers/gpu/drm/i915/intel_ringbuffer.h | 1 +
> 4 files changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b522eb6..238bb25 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -356,6 +356,7 @@
> #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
> #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
> #define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
> +#define MI_BATCH_RESOURCE_STREAMER (1<<10)
>
> #define MI_PREDICATE_SRC0 (0x2400)
> #define MI_PREDICATE_SRC1 (0x2408)
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index fcb074b..3b168f6 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1172,7 +1172,9 @@ static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf,
> return ret;
>
> /* FIXME(BDW): Address space and security selectors. */
> - intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
> + intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 |
> + (ppgtt<<8) | (I915_DISPATCH_RS ?
That doesn't look right.
> + MI_BATCH_RESOURCE_STREAMER : 0));
> intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
> intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
> intel_logical_ring_emit(ringbuf, MI_NOOP);
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 441e250..715cb2a 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -2385,7 +2385,9 @@ gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
> return ret;
>
> /* FIXME(BDW): Address space and security selectors. */
> - intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
> + intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
> + (dispatch_flags & I915_DISPATCH_RS ?
> + MI_BATCH_RESOURCE_STREAMER : 0));
> intel_ring_emit(ring, lower_32_bits(offset));
> intel_ring_emit(ring, upper_32_bits(offset));
> intel_ring_emit(ring, MI_NOOP);
> @@ -2408,7 +2410,9 @@ hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
> intel_ring_emit(ring,
> MI_BATCH_BUFFER_START |
> (dispatch_flags & I915_DISPATCH_SECURE ?
> - 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
> + 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
> + (dispatch_flags & I915_DISPATCH_RS ?
> + MI_BATCH_RESOURCE_STREAMER : 0));
> /* bit0-7 is the length on GEN6+ */
> intel_ring_emit(ring, offset);
> intel_ring_advance(ring);
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index c761fe0..3521bc0 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -167,6 +167,7 @@ struct intel_engine_cs {
> unsigned dispatch_flags);
> #define I915_DISPATCH_SECURE 0x1
> #define I915_DISPATCH_PINNED 0x2
> +#define I915_DISPATCH_RS 0x4
> void (*cleanup)(struct intel_engine_cs *ring);
>
> /* GEN8 signal/wait table - never trust comments!
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2015-06-08 16:18 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-08 10:04 drm/i915/hsw/bdw: Enable resource streamer v3 Abdiel Janulgue
2015-06-08 10:04 ` [PATCH 1/3] drm/i915: Enable resource streamer bits on MI_BATCH_BUFFER_START Abdiel Janulgue
2015-06-08 16:10 ` Ville Syrjälä [this message]
2015-06-08 17:42 ` Abdiel Janulgue
2015-06-08 17:55 ` Chris Wilson
2015-06-09 11:48 ` Dave Gordon
2015-06-08 10:04 ` [PATCH 2/3] drm/i915: Enable Resource Streamer state save/restore Abdiel Janulgue
2015-06-08 10:04 ` [PATCH 3/3] drm/i915: Expose I915_EXEC_RESOURCE_STREAMER flag Abdiel Janulgue
2015-06-13 15:41 ` shuang.he
2015-06-08 15:40 ` drm/i915/hsw/bdw: Enable resource streamer v3 Abdiel Janulgue
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20150608161034.GD5176@intel.com \
--to=ville.syrjala@linux.intel.com \
--cc=abdiel.janulgue@linux.intel.com \
--cc=intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.