diff for duplicates of <20150610021315.6017.58085@quantum> diff --git a/a/1.txt b/N1/1.txt index 8b10b8a..5a762bb 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,131 +1,71 @@ Quoting Joachim Eastwood (2015-05-28 13:31:45) -> +static struct lpc18xx_clk_branch clk_branches[] =3D { -> + {"base_apb3_clk", "apb3_bus", CLK_APB3_BUS, C= -CU_BRANCH_IS_BUS}, -> + {"base_apb3_clk", "apb3_i2c1", CLK_APB3_I2C1, 0= -}, -> + {"base_apb3_clk", "apb3_dac", CLK_APB3_DAC, 0= -}, -> + {"base_apb3_clk", "apb3_adc0", CLK_APB3_ADC0, 0= -}, -> + {"base_apb3_clk", "apb3_adc1", CLK_APB3_ADC1, 0= -}, -> + {"base_apb3_clk", "apb3_can0", CLK_APB3_CAN0, 0= -}, +> +static struct lpc18xx_clk_branch clk_branches[] = { +> + {"base_apb3_clk", "apb3_bus", CLK_APB3_BUS, CCU_BRANCH_IS_BUS}, +> + {"base_apb3_clk", "apb3_i2c1", CLK_APB3_I2C1, 0}, +> + {"base_apb3_clk", "apb3_dac", CLK_APB3_DAC, 0}, +> + {"base_apb3_clk", "apb3_adc0", CLK_APB3_ADC0, 0}, +> + {"base_apb3_clk", "apb3_adc1", CLK_APB3_ADC1, 0}, +> + {"base_apb3_clk", "apb3_can0", CLK_APB3_CAN0, 0}, > + -> + {"base_apb1_clk", "apb1_bus", CLK_APB1_BUS, C= -CU_BRANCH_IS_BUS}, -> + {"base_apb1_clk", "apb1_mc_pwm", CLK_APB1_MOTOCON_PWM, 0= -}, -> + {"base_apb1_clk", "apb1_i2c0", CLK_APB1_I2C0, 0= -}, -> + {"base_apb1_clk", "apb1_i2s", CLK_APB1_I2S, 0= -}, -> + {"base_apb1_clk", "apb1_can1", CLK_APB1_CAN1, 0= -}, +> + {"base_apb1_clk", "apb1_bus", CLK_APB1_BUS, CCU_BRANCH_IS_BUS}, +> + {"base_apb1_clk", "apb1_mc_pwm", CLK_APB1_MOTOCON_PWM, 0}, +> + {"base_apb1_clk", "apb1_i2c0", CLK_APB1_I2C0, 0}, +> + {"base_apb1_clk", "apb1_i2s", CLK_APB1_I2S, 0}, +> + {"base_apb1_clk", "apb1_can1", CLK_APB1_CAN1, 0}, > + -> + {"base_spifi_clk", "spifi", CLK_SPIFI, 0= -}, +> + {"base_spifi_clk", "spifi", CLK_SPIFI, 0}, > + -> + {"base_cpu_clk", "cpu_bus", CLK_CPU_BUS, C= -CU_BRANCH_IS_BUS}, -> + {"base_cpu_clk", "cpu_spifi", CLK_CPU_SPIFI, 0= -}, -> + {"base_cpu_clk", "cpu_gpio", CLK_CPU_GPIO, 0= -}, -> + {"base_cpu_clk", "cpu_lcd", CLK_CPU_LCD, 0= -}, -> + {"base_cpu_clk", "cpu_ethernet", CLK_CPU_ETHERNET, 0= -}, -> + {"base_cpu_clk", "cpu_usb0", CLK_CPU_USB0, 0= -}, -> + {"base_cpu_clk", "cpu_emc", CLK_CPU_EMC, 0= -}, -> + {"base_cpu_clk", "cpu_sdio", CLK_CPU_SDIO, 0= -}, -> + {"base_cpu_clk", "cpu_dma", CLK_CPU_DMA, 0= -}, -> + {"base_cpu_clk", "cpu_core", CLK_CPU_CORE, 0= -}, -> + {"base_cpu_clk", "cpu_sct", CLK_CPU_SCT, 0= -}, -> + {"base_cpu_clk", "cpu_usb1", CLK_CPU_USB1, 0= -}, -> + {"base_cpu_clk", "cpu_emcdiv", CLK_CPU_EMCDIV, C= -CU_BRANCH_HAVE_DIV2}, -> + {"base_cpu_clk", "cpu_flasha", CLK_CPU_FLASHA, C= -CU_BRANCH_HAVE_DIV2}, -> + {"base_cpu_clk", "cpu_flashb", CLK_CPU_FLASHB, C= -CU_BRANCH_HAVE_DIV2}, -> + {"base_cpu_clk", "cpu_m0app", CLK_CPU_M0APP, C= -CU_BRANCH_HAVE_DIV2}, -> + {"base_cpu_clk", "cpu_adchs", CLK_CPU_ADCHS, C= -CU_BRANCH_HAVE_DIV2}, -> + {"base_cpu_clk", "cpu_eeprom", CLK_CPU_EEPROM, C= -CU_BRANCH_HAVE_DIV2}, -> + {"base_cpu_clk", "cpu_wwdt", CLK_CPU_WWDT, 0= -}, -> + {"base_cpu_clk", "cpu_uart0", CLK_CPU_UART0, 0= -}, -> + {"base_cpu_clk", "cpu_uart1", CLK_CPU_UART1, 0= -}, -> + {"base_cpu_clk", "cpu_ssp0", CLK_CPU_SSP0, 0= -}, -> + {"base_cpu_clk", "cpu_timer0", CLK_CPU_TIMER0, 0= -}, -> + {"base_cpu_clk", "cpu_timer1", CLK_CPU_TIMER1, 0= -}, -> + {"base_cpu_clk", "cpu_scu", CLK_CPU_SCU, 0= -}, -> + {"base_cpu_clk", "cpu_creg", CLK_CPU_CREG, 0= -}, -> + {"base_cpu_clk", "cpu_ritimer", CLK_CPU_RITIMER, 0= -}, -> + {"base_cpu_clk", "cpu_uart2", CLK_CPU_UART2, 0= -}, -> + {"base_cpu_clk", "cpu_uart3", CLK_CPU_UART3, 0= -}, -> + {"base_cpu_clk", "cpu_timer2", CLK_CPU_TIMER2, 0= -}, -> + {"base_cpu_clk", "cpu_timer3", CLK_CPU_TIMER3, 0= -}, -> + {"base_cpu_clk", "cpu_ssp1", CLK_CPU_SSP1, 0= -}, -> + {"base_cpu_clk", "cpu_qei", CLK_CPU_QEI, 0= -}, +> + {"base_cpu_clk", "cpu_bus", CLK_CPU_BUS, CCU_BRANCH_IS_BUS}, +> + {"base_cpu_clk", "cpu_spifi", CLK_CPU_SPIFI, 0}, +> + {"base_cpu_clk", "cpu_gpio", CLK_CPU_GPIO, 0}, +> + {"base_cpu_clk", "cpu_lcd", CLK_CPU_LCD, 0}, +> + {"base_cpu_clk", "cpu_ethernet", CLK_CPU_ETHERNET, 0}, +> + {"base_cpu_clk", "cpu_usb0", CLK_CPU_USB0, 0}, +> + {"base_cpu_clk", "cpu_emc", CLK_CPU_EMC, 0}, +> + {"base_cpu_clk", "cpu_sdio", CLK_CPU_SDIO, 0}, +> + {"base_cpu_clk", "cpu_dma", CLK_CPU_DMA, 0}, +> + {"base_cpu_clk", "cpu_core", CLK_CPU_CORE, 0}, +> + {"base_cpu_clk", "cpu_sct", CLK_CPU_SCT, 0}, +> + {"base_cpu_clk", "cpu_usb1", CLK_CPU_USB1, 0}, +> + {"base_cpu_clk", "cpu_emcdiv", CLK_CPU_EMCDIV, CCU_BRANCH_HAVE_DIV2}, +> + {"base_cpu_clk", "cpu_flasha", CLK_CPU_FLASHA, CCU_BRANCH_HAVE_DIV2}, +> + {"base_cpu_clk", "cpu_flashb", CLK_CPU_FLASHB, CCU_BRANCH_HAVE_DIV2}, +> + {"base_cpu_clk", "cpu_m0app", CLK_CPU_M0APP, CCU_BRANCH_HAVE_DIV2}, +> + {"base_cpu_clk", "cpu_adchs", CLK_CPU_ADCHS, CCU_BRANCH_HAVE_DIV2}, +> + {"base_cpu_clk", "cpu_eeprom", CLK_CPU_EEPROM, CCU_BRANCH_HAVE_DIV2}, +> + {"base_cpu_clk", "cpu_wwdt", CLK_CPU_WWDT, 0}, +> + {"base_cpu_clk", "cpu_uart0", CLK_CPU_UART0, 0}, +> + {"base_cpu_clk", "cpu_uart1", CLK_CPU_UART1, 0}, +> + {"base_cpu_clk", "cpu_ssp0", CLK_CPU_SSP0, 0}, +> + {"base_cpu_clk", "cpu_timer0", CLK_CPU_TIMER0, 0}, +> + {"base_cpu_clk", "cpu_timer1", CLK_CPU_TIMER1, 0}, +> + {"base_cpu_clk", "cpu_scu", CLK_CPU_SCU, 0}, +> + {"base_cpu_clk", "cpu_creg", CLK_CPU_CREG, 0}, +> + {"base_cpu_clk", "cpu_ritimer", CLK_CPU_RITIMER, 0}, +> + {"base_cpu_clk", "cpu_uart2", CLK_CPU_UART2, 0}, +> + {"base_cpu_clk", "cpu_uart3", CLK_CPU_UART3, 0}, +> + {"base_cpu_clk", "cpu_timer2", CLK_CPU_TIMER2, 0}, +> + {"base_cpu_clk", "cpu_timer3", CLK_CPU_TIMER3, 0}, +> + {"base_cpu_clk", "cpu_ssp1", CLK_CPU_SSP1, 0}, +> + {"base_cpu_clk", "cpu_qei", CLK_CPU_QEI, 0}, > + -> + {"base_periph_clk", "periph_bus", CLK_PERIPH_BUS, C= -CU_BRANCH_IS_BUS}, -> + {"base_periph_clk", "periph_core", CLK_PERIPH_CORE, 0= -}, -> + {"base_periph_clk", "periph_sgpio", CLK_PERIPH_SGPIO, 0= -}, +> + {"base_periph_clk", "periph_bus", CLK_PERIPH_BUS, CCU_BRANCH_IS_BUS}, +> + {"base_periph_clk", "periph_core", CLK_PERIPH_CORE, 0}, +> + {"base_periph_clk", "periph_sgpio", CLK_PERIPH_SGPIO, 0}, > + -> + {"base_usb0_clk", "usb0", CLK_USB0, 0= -}, -> + {"base_usb1_clk", "usb1", CLK_USB1, 0= -}, -> + {"base_spi_clk", "spi", CLK_SPI, 0= -}, -> + {"base_adchs_clk", "adchs", CLK_ADCHS, 0= -}, +> + {"base_usb0_clk", "usb0", CLK_USB0, 0}, +> + {"base_usb1_clk", "usb1", CLK_USB1, 0}, +> + {"base_spi_clk", "spi", CLK_SPI, 0}, +> + {"base_adchs_clk", "adchs", CLK_ADCHS, 0}, > + -> + {"base_audio_clk", "audio", CLK_AUDIO, 0= -}, -> + {"base_uart3_clk", "apb2_uart3", CLK_APB2_UART3, 0= -}, -> + {"base_uart2_clk", "apb2_uart2", CLK_APB2_UART2, 0= -}, -> + {"base_uart1_clk", "apb0_uart1", CLK_APB0_UART1, 0= -}, -> + {"base_uart0_clk", "apb0_uart0", CLK_APB0_UART0, 0= -}, -> + {"base_ssp1_clk", "apb2_ssp1", CLK_APB2_SSP1, 0= -}, -> + {"base_ssp0_clk", "apb0_ssp0", CLK_APB0_SSP0, 0= -}, -> + {"base_sdio_clk", "sdio", CLK_SDIO, 0= -}, +> + {"base_audio_clk", "audio", CLK_AUDIO, 0}, +> + {"base_uart3_clk", "apb2_uart3", CLK_APB2_UART3, 0}, +> + {"base_uart2_clk", "apb2_uart2", CLK_APB2_UART2, 0}, +> + {"base_uart1_clk", "apb0_uart1", CLK_APB0_UART1, 0}, +> + {"base_uart0_clk", "apb0_uart0", CLK_APB0_UART0, 0}, +> + {"base_ssp1_clk", "apb2_ssp1", CLK_APB2_SSP1, 0}, +> + {"base_ssp0_clk", "apb0_ssp0", CLK_APB0_SSP0, 0}, +> + {"base_sdio_clk", "sdio", CLK_SDIO, 0}, > +}; Hi Joachim, diff --git a/a/content_digest b/N1/content_digest index 62e3a56..395c0b1 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,144 +1,79 @@ "ref\01432845107-12458-1-git-send-email-manabian@gmail.com\0" "ref\01432845107-12458-4-git-send-email-manabian@gmail.com\0" - "From\0Michael Turquette <mturquette@linaro.org>\0" - "Subject\0Re: [PATCH v4 3/5] clk: add lpc18xx ccu clk driver\0" + "From\0mturquette@linaro.org (Michael Turquette)\0" + "Subject\0[PATCH v4 3/5] clk: add lpc18xx ccu clk driver\0" "Date\0Tue, 09 Jun 2015 19:13:15 -0700\0" - "To\0Joachim Eastwood <manabian@gmail.com>" - " sboyd@codeaurora.org\0" - "Cc\0Joachim Eastwood <manabian@gmail.com>" - linux-clk@vger.kernel.org - devicetree@vger.kernel.org - " linux-arm-kernel@lists.infradead.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Quoting Joachim Eastwood (2015-05-28 13:31:45)\n" - "> +static struct lpc18xx_clk_branch clk_branches[] =3D {\n" - "> + {\"base_apb3_clk\", \"apb3_bus\", CLK_APB3_BUS, C=\n" - "CU_BRANCH_IS_BUS},\n" - "> + {\"base_apb3_clk\", \"apb3_i2c1\", CLK_APB3_I2C1, 0=\n" - "},\n" - "> + {\"base_apb3_clk\", \"apb3_dac\", CLK_APB3_DAC, 0=\n" - "},\n" - "> + {\"base_apb3_clk\", \"apb3_adc0\", CLK_APB3_ADC0, 0=\n" - "},\n" - "> + {\"base_apb3_clk\", \"apb3_adc1\", CLK_APB3_ADC1, 0=\n" - "},\n" - "> + {\"base_apb3_clk\", \"apb3_can0\", CLK_APB3_CAN0, 0=\n" - "},\n" + "> +static struct lpc18xx_clk_branch clk_branches[] = {\n" + "> + {\"base_apb3_clk\", \"apb3_bus\", CLK_APB3_BUS, CCU_BRANCH_IS_BUS},\n" + "> + {\"base_apb3_clk\", \"apb3_i2c1\", CLK_APB3_I2C1, 0},\n" + "> + {\"base_apb3_clk\", \"apb3_dac\", CLK_APB3_DAC, 0},\n" + "> + {\"base_apb3_clk\", \"apb3_adc0\", CLK_APB3_ADC0, 0},\n" + "> + {\"base_apb3_clk\", \"apb3_adc1\", CLK_APB3_ADC1, 0},\n" + "> + {\"base_apb3_clk\", \"apb3_can0\", CLK_APB3_CAN0, 0},\n" "> +\n" - "> + {\"base_apb1_clk\", \"apb1_bus\", CLK_APB1_BUS, C=\n" - "CU_BRANCH_IS_BUS},\n" - "> + {\"base_apb1_clk\", \"apb1_mc_pwm\", CLK_APB1_MOTOCON_PWM, 0=\n" - "},\n" - "> + {\"base_apb1_clk\", \"apb1_i2c0\", CLK_APB1_I2C0, 0=\n" - "},\n" - "> + {\"base_apb1_clk\", \"apb1_i2s\", CLK_APB1_I2S, 0=\n" - "},\n" - "> + {\"base_apb1_clk\", \"apb1_can1\", CLK_APB1_CAN1, 0=\n" - "},\n" + "> + {\"base_apb1_clk\", \"apb1_bus\", CLK_APB1_BUS, CCU_BRANCH_IS_BUS},\n" + "> + {\"base_apb1_clk\", \"apb1_mc_pwm\", CLK_APB1_MOTOCON_PWM, 0},\n" + "> + {\"base_apb1_clk\", \"apb1_i2c0\", CLK_APB1_I2C0, 0},\n" + "> + {\"base_apb1_clk\", \"apb1_i2s\", CLK_APB1_I2S, 0},\n" + "> + {\"base_apb1_clk\", \"apb1_can1\", CLK_APB1_CAN1, 0},\n" "> +\n" - "> + {\"base_spifi_clk\", \"spifi\", CLK_SPIFI, 0=\n" - "},\n" + "> + {\"base_spifi_clk\", \"spifi\", CLK_SPIFI, 0},\n" "> +\n" - "> + {\"base_cpu_clk\", \"cpu_bus\", CLK_CPU_BUS, C=\n" - "CU_BRANCH_IS_BUS},\n" - "> + {\"base_cpu_clk\", \"cpu_spifi\", CLK_CPU_SPIFI, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_gpio\", CLK_CPU_GPIO, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_lcd\", CLK_CPU_LCD, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_ethernet\", CLK_CPU_ETHERNET, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_usb0\", CLK_CPU_USB0, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_emc\", CLK_CPU_EMC, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_sdio\", CLK_CPU_SDIO, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_dma\", CLK_CPU_DMA, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_core\", CLK_CPU_CORE, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_sct\", CLK_CPU_SCT, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_usb1\", CLK_CPU_USB1, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_emcdiv\", CLK_CPU_EMCDIV, C=\n" - "CU_BRANCH_HAVE_DIV2},\n" - "> + {\"base_cpu_clk\", \"cpu_flasha\", CLK_CPU_FLASHA, C=\n" - "CU_BRANCH_HAVE_DIV2},\n" - "> + {\"base_cpu_clk\", \"cpu_flashb\", CLK_CPU_FLASHB, C=\n" - "CU_BRANCH_HAVE_DIV2},\n" - "> + {\"base_cpu_clk\", \"cpu_m0app\", CLK_CPU_M0APP, C=\n" - "CU_BRANCH_HAVE_DIV2},\n" - "> + {\"base_cpu_clk\", \"cpu_adchs\", CLK_CPU_ADCHS, C=\n" - "CU_BRANCH_HAVE_DIV2},\n" - "> + {\"base_cpu_clk\", \"cpu_eeprom\", CLK_CPU_EEPROM, C=\n" - "CU_BRANCH_HAVE_DIV2},\n" - "> + {\"base_cpu_clk\", \"cpu_wwdt\", CLK_CPU_WWDT, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_uart0\", CLK_CPU_UART0, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_uart1\", CLK_CPU_UART1, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_ssp0\", CLK_CPU_SSP0, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_timer0\", CLK_CPU_TIMER0, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_timer1\", CLK_CPU_TIMER1, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_scu\", CLK_CPU_SCU, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_creg\", CLK_CPU_CREG, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_ritimer\", CLK_CPU_RITIMER, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_uart2\", CLK_CPU_UART2, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_uart3\", CLK_CPU_UART3, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_timer2\", CLK_CPU_TIMER2, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_timer3\", CLK_CPU_TIMER3, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_ssp1\", CLK_CPU_SSP1, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_qei\", CLK_CPU_QEI, 0=\n" - "},\n" + "> + {\"base_cpu_clk\", \"cpu_bus\", CLK_CPU_BUS, CCU_BRANCH_IS_BUS},\n" + "> + {\"base_cpu_clk\", \"cpu_spifi\", CLK_CPU_SPIFI, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_gpio\", CLK_CPU_GPIO, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_lcd\", CLK_CPU_LCD, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_ethernet\", CLK_CPU_ETHERNET, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_usb0\", CLK_CPU_USB0, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_emc\", CLK_CPU_EMC, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_sdio\", CLK_CPU_SDIO, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_dma\", CLK_CPU_DMA, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_core\", CLK_CPU_CORE, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_sct\", CLK_CPU_SCT, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_usb1\", CLK_CPU_USB1, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_emcdiv\", CLK_CPU_EMCDIV, CCU_BRANCH_HAVE_DIV2},\n" + "> + {\"base_cpu_clk\", \"cpu_flasha\", CLK_CPU_FLASHA, CCU_BRANCH_HAVE_DIV2},\n" + "> + {\"base_cpu_clk\", \"cpu_flashb\", CLK_CPU_FLASHB, CCU_BRANCH_HAVE_DIV2},\n" + "> + {\"base_cpu_clk\", \"cpu_m0app\", CLK_CPU_M0APP, CCU_BRANCH_HAVE_DIV2},\n" + "> + {\"base_cpu_clk\", \"cpu_adchs\", CLK_CPU_ADCHS, CCU_BRANCH_HAVE_DIV2},\n" + "> + {\"base_cpu_clk\", \"cpu_eeprom\", CLK_CPU_EEPROM, CCU_BRANCH_HAVE_DIV2},\n" + "> + {\"base_cpu_clk\", \"cpu_wwdt\", CLK_CPU_WWDT, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_uart0\", CLK_CPU_UART0, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_uart1\", CLK_CPU_UART1, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_ssp0\", CLK_CPU_SSP0, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_timer0\", CLK_CPU_TIMER0, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_timer1\", CLK_CPU_TIMER1, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_scu\", CLK_CPU_SCU, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_creg\", CLK_CPU_CREG, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_ritimer\", CLK_CPU_RITIMER, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_uart2\", CLK_CPU_UART2, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_uart3\", CLK_CPU_UART3, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_timer2\", CLK_CPU_TIMER2, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_timer3\", CLK_CPU_TIMER3, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_ssp1\", CLK_CPU_SSP1, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_qei\", CLK_CPU_QEI, 0},\n" "> +\n" - "> + {\"base_periph_clk\", \"periph_bus\", CLK_PERIPH_BUS, C=\n" - "CU_BRANCH_IS_BUS},\n" - "> + {\"base_periph_clk\", \"periph_core\", CLK_PERIPH_CORE, 0=\n" - "},\n" - "> + {\"base_periph_clk\", \"periph_sgpio\", CLK_PERIPH_SGPIO, 0=\n" - "},\n" + "> + {\"base_periph_clk\", \"periph_bus\", CLK_PERIPH_BUS, CCU_BRANCH_IS_BUS},\n" + "> + {\"base_periph_clk\", \"periph_core\", CLK_PERIPH_CORE, 0},\n" + "> + {\"base_periph_clk\", \"periph_sgpio\", CLK_PERIPH_SGPIO, 0},\n" "> +\n" - "> + {\"base_usb0_clk\", \"usb0\", CLK_USB0, 0=\n" - "},\n" - "> + {\"base_usb1_clk\", \"usb1\", CLK_USB1, 0=\n" - "},\n" - "> + {\"base_spi_clk\", \"spi\", CLK_SPI, 0=\n" - "},\n" - "> + {\"base_adchs_clk\", \"adchs\", CLK_ADCHS, 0=\n" - "},\n" + "> + {\"base_usb0_clk\", \"usb0\", CLK_USB0, 0},\n" + "> + {\"base_usb1_clk\", \"usb1\", CLK_USB1, 0},\n" + "> + {\"base_spi_clk\", \"spi\", CLK_SPI, 0},\n" + "> + {\"base_adchs_clk\", \"adchs\", CLK_ADCHS, 0},\n" "> +\n" - "> + {\"base_audio_clk\", \"audio\", CLK_AUDIO, 0=\n" - "},\n" - "> + {\"base_uart3_clk\", \"apb2_uart3\", CLK_APB2_UART3, 0=\n" - "},\n" - "> + {\"base_uart2_clk\", \"apb2_uart2\", CLK_APB2_UART2, 0=\n" - "},\n" - "> + {\"base_uart1_clk\", \"apb0_uart1\", CLK_APB0_UART1, 0=\n" - "},\n" - "> + {\"base_uart0_clk\", \"apb0_uart0\", CLK_APB0_UART0, 0=\n" - "},\n" - "> + {\"base_ssp1_clk\", \"apb2_ssp1\", CLK_APB2_SSP1, 0=\n" - "},\n" - "> + {\"base_ssp0_clk\", \"apb0_ssp0\", CLK_APB0_SSP0, 0=\n" - "},\n" - "> + {\"base_sdio_clk\", \"sdio\", CLK_SDIO, 0=\n" - "},\n" + "> + {\"base_audio_clk\", \"audio\", CLK_AUDIO, 0},\n" + "> + {\"base_uart3_clk\", \"apb2_uart3\", CLK_APB2_UART3, 0},\n" + "> + {\"base_uart2_clk\", \"apb2_uart2\", CLK_APB2_UART2, 0},\n" + "> + {\"base_uart1_clk\", \"apb0_uart1\", CLK_APB0_UART1, 0},\n" + "> + {\"base_uart0_clk\", \"apb0_uart0\", CLK_APB0_UART0, 0},\n" + "> + {\"base_ssp1_clk\", \"apb2_ssp1\", CLK_APB2_SSP1, 0},\n" + "> + {\"base_ssp0_clk\", \"apb0_ssp0\", CLK_APB0_SSP0, 0},\n" + "> + {\"base_sdio_clk\", \"sdio\", CLK_SDIO, 0},\n" "> +};\n" "\n" "Hi Joachim,\n" @@ -159,4 +94,4 @@ "Regards,\n" Mike -23322abd7835f64b233a1e7db250e7f65c97a8f6305a053c34b8002f5557ab98 +8644066c2c1c623d58fe621d91e5fad239346c871599bbf22a8b41ed38a3dba7
diff --git a/a/1.txt b/N2/1.txt index 8b10b8a..e8d78b1 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,131 +1,71 @@ Quoting Joachim Eastwood (2015-05-28 13:31:45) -> +static struct lpc18xx_clk_branch clk_branches[] =3D { -> + {"base_apb3_clk", "apb3_bus", CLK_APB3_BUS, C= -CU_BRANCH_IS_BUS}, -> + {"base_apb3_clk", "apb3_i2c1", CLK_APB3_I2C1, 0= -}, -> + {"base_apb3_clk", "apb3_dac", CLK_APB3_DAC, 0= -}, -> + {"base_apb3_clk", "apb3_adc0", CLK_APB3_ADC0, 0= -}, -> + {"base_apb3_clk", "apb3_adc1", CLK_APB3_ADC1, 0= -}, -> + {"base_apb3_clk", "apb3_can0", CLK_APB3_CAN0, 0= -}, +> +static struct lpc18xx_clk_branch clk_branches[] = { +> + {"base_apb3_clk", "apb3_bus", CLK_APB3_BUS, CCU_BRANCH_IS_BUS}, +> + {"base_apb3_clk", "apb3_i2c1", CLK_APB3_I2C1, 0}, +> + {"base_apb3_clk", "apb3_dac", CLK_APB3_DAC, 0}, +> + {"base_apb3_clk", "apb3_adc0", CLK_APB3_ADC0, 0}, +> + {"base_apb3_clk", "apb3_adc1", CLK_APB3_ADC1, 0}, +> + {"base_apb3_clk", "apb3_can0", CLK_APB3_CAN0, 0}, > + -> + {"base_apb1_clk", "apb1_bus", CLK_APB1_BUS, C= -CU_BRANCH_IS_BUS}, -> + {"base_apb1_clk", "apb1_mc_pwm", CLK_APB1_MOTOCON_PWM, 0= -}, -> + {"base_apb1_clk", "apb1_i2c0", CLK_APB1_I2C0, 0= -}, -> + {"base_apb1_clk", "apb1_i2s", CLK_APB1_I2S, 0= -}, -> + {"base_apb1_clk", "apb1_can1", CLK_APB1_CAN1, 0= -}, +> + {"base_apb1_clk", "apb1_bus", CLK_APB1_BUS, CCU_BRANCH_IS_BUS}, +> + {"base_apb1_clk", "apb1_mc_pwm", CLK_APB1_MOTOCON_PWM, 0}, +> + {"base_apb1_clk", "apb1_i2c0", CLK_APB1_I2C0, 0}, +> + {"base_apb1_clk", "apb1_i2s", CLK_APB1_I2S, 0}, +> + {"base_apb1_clk", "apb1_can1", CLK_APB1_CAN1, 0}, > + -> + {"base_spifi_clk", "spifi", CLK_SPIFI, 0= -}, +> + {"base_spifi_clk", "spifi", CLK_SPIFI, 0}, > + -> + {"base_cpu_clk", "cpu_bus", CLK_CPU_BUS, C= -CU_BRANCH_IS_BUS}, -> + {"base_cpu_clk", "cpu_spifi", CLK_CPU_SPIFI, 0= -}, -> + {"base_cpu_clk", "cpu_gpio", CLK_CPU_GPIO, 0= -}, -> + {"base_cpu_clk", "cpu_lcd", CLK_CPU_LCD, 0= -}, -> + {"base_cpu_clk", "cpu_ethernet", CLK_CPU_ETHERNET, 0= -}, -> + {"base_cpu_clk", "cpu_usb0", CLK_CPU_USB0, 0= -}, -> + {"base_cpu_clk", "cpu_emc", CLK_CPU_EMC, 0= -}, -> + {"base_cpu_clk", "cpu_sdio", CLK_CPU_SDIO, 0= -}, -> + {"base_cpu_clk", "cpu_dma", CLK_CPU_DMA, 0= -}, -> + {"base_cpu_clk", "cpu_core", CLK_CPU_CORE, 0= -}, -> + {"base_cpu_clk", "cpu_sct", CLK_CPU_SCT, 0= -}, -> + {"base_cpu_clk", "cpu_usb1", CLK_CPU_USB1, 0= -}, -> + {"base_cpu_clk", "cpu_emcdiv", CLK_CPU_EMCDIV, C= -CU_BRANCH_HAVE_DIV2}, -> + {"base_cpu_clk", "cpu_flasha", CLK_CPU_FLASHA, C= -CU_BRANCH_HAVE_DIV2}, -> + {"base_cpu_clk", "cpu_flashb", CLK_CPU_FLASHB, C= -CU_BRANCH_HAVE_DIV2}, -> + {"base_cpu_clk", "cpu_m0app", CLK_CPU_M0APP, C= -CU_BRANCH_HAVE_DIV2}, -> + {"base_cpu_clk", "cpu_adchs", CLK_CPU_ADCHS, C= -CU_BRANCH_HAVE_DIV2}, -> + {"base_cpu_clk", "cpu_eeprom", CLK_CPU_EEPROM, C= -CU_BRANCH_HAVE_DIV2}, -> + {"base_cpu_clk", "cpu_wwdt", CLK_CPU_WWDT, 0= -}, -> + {"base_cpu_clk", "cpu_uart0", CLK_CPU_UART0, 0= -}, -> + {"base_cpu_clk", "cpu_uart1", CLK_CPU_UART1, 0= -}, -> + {"base_cpu_clk", "cpu_ssp0", CLK_CPU_SSP0, 0= -}, -> + {"base_cpu_clk", "cpu_timer0", CLK_CPU_TIMER0, 0= -}, -> + {"base_cpu_clk", "cpu_timer1", CLK_CPU_TIMER1, 0= -}, -> + {"base_cpu_clk", "cpu_scu", CLK_CPU_SCU, 0= -}, -> + {"base_cpu_clk", "cpu_creg", CLK_CPU_CREG, 0= -}, -> + {"base_cpu_clk", "cpu_ritimer", CLK_CPU_RITIMER, 0= -}, -> + {"base_cpu_clk", "cpu_uart2", CLK_CPU_UART2, 0= -}, -> + {"base_cpu_clk", "cpu_uart3", CLK_CPU_UART3, 0= -}, -> + {"base_cpu_clk", "cpu_timer2", CLK_CPU_TIMER2, 0= -}, -> + {"base_cpu_clk", "cpu_timer3", CLK_CPU_TIMER3, 0= -}, -> + {"base_cpu_clk", "cpu_ssp1", CLK_CPU_SSP1, 0= -}, -> + {"base_cpu_clk", "cpu_qei", CLK_CPU_QEI, 0= -}, +> + {"base_cpu_clk", "cpu_bus", CLK_CPU_BUS, CCU_BRANCH_IS_BUS}, +> + {"base_cpu_clk", "cpu_spifi", CLK_CPU_SPIFI, 0}, +> + {"base_cpu_clk", "cpu_gpio", CLK_CPU_GPIO, 0}, +> + {"base_cpu_clk", "cpu_lcd", CLK_CPU_LCD, 0}, +> + {"base_cpu_clk", "cpu_ethernet", CLK_CPU_ETHERNET, 0}, +> + {"base_cpu_clk", "cpu_usb0", CLK_CPU_USB0, 0}, +> + {"base_cpu_clk", "cpu_emc", CLK_CPU_EMC, 0}, +> + {"base_cpu_clk", "cpu_sdio", CLK_CPU_SDIO, 0}, +> + {"base_cpu_clk", "cpu_dma", CLK_CPU_DMA, 0}, +> + {"base_cpu_clk", "cpu_core", CLK_CPU_CORE, 0}, +> + {"base_cpu_clk", "cpu_sct", CLK_CPU_SCT, 0}, +> + {"base_cpu_clk", "cpu_usb1", CLK_CPU_USB1, 0}, +> + {"base_cpu_clk", "cpu_emcdiv", CLK_CPU_EMCDIV, CCU_BRANCH_HAVE_DIV2}, +> + {"base_cpu_clk", "cpu_flasha", CLK_CPU_FLASHA, CCU_BRANCH_HAVE_DIV2}, +> + {"base_cpu_clk", "cpu_flashb", CLK_CPU_FLASHB, CCU_BRANCH_HAVE_DIV2}, +> + {"base_cpu_clk", "cpu_m0app", CLK_CPU_M0APP, CCU_BRANCH_HAVE_DIV2}, +> + {"base_cpu_clk", "cpu_adchs", CLK_CPU_ADCHS, CCU_BRANCH_HAVE_DIV2}, +> + {"base_cpu_clk", "cpu_eeprom", CLK_CPU_EEPROM, CCU_BRANCH_HAVE_DIV2}, +> + {"base_cpu_clk", "cpu_wwdt", CLK_CPU_WWDT, 0}, +> + {"base_cpu_clk", "cpu_uart0", CLK_CPU_UART0, 0}, +> + {"base_cpu_clk", "cpu_uart1", CLK_CPU_UART1, 0}, +> + {"base_cpu_clk", "cpu_ssp0", CLK_CPU_SSP0, 0}, +> + {"base_cpu_clk", "cpu_timer0", CLK_CPU_TIMER0, 0}, +> + {"base_cpu_clk", "cpu_timer1", CLK_CPU_TIMER1, 0}, +> + {"base_cpu_clk", "cpu_scu", CLK_CPU_SCU, 0}, +> + {"base_cpu_clk", "cpu_creg", CLK_CPU_CREG, 0}, +> + {"base_cpu_clk", "cpu_ritimer", CLK_CPU_RITIMER, 0}, +> + {"base_cpu_clk", "cpu_uart2", CLK_CPU_UART2, 0}, +> + {"base_cpu_clk", "cpu_uart3", CLK_CPU_UART3, 0}, +> + {"base_cpu_clk", "cpu_timer2", CLK_CPU_TIMER2, 0}, +> + {"base_cpu_clk", "cpu_timer3", CLK_CPU_TIMER3, 0}, +> + {"base_cpu_clk", "cpu_ssp1", CLK_CPU_SSP1, 0}, +> + {"base_cpu_clk", "cpu_qei", CLK_CPU_QEI, 0}, > + -> + {"base_periph_clk", "periph_bus", CLK_PERIPH_BUS, C= -CU_BRANCH_IS_BUS}, -> + {"base_periph_clk", "periph_core", CLK_PERIPH_CORE, 0= -}, -> + {"base_periph_clk", "periph_sgpio", CLK_PERIPH_SGPIO, 0= -}, +> + {"base_periph_clk", "periph_bus", CLK_PERIPH_BUS, CCU_BRANCH_IS_BUS}, +> + {"base_periph_clk", "periph_core", CLK_PERIPH_CORE, 0}, +> + {"base_periph_clk", "periph_sgpio", CLK_PERIPH_SGPIO, 0}, > + -> + {"base_usb0_clk", "usb0", CLK_USB0, 0= -}, -> + {"base_usb1_clk", "usb1", CLK_USB1, 0= -}, -> + {"base_spi_clk", "spi", CLK_SPI, 0= -}, -> + {"base_adchs_clk", "adchs", CLK_ADCHS, 0= -}, +> + {"base_usb0_clk", "usb0", CLK_USB0, 0}, +> + {"base_usb1_clk", "usb1", CLK_USB1, 0}, +> + {"base_spi_clk", "spi", CLK_SPI, 0}, +> + {"base_adchs_clk", "adchs", CLK_ADCHS, 0}, > + -> + {"base_audio_clk", "audio", CLK_AUDIO, 0= -}, -> + {"base_uart3_clk", "apb2_uart3", CLK_APB2_UART3, 0= -}, -> + {"base_uart2_clk", "apb2_uart2", CLK_APB2_UART2, 0= -}, -> + {"base_uart1_clk", "apb0_uart1", CLK_APB0_UART1, 0= -}, -> + {"base_uart0_clk", "apb0_uart0", CLK_APB0_UART0, 0= -}, -> + {"base_ssp1_clk", "apb2_ssp1", CLK_APB2_SSP1, 0= -}, -> + {"base_ssp0_clk", "apb0_ssp0", CLK_APB0_SSP0, 0= -}, -> + {"base_sdio_clk", "sdio", CLK_SDIO, 0= -}, +> + {"base_audio_clk", "audio", CLK_AUDIO, 0}, +> + {"base_uart3_clk", "apb2_uart3", CLK_APB2_UART3, 0}, +> + {"base_uart2_clk", "apb2_uart2", CLK_APB2_UART2, 0}, +> + {"base_uart1_clk", "apb0_uart1", CLK_APB0_UART1, 0}, +> + {"base_uart0_clk", "apb0_uart0", CLK_APB0_UART0, 0}, +> + {"base_ssp1_clk", "apb2_ssp1", CLK_APB2_SSP1, 0}, +> + {"base_ssp0_clk", "apb0_ssp0", CLK_APB0_SSP0, 0}, +> + {"base_sdio_clk", "sdio", CLK_SDIO, 0}, > +}; Hi Joachim, @@ -145,3 +85,7 @@ headers. Regards, Mike +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N2/content_digest index 62e3a56..51c842b 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,144 +1,84 @@ "ref\01432845107-12458-1-git-send-email-manabian@gmail.com\0" "ref\01432845107-12458-4-git-send-email-manabian@gmail.com\0" - "From\0Michael Turquette <mturquette@linaro.org>\0" + "ref\01432845107-12458-4-git-send-email-manabian-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org\0" + "From\0Michael Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>\0" "Subject\0Re: [PATCH v4 3/5] clk: add lpc18xx ccu clk driver\0" "Date\0Tue, 09 Jun 2015 19:13:15 -0700\0" - "To\0Joachim Eastwood <manabian@gmail.com>" - " sboyd@codeaurora.org\0" - "Cc\0Joachim Eastwood <manabian@gmail.com>" - linux-clk@vger.kernel.org - devicetree@vger.kernel.org - " linux-arm-kernel@lists.infradead.org\0" + "To\0sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org\0" + "Cc\0Joachim Eastwood <manabian-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>" + linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0" "\00:1\0" "b\0" "Quoting Joachim Eastwood (2015-05-28 13:31:45)\n" - "> +static struct lpc18xx_clk_branch clk_branches[] =3D {\n" - "> + {\"base_apb3_clk\", \"apb3_bus\", CLK_APB3_BUS, C=\n" - "CU_BRANCH_IS_BUS},\n" - "> + {\"base_apb3_clk\", \"apb3_i2c1\", CLK_APB3_I2C1, 0=\n" - "},\n" - "> + {\"base_apb3_clk\", \"apb3_dac\", CLK_APB3_DAC, 0=\n" - "},\n" - "> + {\"base_apb3_clk\", \"apb3_adc0\", CLK_APB3_ADC0, 0=\n" - "},\n" - "> + {\"base_apb3_clk\", \"apb3_adc1\", CLK_APB3_ADC1, 0=\n" - "},\n" - "> + {\"base_apb3_clk\", \"apb3_can0\", CLK_APB3_CAN0, 0=\n" - "},\n" + "> +static struct lpc18xx_clk_branch clk_branches[] = {\n" + "> + {\"base_apb3_clk\", \"apb3_bus\", CLK_APB3_BUS, CCU_BRANCH_IS_BUS},\n" + "> + {\"base_apb3_clk\", \"apb3_i2c1\", CLK_APB3_I2C1, 0},\n" + "> + {\"base_apb3_clk\", \"apb3_dac\", CLK_APB3_DAC, 0},\n" + "> + {\"base_apb3_clk\", \"apb3_adc0\", CLK_APB3_ADC0, 0},\n" + "> + {\"base_apb3_clk\", \"apb3_adc1\", CLK_APB3_ADC1, 0},\n" + "> + {\"base_apb3_clk\", \"apb3_can0\", CLK_APB3_CAN0, 0},\n" "> +\n" - "> + {\"base_apb1_clk\", \"apb1_bus\", CLK_APB1_BUS, C=\n" - "CU_BRANCH_IS_BUS},\n" - "> + {\"base_apb1_clk\", \"apb1_mc_pwm\", CLK_APB1_MOTOCON_PWM, 0=\n" - "},\n" - "> + {\"base_apb1_clk\", \"apb1_i2c0\", CLK_APB1_I2C0, 0=\n" - "},\n" - "> + {\"base_apb1_clk\", \"apb1_i2s\", CLK_APB1_I2S, 0=\n" - "},\n" - "> + {\"base_apb1_clk\", \"apb1_can1\", CLK_APB1_CAN1, 0=\n" - "},\n" + "> + {\"base_apb1_clk\", \"apb1_bus\", CLK_APB1_BUS, CCU_BRANCH_IS_BUS},\n" + "> + {\"base_apb1_clk\", \"apb1_mc_pwm\", CLK_APB1_MOTOCON_PWM, 0},\n" + "> + {\"base_apb1_clk\", \"apb1_i2c0\", CLK_APB1_I2C0, 0},\n" + "> + {\"base_apb1_clk\", \"apb1_i2s\", CLK_APB1_I2S, 0},\n" + "> + {\"base_apb1_clk\", \"apb1_can1\", CLK_APB1_CAN1, 0},\n" "> +\n" - "> + {\"base_spifi_clk\", \"spifi\", CLK_SPIFI, 0=\n" - "},\n" + "> + {\"base_spifi_clk\", \"spifi\", CLK_SPIFI, 0},\n" "> +\n" - "> + {\"base_cpu_clk\", \"cpu_bus\", CLK_CPU_BUS, C=\n" - "CU_BRANCH_IS_BUS},\n" - "> + {\"base_cpu_clk\", \"cpu_spifi\", CLK_CPU_SPIFI, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_gpio\", CLK_CPU_GPIO, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_lcd\", CLK_CPU_LCD, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_ethernet\", CLK_CPU_ETHERNET, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_usb0\", CLK_CPU_USB0, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_emc\", CLK_CPU_EMC, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_sdio\", CLK_CPU_SDIO, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_dma\", CLK_CPU_DMA, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_core\", CLK_CPU_CORE, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_sct\", CLK_CPU_SCT, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_usb1\", CLK_CPU_USB1, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_emcdiv\", CLK_CPU_EMCDIV, C=\n" - "CU_BRANCH_HAVE_DIV2},\n" - "> + {\"base_cpu_clk\", \"cpu_flasha\", CLK_CPU_FLASHA, C=\n" - "CU_BRANCH_HAVE_DIV2},\n" - "> + {\"base_cpu_clk\", \"cpu_flashb\", CLK_CPU_FLASHB, C=\n" - "CU_BRANCH_HAVE_DIV2},\n" - "> + {\"base_cpu_clk\", \"cpu_m0app\", CLK_CPU_M0APP, C=\n" - "CU_BRANCH_HAVE_DIV2},\n" - "> + {\"base_cpu_clk\", \"cpu_adchs\", CLK_CPU_ADCHS, C=\n" - "CU_BRANCH_HAVE_DIV2},\n" - "> + {\"base_cpu_clk\", \"cpu_eeprom\", CLK_CPU_EEPROM, C=\n" - "CU_BRANCH_HAVE_DIV2},\n" - "> + {\"base_cpu_clk\", \"cpu_wwdt\", CLK_CPU_WWDT, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_uart0\", CLK_CPU_UART0, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_uart1\", CLK_CPU_UART1, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_ssp0\", CLK_CPU_SSP0, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_timer0\", CLK_CPU_TIMER0, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_timer1\", CLK_CPU_TIMER1, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_scu\", CLK_CPU_SCU, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_creg\", CLK_CPU_CREG, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_ritimer\", CLK_CPU_RITIMER, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_uart2\", CLK_CPU_UART2, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_uart3\", CLK_CPU_UART3, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_timer2\", CLK_CPU_TIMER2, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_timer3\", CLK_CPU_TIMER3, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_ssp1\", CLK_CPU_SSP1, 0=\n" - "},\n" - "> + {\"base_cpu_clk\", \"cpu_qei\", CLK_CPU_QEI, 0=\n" - "},\n" + "> + {\"base_cpu_clk\", \"cpu_bus\", CLK_CPU_BUS, CCU_BRANCH_IS_BUS},\n" + "> + {\"base_cpu_clk\", \"cpu_spifi\", CLK_CPU_SPIFI, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_gpio\", CLK_CPU_GPIO, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_lcd\", CLK_CPU_LCD, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_ethernet\", CLK_CPU_ETHERNET, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_usb0\", CLK_CPU_USB0, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_emc\", CLK_CPU_EMC, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_sdio\", CLK_CPU_SDIO, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_dma\", CLK_CPU_DMA, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_core\", CLK_CPU_CORE, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_sct\", CLK_CPU_SCT, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_usb1\", CLK_CPU_USB1, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_emcdiv\", CLK_CPU_EMCDIV, CCU_BRANCH_HAVE_DIV2},\n" + "> + {\"base_cpu_clk\", \"cpu_flasha\", CLK_CPU_FLASHA, CCU_BRANCH_HAVE_DIV2},\n" + "> + {\"base_cpu_clk\", \"cpu_flashb\", CLK_CPU_FLASHB, CCU_BRANCH_HAVE_DIV2},\n" + "> + {\"base_cpu_clk\", \"cpu_m0app\", CLK_CPU_M0APP, CCU_BRANCH_HAVE_DIV2},\n" + "> + {\"base_cpu_clk\", \"cpu_adchs\", CLK_CPU_ADCHS, CCU_BRANCH_HAVE_DIV2},\n" + "> + {\"base_cpu_clk\", \"cpu_eeprom\", CLK_CPU_EEPROM, CCU_BRANCH_HAVE_DIV2},\n" + "> + {\"base_cpu_clk\", \"cpu_wwdt\", CLK_CPU_WWDT, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_uart0\", CLK_CPU_UART0, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_uart1\", CLK_CPU_UART1, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_ssp0\", CLK_CPU_SSP0, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_timer0\", CLK_CPU_TIMER0, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_timer1\", CLK_CPU_TIMER1, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_scu\", CLK_CPU_SCU, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_creg\", CLK_CPU_CREG, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_ritimer\", CLK_CPU_RITIMER, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_uart2\", CLK_CPU_UART2, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_uart3\", CLK_CPU_UART3, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_timer2\", CLK_CPU_TIMER2, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_timer3\", CLK_CPU_TIMER3, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_ssp1\", CLK_CPU_SSP1, 0},\n" + "> + {\"base_cpu_clk\", \"cpu_qei\", CLK_CPU_QEI, 0},\n" "> +\n" - "> + {\"base_periph_clk\", \"periph_bus\", CLK_PERIPH_BUS, C=\n" - "CU_BRANCH_IS_BUS},\n" - "> + {\"base_periph_clk\", \"periph_core\", CLK_PERIPH_CORE, 0=\n" - "},\n" - "> + {\"base_periph_clk\", \"periph_sgpio\", CLK_PERIPH_SGPIO, 0=\n" - "},\n" + "> + {\"base_periph_clk\", \"periph_bus\", CLK_PERIPH_BUS, CCU_BRANCH_IS_BUS},\n" + "> + {\"base_periph_clk\", \"periph_core\", CLK_PERIPH_CORE, 0},\n" + "> + {\"base_periph_clk\", \"periph_sgpio\", CLK_PERIPH_SGPIO, 0},\n" "> +\n" - "> + {\"base_usb0_clk\", \"usb0\", CLK_USB0, 0=\n" - "},\n" - "> + {\"base_usb1_clk\", \"usb1\", CLK_USB1, 0=\n" - "},\n" - "> + {\"base_spi_clk\", \"spi\", CLK_SPI, 0=\n" - "},\n" - "> + {\"base_adchs_clk\", \"adchs\", CLK_ADCHS, 0=\n" - "},\n" + "> + {\"base_usb0_clk\", \"usb0\", CLK_USB0, 0},\n" + "> + {\"base_usb1_clk\", \"usb1\", CLK_USB1, 0},\n" + "> + {\"base_spi_clk\", \"spi\", CLK_SPI, 0},\n" + "> + {\"base_adchs_clk\", \"adchs\", CLK_ADCHS, 0},\n" "> +\n" - "> + {\"base_audio_clk\", \"audio\", CLK_AUDIO, 0=\n" - "},\n" - "> + {\"base_uart3_clk\", \"apb2_uart3\", CLK_APB2_UART3, 0=\n" - "},\n" - "> + {\"base_uart2_clk\", \"apb2_uart2\", CLK_APB2_UART2, 0=\n" - "},\n" - "> + {\"base_uart1_clk\", \"apb0_uart1\", CLK_APB0_UART1, 0=\n" - "},\n" - "> + {\"base_uart0_clk\", \"apb0_uart0\", CLK_APB0_UART0, 0=\n" - "},\n" - "> + {\"base_ssp1_clk\", \"apb2_ssp1\", CLK_APB2_SSP1, 0=\n" - "},\n" - "> + {\"base_ssp0_clk\", \"apb0_ssp0\", CLK_APB0_SSP0, 0=\n" - "},\n" - "> + {\"base_sdio_clk\", \"sdio\", CLK_SDIO, 0=\n" - "},\n" + "> + {\"base_audio_clk\", \"audio\", CLK_AUDIO, 0},\n" + "> + {\"base_uart3_clk\", \"apb2_uart3\", CLK_APB2_UART3, 0},\n" + "> + {\"base_uart2_clk\", \"apb2_uart2\", CLK_APB2_UART2, 0},\n" + "> + {\"base_uart1_clk\", \"apb0_uart1\", CLK_APB0_UART1, 0},\n" + "> + {\"base_uart0_clk\", \"apb0_uart0\", CLK_APB0_UART0, 0},\n" + "> + {\"base_ssp1_clk\", \"apb2_ssp1\", CLK_APB2_SSP1, 0},\n" + "> + {\"base_ssp0_clk\", \"apb0_ssp0\", CLK_APB0_SSP0, 0},\n" + "> + {\"base_sdio_clk\", \"sdio\", CLK_SDIO, 0},\n" "> +};\n" "\n" "Hi Joachim,\n" @@ -157,6 +97,10 @@ "headers.\n" "\n" "Regards,\n" - Mike + "Mike\n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -23322abd7835f64b233a1e7db250e7f65c97a8f6305a053c34b8002f5557ab98 +b351711108344b05b467d82634a686e38e2898d442a939f5c58fae04b764dabc
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