Re: [Qemu-devel] [PATCH v4 2/6] target-arm: Add CNTHCTL_EL2

["Edgar E. Iglesias" <edgar.iglesias@xilinx.com>]

On Fri, Jun 12, 2015 at 05:51:55PM +0100, Peter Maydell wrote:
> On 5 June 2015 at 11:33, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote:
> > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> >
> > Adds control for trapping selected timer and counter accesses to EL2.
> >
> > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> > ---
> >  target-arm/cpu.h    |  1 +
> >  target-arm/helper.c | 30 ++++++++++++++++++++++++++++--
> >  2 files changed, 29 insertions(+), 2 deletions(-)
> >
> > diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> > index 1a66aa4..f39c32b 100644
> > --- a/target-arm/cpu.h
> > +++ b/target-arm/cpu.h
> > @@ -355,6 +355,7 @@ typedef struct CPUARMState {
> >          };
> >          uint64_t c14_cntfrq; /* Counter Frequency register */
> >          uint64_t c14_cntkctl; /* Timer Control register */
> > +        uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */
> >          uint64_t cntvoff_el2; /* Counter Virtual Offset register */
> >          ARMGenericTimer c14_timer[NUM_GTIMERS];
> >          uint32_t c15_cpar; /* XScale Coprocessor Access Register */
> > diff --git a/target-arm/helper.c b/target-arm/helper.c
> > index 7901da1..1795e5f 100644
> > --- a/target-arm/helper.c
> > +++ b/target-arm/helper.c
> > @@ -1153,8 +1153,17 @@ static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri)
> >
> >  static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx)
> >  {
> > +    unsigned int cur_el = arm_current_el(env);
> > +    bool secure = arm_is_secure(env);
> > +
> > +    if (arm_feature(env, ARM_FEATURE_EL2) &&
> > +        timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
> > +        !extract32(env->cp15.cnthctl_el2, 0, 1)) {
> > +        return CP_ACCESS_TRAP_EL2;
> > +    }
> 
> The CNTKCTL controls take precedence over the CNTHCTL ones, so
> this check needs to go below the existing one.
> 
> > +
> >      /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
> > -    if (arm_current_el(env) == 0 &&
> > +    if (cur_el == 0 &&
> >          !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
> >          return CP_ACCESS_TRAP;
> >      }
> > @@ -1163,10 +1172,20 @@ static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx)
> >
> >  static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx)
> >  {
> > +    unsigned int cur_el = arm_current_el(env);
> > +    bool secure = arm_is_secure(env);
> > +
> > +    if (arm_feature(env, ARM_FEATURE_EL2)) {
> > +        if (timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
> > +            !extract32(env->cp15.cnthctl_el2, 1, 1)) {
> > +            return CP_ACCESS_TRAP_EL2;
> > +        }
> > +    }
> 
> Wrong order again.

Fixed both.

> 
> > +
> >      /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
> >       * EL0[PV]TEN is zero.
> >       */
> > -    if (arm_current_el(env) == 0 &&
> > +    if (cur_el == 0 &&
> >          !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
> >          return CP_ACCESS_TRAP;
> >      }
> > @@ -2566,6 +2585,9 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
> >      { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
> >        .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
> >        .resetvalue = 0 },
> > +    { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
> > +      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
> > +      .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
> >      { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
> >        .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
> >        .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
> > @@ -2685,6 +2707,10 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
> >        .type = ARM_CP_NO_RAW, .access = PL2_W,
> >        .writefn = tlbi_aa64_vaa_write },
> >  #ifndef CONFIG_USER_ONLY
> > +    { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
> > +      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
> > +      .access = PL2_RW, .resetvalue = 3,
> 
> Why 3? The ARM ARM says the resetvalue is IMPDEF and might
> be UNKNOWN.

Hi, I sohuld added a comment about this. The ARMv7 manual says that
bit 0 and 1 reset to 1. ARMv8 has these as IMPDEF so I figured
3 would be OK in both cases.

Does that sound OK?

Cheers,
Edgar




> 
> > +      .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) },
> >      { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
> >        .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
> >        .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0,
> > --
> > 1.9.1
> >
> 
> thanks
> -- PMM