diff for duplicates of <20150618223728.9112.75331@quantum> diff --git a/a/1.txt b/N1/1.txt index fda3d98..585d831 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -2,8 +2,7 @@ Quoting Murali Karicheri (2015-05-29 09:04:12) > Main PLL controller has post divider bits in a separate register in > pll controller. Use the value from this register instead of fixed > divider when available. -> = - +> > Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Applied to clk-next. @@ -13,44 +12,35 @@ Mike > --- > .../devicetree/bindings/clock/keystone-pll.txt | 8 ++++---- -> drivers/clk/keystone/pll.c | 20 ++++++++++++++= -++++-- +> drivers/clk/keystone/pll.c | 20 ++++++++++++++++++-- > 2 files changed, 22 insertions(+), 6 deletions(-) -> = - -> diff --git a/Documentation/devicetree/bindings/clock/keystone-pll.txt b/D= -ocumentation/devicetree/bindings/clock/keystone-pll.txt +> +> diff --git a/Documentation/devicetree/bindings/clock/keystone-pll.txt b/Documentation/devicetree/bindings/clock/keystone-pll.txt > index 225990f..47570d2 100644 > --- a/Documentation/devicetree/bindings/clock/keystone-pll.txt > +++ b/Documentation/devicetree/bindings/clock/keystone-pll.txt > @@ -15,8 +15,8 @@ Required properties: -> - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll= --clock" +> - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock" > - clocks : parent clock phandle > - reg - pll control0 and pll multipler registers -> -- reg-names : control and multiplier. The multiplier is applicable only = -for +> -- reg-names : control and multiplier. The multiplier is applicable only for > - main pll clock > +- reg-names : control, multiplier and post-divider. The multiplier and -> + post-divider registers are applicable only for main pll c= -lock -> - fixed-postdiv : fixed post divider value. If absent, use clkod registe= -r bits +> + post-divider registers are applicable only for main pll clock +> - fixed-postdiv : fixed post divider value. If absent, use clkod register bits > for postdiv -> = - +> > @@ -25,8 +25,8 @@ Example: -> #clock-cells =3D <0>; -> compatible =3D "ti,keystone,main-pll-clock"; -> clocks =3D <&refclksys>; -> - reg =3D <0x02620350 4>, <0x02310110 4>; -> - reg-names =3D "control", "multiplier"; -> + reg =3D <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; -> + reg-names =3D "control", "multiplier", "post-divider"; -> fixed-postdiv =3D <2>; +> #clock-cells = <0>; +> compatible = "ti,keystone,main-pll-clock"; +> clocks = <&refclksys>; +> - reg = <0x02620350 4>, <0x02310110 4>; +> - reg-names = "control", "multiplier"; +> + reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; +> + reg-names = "control", "multiplier", "post-divider"; +> fixed-postdiv = <2>; > }; -> = - +> > diff --git a/drivers/clk/keystone/pll.c b/drivers/clk/keystone/pll.c > index 0dd8a4b..4a375ea 100644 > --- a/drivers/clk/keystone/pll.c @@ -73,56 +63,49 @@ r bits > void __iomem *pll_ctl0; > u32 pllm_lower_mask; > u32 pllm_upper_mask; -> @@ -102,7 +104,11 @@ static unsigned long clk_pllclk_recalc(struct clk_hw= - *hw, +> @@ -102,7 +104,11 @@ static unsigned long clk_pllclk_recalc(struct clk_hw *hw, > /* read post divider from od bits*/ -> postdiv =3D ((val & pll_data->clkod_mask) >> +> postdiv = ((val & pll_data->clkod_mask) >> > pll_data->clkod_shift) + 1; > - else > + else if (pll_data->pllod) { -> + postdiv =3D readl(pll_data->pllod); -> + postdiv =3D ((postdiv & pll_data->clkod_mask) >> +> + postdiv = readl(pll_data->pllod); +> + postdiv = ((postdiv & pll_data->clkod_mask) >> > + pll_data->clkod_shift) + 1; > + } else -> postdiv =3D pll_data->postdiv; -> = - -> rate /=3D (prediv + 1); -> @@ -172,12 +178,21 @@ static void __init _of_pll_clk_init(struct device_n= -ode *node, bool pllctrl) +> postdiv = pll_data->postdiv; +> +> rate /= (prediv + 1); +> @@ -172,12 +178,21 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl) > /* assume the PLL has output divider register bits */ -> pll_data->clkod_mask =3D CLKOD_MASK; -> pll_data->clkod_shift =3D CLKOD_SHIFT; +> pll_data->clkod_mask = CLKOD_MASK; +> pll_data->clkod_shift = CLKOD_SHIFT; > + > + /* > + * Check if there is an post-divider register. If not > + * assume od bits are part of control register. > + */ -> + i =3D of_property_match_string(node, "reg-names", +> + i = of_property_match_string(node, "reg-names", > + "post-divider"); -> + pll_data->pllod =3D of_iomap(node, i); +> + pll_data->pllod = of_iomap(node, i); > } -> = - -> i =3D of_property_match_string(node, "reg-names", "control"); -> pll_data->pll_ctl0 =3D of_iomap(node, i); +> +> i = of_property_match_string(node, "reg-names", "control"); +> pll_data->pll_ctl0 = of_iomap(node, i); > if (!pll_data->pll_ctl0) { > pr_err("%s: ioremap failed\n", __func__); > + iounmap(pll_data->pllod); > goto out; > } -> = - -> @@ -193,6 +208,7 @@ static void __init _of_pll_clk_init(struct device_nod= -e *node, bool pllctrl) -> pll_data->pllm =3D of_iomap(node, i); +> +> @@ -193,6 +208,7 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl) +> pll_data->pllm = of_iomap(node, i); > if (!pll_data->pllm) { > iounmap(pll_data->pll_ctl0); > + iounmap(pll_data->pllod); > goto out; > } > } -> -- = - +> -- > 1.9.1 ->=20 +> diff --git a/a/content_digest b/N1/content_digest index 7113330..05164e2 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,29 +1,15 @@ "ref\01432915453-409-1-git-send-email-m-karicheri2@ti.com\0" - "From\0Michael Turquette <mturquette@linaro.org>\0" - "Subject\0Re: [PATCH 1/2] clk: keystone: add support for post divider register for main pll\0" + "From\0mturquette@linaro.org (Michael Turquette)\0" + "Subject\0[PATCH 1/2] clk: keystone: add support for post divider register for main pll\0" "Date\0Thu, 18 Jun 2015 15:37:28 -0700\0" - "To\0Murali Karicheri <m-karicheri2@ti.com>" - robh+dt@kernel.org - pawel.moll@arm.com - mark.rutland@arm.com - ijc+devicetree@hellion.org.uk - galak@codeaurora.org - ssantosh@kernel.org - sboyd@codeaurora.org - devicetree@vger.kernel.org - linux-kernel@vger.kernel.org - linux-clk@vger.kernel.org - linux@arm.linux.org.uk - " linux-arm-kernel@lists.infradead.org\0" - "Cc\0Murali Karicheri <m-karicheri2@ti.com>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Quoting Murali Karicheri (2015-05-29 09:04:12)\n" "> Main PLL controller has post divider bits in a separate register in\n" "> pll controller. Use the value from this register instead of fixed\n" "> divider when available.\n" - "> =\n" - "\n" + "> \n" "> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>\n" "\n" "Applied to clk-next.\n" @@ -33,44 +19,35 @@ "\n" "> ---\n" "> .../devicetree/bindings/clock/keystone-pll.txt | 8 ++++----\n" - "> drivers/clk/keystone/pll.c | 20 ++++++++++++++=\n" - "++++--\n" + "> drivers/clk/keystone/pll.c | 20 ++++++++++++++++++--\n" "> 2 files changed, 22 insertions(+), 6 deletions(-)\n" - "> =\n" - "\n" - "> diff --git a/Documentation/devicetree/bindings/clock/keystone-pll.txt b/D=\n" - "ocumentation/devicetree/bindings/clock/keystone-pll.txt\n" + "> \n" + "> diff --git a/Documentation/devicetree/bindings/clock/keystone-pll.txt b/Documentation/devicetree/bindings/clock/keystone-pll.txt\n" "> index 225990f..47570d2 100644\n" "> --- a/Documentation/devicetree/bindings/clock/keystone-pll.txt\n" "> +++ b/Documentation/devicetree/bindings/clock/keystone-pll.txt\n" "> @@ -15,8 +15,8 @@ Required properties:\n" - "> - compatible : shall be \"ti,keystone,main-pll-clock\" or \"ti,keystone,pll=\n" - "-clock\"\n" + "> - compatible : shall be \"ti,keystone,main-pll-clock\" or \"ti,keystone,pll-clock\"\n" "> - clocks : parent clock phandle\n" "> - reg - pll control0 and pll multipler registers\n" - "> -- reg-names : control and multiplier. The multiplier is applicable only =\n" - "for\n" + "> -- reg-names : control and multiplier. The multiplier is applicable only for\n" "> - main pll clock\n" "> +- reg-names : control, multiplier and post-divider. The multiplier and\n" - "> + post-divider registers are applicable only for main pll c=\n" - "lock\n" - "> - fixed-postdiv : fixed post divider value. If absent, use clkod registe=\n" - "r bits\n" + "> + post-divider registers are applicable only for main pll clock\n" + "> - fixed-postdiv : fixed post divider value. If absent, use clkod register bits\n" "> for postdiv\n" - "> =\n" - "\n" + "> \n" "> @@ -25,8 +25,8 @@ Example:\n" - "> #clock-cells =3D <0>;\n" - "> compatible =3D \"ti,keystone,main-pll-clock\";\n" - "> clocks =3D <&refclksys>;\n" - "> - reg =3D <0x02620350 4>, <0x02310110 4>;\n" - "> - reg-names =3D \"control\", \"multiplier\";\n" - "> + reg =3D <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;\n" - "> + reg-names =3D \"control\", \"multiplier\", \"post-divider\";\n" - "> fixed-postdiv =3D <2>;\n" + "> #clock-cells = <0>;\n" + "> compatible = \"ti,keystone,main-pll-clock\";\n" + "> clocks = <&refclksys>;\n" + "> - reg = <0x02620350 4>, <0x02310110 4>;\n" + "> - reg-names = \"control\", \"multiplier\";\n" + "> + reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;\n" + "> + reg-names = \"control\", \"multiplier\", \"post-divider\";\n" + "> fixed-postdiv = <2>;\n" "> };\n" - "> =\n" - "\n" + "> \n" "> diff --git a/drivers/clk/keystone/pll.c b/drivers/clk/keystone/pll.c\n" "> index 0dd8a4b..4a375ea 100644\n" "> --- a/drivers/clk/keystone/pll.c\n" @@ -93,58 +70,51 @@ "> void __iomem *pll_ctl0;\n" "> u32 pllm_lower_mask;\n" "> u32 pllm_upper_mask;\n" - "> @@ -102,7 +104,11 @@ static unsigned long clk_pllclk_recalc(struct clk_hw=\n" - " *hw,\n" + "> @@ -102,7 +104,11 @@ static unsigned long clk_pllclk_recalc(struct clk_hw *hw,\n" "> /* read post divider from od bits*/\n" - "> postdiv =3D ((val & pll_data->clkod_mask) >>\n" + "> postdiv = ((val & pll_data->clkod_mask) >>\n" "> pll_data->clkod_shift) + 1;\n" "> - else\n" "> + else if (pll_data->pllod) {\n" - "> + postdiv =3D readl(pll_data->pllod);\n" - "> + postdiv =3D ((postdiv & pll_data->clkod_mask) >>\n" + "> + postdiv = readl(pll_data->pllod);\n" + "> + postdiv = ((postdiv & pll_data->clkod_mask) >>\n" "> + pll_data->clkod_shift) + 1;\n" "> + } else\n" - "> postdiv =3D pll_data->postdiv;\n" - "> =\n" - "\n" - "> rate /=3D (prediv + 1);\n" - "> @@ -172,12 +178,21 @@ static void __init _of_pll_clk_init(struct device_n=\n" - "ode *node, bool pllctrl)\n" + "> postdiv = pll_data->postdiv;\n" + "> \n" + "> rate /= (prediv + 1);\n" + "> @@ -172,12 +178,21 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl)\n" "> /* assume the PLL has output divider register bits */\n" - "> pll_data->clkod_mask =3D CLKOD_MASK;\n" - "> pll_data->clkod_shift =3D CLKOD_SHIFT;\n" + "> pll_data->clkod_mask = CLKOD_MASK;\n" + "> pll_data->clkod_shift = CLKOD_SHIFT;\n" "> +\n" "> + /*\n" "> + * Check if there is an post-divider register. If not\n" "> + * assume od bits are part of control register.\n" "> + */\n" - "> + i =3D of_property_match_string(node, \"reg-names\",\n" + "> + i = of_property_match_string(node, \"reg-names\",\n" "> + \"post-divider\");\n" - "> + pll_data->pllod =3D of_iomap(node, i);\n" + "> + pll_data->pllod = of_iomap(node, i);\n" "> }\n" - "> =\n" - "\n" - "> i =3D of_property_match_string(node, \"reg-names\", \"control\");\n" - "> pll_data->pll_ctl0 =3D of_iomap(node, i);\n" + "> \n" + "> i = of_property_match_string(node, \"reg-names\", \"control\");\n" + "> pll_data->pll_ctl0 = of_iomap(node, i);\n" "> if (!pll_data->pll_ctl0) {\n" "> pr_err(\"%s: ioremap failed\\n\", __func__);\n" "> + iounmap(pll_data->pllod);\n" "> goto out;\n" "> }\n" - "> =\n" - "\n" - "> @@ -193,6 +208,7 @@ static void __init _of_pll_clk_init(struct device_nod=\n" - "e *node, bool pllctrl)\n" - "> pll_data->pllm =3D of_iomap(node, i);\n" + "> \n" + "> @@ -193,6 +208,7 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl)\n" + "> pll_data->pllm = of_iomap(node, i);\n" "> if (!pll_data->pllm) {\n" "> iounmap(pll_data->pll_ctl0);\n" "> + iounmap(pll_data->pllod);\n" "> goto out;\n" "> }\n" "> }\n" - "> -- =\n" - "\n" + "> -- \n" "> 1.9.1\n" - >=20 + > -490d67df368bdee9595c7e589d7d3b552f683e9856f5d889c08f965591c95c27 +2690c384293bd3eb20817eb4286b2b8f622d47fbed6615706777a912a6e31499
diff --git a/a/1.txt b/N2/1.txt index fda3d98..585d831 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -2,8 +2,7 @@ Quoting Murali Karicheri (2015-05-29 09:04:12) > Main PLL controller has post divider bits in a separate register in > pll controller. Use the value from this register instead of fixed > divider when available. -> = - +> > Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Applied to clk-next. @@ -13,44 +12,35 @@ Mike > --- > .../devicetree/bindings/clock/keystone-pll.txt | 8 ++++---- -> drivers/clk/keystone/pll.c | 20 ++++++++++++++= -++++-- +> drivers/clk/keystone/pll.c | 20 ++++++++++++++++++-- > 2 files changed, 22 insertions(+), 6 deletions(-) -> = - -> diff --git a/Documentation/devicetree/bindings/clock/keystone-pll.txt b/D= -ocumentation/devicetree/bindings/clock/keystone-pll.txt +> +> diff --git a/Documentation/devicetree/bindings/clock/keystone-pll.txt b/Documentation/devicetree/bindings/clock/keystone-pll.txt > index 225990f..47570d2 100644 > --- a/Documentation/devicetree/bindings/clock/keystone-pll.txt > +++ b/Documentation/devicetree/bindings/clock/keystone-pll.txt > @@ -15,8 +15,8 @@ Required properties: -> - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll= --clock" +> - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock" > - clocks : parent clock phandle > - reg - pll control0 and pll multipler registers -> -- reg-names : control and multiplier. The multiplier is applicable only = -for +> -- reg-names : control and multiplier. The multiplier is applicable only for > - main pll clock > +- reg-names : control, multiplier and post-divider. The multiplier and -> + post-divider registers are applicable only for main pll c= -lock -> - fixed-postdiv : fixed post divider value. If absent, use clkod registe= -r bits +> + post-divider registers are applicable only for main pll clock +> - fixed-postdiv : fixed post divider value. If absent, use clkod register bits > for postdiv -> = - +> > @@ -25,8 +25,8 @@ Example: -> #clock-cells =3D <0>; -> compatible =3D "ti,keystone,main-pll-clock"; -> clocks =3D <&refclksys>; -> - reg =3D <0x02620350 4>, <0x02310110 4>; -> - reg-names =3D "control", "multiplier"; -> + reg =3D <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; -> + reg-names =3D "control", "multiplier", "post-divider"; -> fixed-postdiv =3D <2>; +> #clock-cells = <0>; +> compatible = "ti,keystone,main-pll-clock"; +> clocks = <&refclksys>; +> - reg = <0x02620350 4>, <0x02310110 4>; +> - reg-names = "control", "multiplier"; +> + reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; +> + reg-names = "control", "multiplier", "post-divider"; +> fixed-postdiv = <2>; > }; -> = - +> > diff --git a/drivers/clk/keystone/pll.c b/drivers/clk/keystone/pll.c > index 0dd8a4b..4a375ea 100644 > --- a/drivers/clk/keystone/pll.c @@ -73,56 +63,49 @@ r bits > void __iomem *pll_ctl0; > u32 pllm_lower_mask; > u32 pllm_upper_mask; -> @@ -102,7 +104,11 @@ static unsigned long clk_pllclk_recalc(struct clk_hw= - *hw, +> @@ -102,7 +104,11 @@ static unsigned long clk_pllclk_recalc(struct clk_hw *hw, > /* read post divider from od bits*/ -> postdiv =3D ((val & pll_data->clkod_mask) >> +> postdiv = ((val & pll_data->clkod_mask) >> > pll_data->clkod_shift) + 1; > - else > + else if (pll_data->pllod) { -> + postdiv =3D readl(pll_data->pllod); -> + postdiv =3D ((postdiv & pll_data->clkod_mask) >> +> + postdiv = readl(pll_data->pllod); +> + postdiv = ((postdiv & pll_data->clkod_mask) >> > + pll_data->clkod_shift) + 1; > + } else -> postdiv =3D pll_data->postdiv; -> = - -> rate /=3D (prediv + 1); -> @@ -172,12 +178,21 @@ static void __init _of_pll_clk_init(struct device_n= -ode *node, bool pllctrl) +> postdiv = pll_data->postdiv; +> +> rate /= (prediv + 1); +> @@ -172,12 +178,21 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl) > /* assume the PLL has output divider register bits */ -> pll_data->clkod_mask =3D CLKOD_MASK; -> pll_data->clkod_shift =3D CLKOD_SHIFT; +> pll_data->clkod_mask = CLKOD_MASK; +> pll_data->clkod_shift = CLKOD_SHIFT; > + > + /* > + * Check if there is an post-divider register. If not > + * assume od bits are part of control register. > + */ -> + i =3D of_property_match_string(node, "reg-names", +> + i = of_property_match_string(node, "reg-names", > + "post-divider"); -> + pll_data->pllod =3D of_iomap(node, i); +> + pll_data->pllod = of_iomap(node, i); > } -> = - -> i =3D of_property_match_string(node, "reg-names", "control"); -> pll_data->pll_ctl0 =3D of_iomap(node, i); +> +> i = of_property_match_string(node, "reg-names", "control"); +> pll_data->pll_ctl0 = of_iomap(node, i); > if (!pll_data->pll_ctl0) { > pr_err("%s: ioremap failed\n", __func__); > + iounmap(pll_data->pllod); > goto out; > } -> = - -> @@ -193,6 +208,7 @@ static void __init _of_pll_clk_init(struct device_nod= -e *node, bool pllctrl) -> pll_data->pllm =3D of_iomap(node, i); +> +> @@ -193,6 +208,7 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl) +> pll_data->pllm = of_iomap(node, i); > if (!pll_data->pllm) { > iounmap(pll_data->pll_ctl0); > + iounmap(pll_data->pllod); > goto out; > } > } -> -- = - +> -- > 1.9.1 ->=20 +> diff --git a/a/content_digest b/N2/content_digest index 7113330..f5d4312 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -2,8 +2,7 @@ "From\0Michael Turquette <mturquette@linaro.org>\0" "Subject\0Re: [PATCH 1/2] clk: keystone: add support for post divider register for main pll\0" "Date\0Thu, 18 Jun 2015 15:37:28 -0700\0" - "To\0Murali Karicheri <m-karicheri2@ti.com>" - robh+dt@kernel.org + "To\0robh+dt@kernel.org" pawel.moll@arm.com mark.rutland@arm.com ijc+devicetree@hellion.org.uk @@ -22,8 +21,7 @@ "> Main PLL controller has post divider bits in a separate register in\n" "> pll controller. Use the value from this register instead of fixed\n" "> divider when available.\n" - "> =\n" - "\n" + "> \n" "> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>\n" "\n" "Applied to clk-next.\n" @@ -33,44 +31,35 @@ "\n" "> ---\n" "> .../devicetree/bindings/clock/keystone-pll.txt | 8 ++++----\n" - "> drivers/clk/keystone/pll.c | 20 ++++++++++++++=\n" - "++++--\n" + "> drivers/clk/keystone/pll.c | 20 ++++++++++++++++++--\n" "> 2 files changed, 22 insertions(+), 6 deletions(-)\n" - "> =\n" - "\n" - "> diff --git a/Documentation/devicetree/bindings/clock/keystone-pll.txt b/D=\n" - "ocumentation/devicetree/bindings/clock/keystone-pll.txt\n" + "> \n" + "> diff --git a/Documentation/devicetree/bindings/clock/keystone-pll.txt b/Documentation/devicetree/bindings/clock/keystone-pll.txt\n" "> index 225990f..47570d2 100644\n" "> --- a/Documentation/devicetree/bindings/clock/keystone-pll.txt\n" "> +++ b/Documentation/devicetree/bindings/clock/keystone-pll.txt\n" "> @@ -15,8 +15,8 @@ Required properties:\n" - "> - compatible : shall be \"ti,keystone,main-pll-clock\" or \"ti,keystone,pll=\n" - "-clock\"\n" + "> - compatible : shall be \"ti,keystone,main-pll-clock\" or \"ti,keystone,pll-clock\"\n" "> - clocks : parent clock phandle\n" "> - reg - pll control0 and pll multipler registers\n" - "> -- reg-names : control and multiplier. The multiplier is applicable only =\n" - "for\n" + "> -- reg-names : control and multiplier. The multiplier is applicable only for\n" "> - main pll clock\n" "> +- reg-names : control, multiplier and post-divider. The multiplier and\n" - "> + post-divider registers are applicable only for main pll c=\n" - "lock\n" - "> - fixed-postdiv : fixed post divider value. If absent, use clkod registe=\n" - "r bits\n" + "> + post-divider registers are applicable only for main pll clock\n" + "> - fixed-postdiv : fixed post divider value. If absent, use clkod register bits\n" "> for postdiv\n" - "> =\n" - "\n" + "> \n" "> @@ -25,8 +25,8 @@ Example:\n" - "> #clock-cells =3D <0>;\n" - "> compatible =3D \"ti,keystone,main-pll-clock\";\n" - "> clocks =3D <&refclksys>;\n" - "> - reg =3D <0x02620350 4>, <0x02310110 4>;\n" - "> - reg-names =3D \"control\", \"multiplier\";\n" - "> + reg =3D <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;\n" - "> + reg-names =3D \"control\", \"multiplier\", \"post-divider\";\n" - "> fixed-postdiv =3D <2>;\n" + "> #clock-cells = <0>;\n" + "> compatible = \"ti,keystone,main-pll-clock\";\n" + "> clocks = <&refclksys>;\n" + "> - reg = <0x02620350 4>, <0x02310110 4>;\n" + "> - reg-names = \"control\", \"multiplier\";\n" + "> + reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;\n" + "> + reg-names = \"control\", \"multiplier\", \"post-divider\";\n" + "> fixed-postdiv = <2>;\n" "> };\n" - "> =\n" - "\n" + "> \n" "> diff --git a/drivers/clk/keystone/pll.c b/drivers/clk/keystone/pll.c\n" "> index 0dd8a4b..4a375ea 100644\n" "> --- a/drivers/clk/keystone/pll.c\n" @@ -93,58 +82,51 @@ "> void __iomem *pll_ctl0;\n" "> u32 pllm_lower_mask;\n" "> u32 pllm_upper_mask;\n" - "> @@ -102,7 +104,11 @@ static unsigned long clk_pllclk_recalc(struct clk_hw=\n" - " *hw,\n" + "> @@ -102,7 +104,11 @@ static unsigned long clk_pllclk_recalc(struct clk_hw *hw,\n" "> /* read post divider from od bits*/\n" - "> postdiv =3D ((val & pll_data->clkod_mask) >>\n" + "> postdiv = ((val & pll_data->clkod_mask) >>\n" "> pll_data->clkod_shift) + 1;\n" "> - else\n" "> + else if (pll_data->pllod) {\n" - "> + postdiv =3D readl(pll_data->pllod);\n" - "> + postdiv =3D ((postdiv & pll_data->clkod_mask) >>\n" + "> + postdiv = readl(pll_data->pllod);\n" + "> + postdiv = ((postdiv & pll_data->clkod_mask) >>\n" "> + pll_data->clkod_shift) + 1;\n" "> + } else\n" - "> postdiv =3D pll_data->postdiv;\n" - "> =\n" - "\n" - "> rate /=3D (prediv + 1);\n" - "> @@ -172,12 +178,21 @@ static void __init _of_pll_clk_init(struct device_n=\n" - "ode *node, bool pllctrl)\n" + "> postdiv = pll_data->postdiv;\n" + "> \n" + "> rate /= (prediv + 1);\n" + "> @@ -172,12 +178,21 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl)\n" "> /* assume the PLL has output divider register bits */\n" - "> pll_data->clkod_mask =3D CLKOD_MASK;\n" - "> pll_data->clkod_shift =3D CLKOD_SHIFT;\n" + "> pll_data->clkod_mask = CLKOD_MASK;\n" + "> pll_data->clkod_shift = CLKOD_SHIFT;\n" "> +\n" "> + /*\n" "> + * Check if there is an post-divider register. If not\n" "> + * assume od bits are part of control register.\n" "> + */\n" - "> + i =3D of_property_match_string(node, \"reg-names\",\n" + "> + i = of_property_match_string(node, \"reg-names\",\n" "> + \"post-divider\");\n" - "> + pll_data->pllod =3D of_iomap(node, i);\n" + "> + pll_data->pllod = of_iomap(node, i);\n" "> }\n" - "> =\n" - "\n" - "> i =3D of_property_match_string(node, \"reg-names\", \"control\");\n" - "> pll_data->pll_ctl0 =3D of_iomap(node, i);\n" + "> \n" + "> i = of_property_match_string(node, \"reg-names\", \"control\");\n" + "> pll_data->pll_ctl0 = of_iomap(node, i);\n" "> if (!pll_data->pll_ctl0) {\n" "> pr_err(\"%s: ioremap failed\\n\", __func__);\n" "> + iounmap(pll_data->pllod);\n" "> goto out;\n" "> }\n" - "> =\n" - "\n" - "> @@ -193,6 +208,7 @@ static void __init _of_pll_clk_init(struct device_nod=\n" - "e *node, bool pllctrl)\n" - "> pll_data->pllm =3D of_iomap(node, i);\n" + "> \n" + "> @@ -193,6 +208,7 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl)\n" + "> pll_data->pllm = of_iomap(node, i);\n" "> if (!pll_data->pllm) {\n" "> iounmap(pll_data->pll_ctl0);\n" "> + iounmap(pll_data->pllod);\n" "> goto out;\n" "> }\n" "> }\n" - "> -- =\n" - "\n" + "> -- \n" "> 1.9.1\n" - >=20 + > -490d67df368bdee9595c7e589d7d3b552f683e9856f5d889c08f965591c95c27 +3e66b2ede1aeeacd834d7bb377f9ca96de6848085f1ee8552f9b902a68387322
diff --git a/a/1.txt b/N3/1.txt index fda3d98..585d831 100644 --- a/a/1.txt +++ b/N3/1.txt @@ -2,8 +2,7 @@ Quoting Murali Karicheri (2015-05-29 09:04:12) > Main PLL controller has post divider bits in a separate register in > pll controller. Use the value from this register instead of fixed > divider when available. -> = - +> > Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Applied to clk-next. @@ -13,44 +12,35 @@ Mike > --- > .../devicetree/bindings/clock/keystone-pll.txt | 8 ++++---- -> drivers/clk/keystone/pll.c | 20 ++++++++++++++= -++++-- +> drivers/clk/keystone/pll.c | 20 ++++++++++++++++++-- > 2 files changed, 22 insertions(+), 6 deletions(-) -> = - -> diff --git a/Documentation/devicetree/bindings/clock/keystone-pll.txt b/D= -ocumentation/devicetree/bindings/clock/keystone-pll.txt +> +> diff --git a/Documentation/devicetree/bindings/clock/keystone-pll.txt b/Documentation/devicetree/bindings/clock/keystone-pll.txt > index 225990f..47570d2 100644 > --- a/Documentation/devicetree/bindings/clock/keystone-pll.txt > +++ b/Documentation/devicetree/bindings/clock/keystone-pll.txt > @@ -15,8 +15,8 @@ Required properties: -> - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll= --clock" +> - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock" > - clocks : parent clock phandle > - reg - pll control0 and pll multipler registers -> -- reg-names : control and multiplier. The multiplier is applicable only = -for +> -- reg-names : control and multiplier. The multiplier is applicable only for > - main pll clock > +- reg-names : control, multiplier and post-divider. The multiplier and -> + post-divider registers are applicable only for main pll c= -lock -> - fixed-postdiv : fixed post divider value. If absent, use clkod registe= -r bits +> + post-divider registers are applicable only for main pll clock +> - fixed-postdiv : fixed post divider value. If absent, use clkod register bits > for postdiv -> = - +> > @@ -25,8 +25,8 @@ Example: -> #clock-cells =3D <0>; -> compatible =3D "ti,keystone,main-pll-clock"; -> clocks =3D <&refclksys>; -> - reg =3D <0x02620350 4>, <0x02310110 4>; -> - reg-names =3D "control", "multiplier"; -> + reg =3D <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; -> + reg-names =3D "control", "multiplier", "post-divider"; -> fixed-postdiv =3D <2>; +> #clock-cells = <0>; +> compatible = "ti,keystone,main-pll-clock"; +> clocks = <&refclksys>; +> - reg = <0x02620350 4>, <0x02310110 4>; +> - reg-names = "control", "multiplier"; +> + reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; +> + reg-names = "control", "multiplier", "post-divider"; +> fixed-postdiv = <2>; > }; -> = - +> > diff --git a/drivers/clk/keystone/pll.c b/drivers/clk/keystone/pll.c > index 0dd8a4b..4a375ea 100644 > --- a/drivers/clk/keystone/pll.c @@ -73,56 +63,49 @@ r bits > void __iomem *pll_ctl0; > u32 pllm_lower_mask; > u32 pllm_upper_mask; -> @@ -102,7 +104,11 @@ static unsigned long clk_pllclk_recalc(struct clk_hw= - *hw, +> @@ -102,7 +104,11 @@ static unsigned long clk_pllclk_recalc(struct clk_hw *hw, > /* read post divider from od bits*/ -> postdiv =3D ((val & pll_data->clkod_mask) >> +> postdiv = ((val & pll_data->clkod_mask) >> > pll_data->clkod_shift) + 1; > - else > + else if (pll_data->pllod) { -> + postdiv =3D readl(pll_data->pllod); -> + postdiv =3D ((postdiv & pll_data->clkod_mask) >> +> + postdiv = readl(pll_data->pllod); +> + postdiv = ((postdiv & pll_data->clkod_mask) >> > + pll_data->clkod_shift) + 1; > + } else -> postdiv =3D pll_data->postdiv; -> = - -> rate /=3D (prediv + 1); -> @@ -172,12 +178,21 @@ static void __init _of_pll_clk_init(struct device_n= -ode *node, bool pllctrl) +> postdiv = pll_data->postdiv; +> +> rate /= (prediv + 1); +> @@ -172,12 +178,21 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl) > /* assume the PLL has output divider register bits */ -> pll_data->clkod_mask =3D CLKOD_MASK; -> pll_data->clkod_shift =3D CLKOD_SHIFT; +> pll_data->clkod_mask = CLKOD_MASK; +> pll_data->clkod_shift = CLKOD_SHIFT; > + > + /* > + * Check if there is an post-divider register. If not > + * assume od bits are part of control register. > + */ -> + i =3D of_property_match_string(node, "reg-names", +> + i = of_property_match_string(node, "reg-names", > + "post-divider"); -> + pll_data->pllod =3D of_iomap(node, i); +> + pll_data->pllod = of_iomap(node, i); > } -> = - -> i =3D of_property_match_string(node, "reg-names", "control"); -> pll_data->pll_ctl0 =3D of_iomap(node, i); +> +> i = of_property_match_string(node, "reg-names", "control"); +> pll_data->pll_ctl0 = of_iomap(node, i); > if (!pll_data->pll_ctl0) { > pr_err("%s: ioremap failed\n", __func__); > + iounmap(pll_data->pllod); > goto out; > } -> = - -> @@ -193,6 +208,7 @@ static void __init _of_pll_clk_init(struct device_nod= -e *node, bool pllctrl) -> pll_data->pllm =3D of_iomap(node, i); +> +> @@ -193,6 +208,7 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl) +> pll_data->pllm = of_iomap(node, i); > if (!pll_data->pllm) { > iounmap(pll_data->pll_ctl0); > + iounmap(pll_data->pllod); > goto out; > } > } -> -- = - +> -- > 1.9.1 ->=20 +> diff --git a/a/content_digest b/N3/content_digest index 7113330..93f1bbd 100644 --- a/a/content_digest +++ b/N3/content_digest @@ -22,8 +22,7 @@ "> Main PLL controller has post divider bits in a separate register in\n" "> pll controller. Use the value from this register instead of fixed\n" "> divider when available.\n" - "> =\n" - "\n" + "> \n" "> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>\n" "\n" "Applied to clk-next.\n" @@ -33,44 +32,35 @@ "\n" "> ---\n" "> .../devicetree/bindings/clock/keystone-pll.txt | 8 ++++----\n" - "> drivers/clk/keystone/pll.c | 20 ++++++++++++++=\n" - "++++--\n" + "> drivers/clk/keystone/pll.c | 20 ++++++++++++++++++--\n" "> 2 files changed, 22 insertions(+), 6 deletions(-)\n" - "> =\n" - "\n" - "> diff --git a/Documentation/devicetree/bindings/clock/keystone-pll.txt b/D=\n" - "ocumentation/devicetree/bindings/clock/keystone-pll.txt\n" + "> \n" + "> diff --git a/Documentation/devicetree/bindings/clock/keystone-pll.txt b/Documentation/devicetree/bindings/clock/keystone-pll.txt\n" "> index 225990f..47570d2 100644\n" "> --- a/Documentation/devicetree/bindings/clock/keystone-pll.txt\n" "> +++ b/Documentation/devicetree/bindings/clock/keystone-pll.txt\n" "> @@ -15,8 +15,8 @@ Required properties:\n" - "> - compatible : shall be \"ti,keystone,main-pll-clock\" or \"ti,keystone,pll=\n" - "-clock\"\n" + "> - compatible : shall be \"ti,keystone,main-pll-clock\" or \"ti,keystone,pll-clock\"\n" "> - clocks : parent clock phandle\n" "> - reg - pll control0 and pll multipler registers\n" - "> -- reg-names : control and multiplier. The multiplier is applicable only =\n" - "for\n" + "> -- reg-names : control and multiplier. The multiplier is applicable only for\n" "> - main pll clock\n" "> +- reg-names : control, multiplier and post-divider. The multiplier and\n" - "> + post-divider registers are applicable only for main pll c=\n" - "lock\n" - "> - fixed-postdiv : fixed post divider value. If absent, use clkod registe=\n" - "r bits\n" + "> + post-divider registers are applicable only for main pll clock\n" + "> - fixed-postdiv : fixed post divider value. If absent, use clkod register bits\n" "> for postdiv\n" - "> =\n" - "\n" + "> \n" "> @@ -25,8 +25,8 @@ Example:\n" - "> #clock-cells =3D <0>;\n" - "> compatible =3D \"ti,keystone,main-pll-clock\";\n" - "> clocks =3D <&refclksys>;\n" - "> - reg =3D <0x02620350 4>, <0x02310110 4>;\n" - "> - reg-names =3D \"control\", \"multiplier\";\n" - "> + reg =3D <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;\n" - "> + reg-names =3D \"control\", \"multiplier\", \"post-divider\";\n" - "> fixed-postdiv =3D <2>;\n" + "> #clock-cells = <0>;\n" + "> compatible = \"ti,keystone,main-pll-clock\";\n" + "> clocks = <&refclksys>;\n" + "> - reg = <0x02620350 4>, <0x02310110 4>;\n" + "> - reg-names = \"control\", \"multiplier\";\n" + "> + reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;\n" + "> + reg-names = \"control\", \"multiplier\", \"post-divider\";\n" + "> fixed-postdiv = <2>;\n" "> };\n" - "> =\n" - "\n" + "> \n" "> diff --git a/drivers/clk/keystone/pll.c b/drivers/clk/keystone/pll.c\n" "> index 0dd8a4b..4a375ea 100644\n" "> --- a/drivers/clk/keystone/pll.c\n" @@ -93,58 +83,51 @@ "> void __iomem *pll_ctl0;\n" "> u32 pllm_lower_mask;\n" "> u32 pllm_upper_mask;\n" - "> @@ -102,7 +104,11 @@ static unsigned long clk_pllclk_recalc(struct clk_hw=\n" - " *hw,\n" + "> @@ -102,7 +104,11 @@ static unsigned long clk_pllclk_recalc(struct clk_hw *hw,\n" "> /* read post divider from od bits*/\n" - "> postdiv =3D ((val & pll_data->clkod_mask) >>\n" + "> postdiv = ((val & pll_data->clkod_mask) >>\n" "> pll_data->clkod_shift) + 1;\n" "> - else\n" "> + else if (pll_data->pllod) {\n" - "> + postdiv =3D readl(pll_data->pllod);\n" - "> + postdiv =3D ((postdiv & pll_data->clkod_mask) >>\n" + "> + postdiv = readl(pll_data->pllod);\n" + "> + postdiv = ((postdiv & pll_data->clkod_mask) >>\n" "> + pll_data->clkod_shift) + 1;\n" "> + } else\n" - "> postdiv =3D pll_data->postdiv;\n" - "> =\n" - "\n" - "> rate /=3D (prediv + 1);\n" - "> @@ -172,12 +178,21 @@ static void __init _of_pll_clk_init(struct device_n=\n" - "ode *node, bool pllctrl)\n" + "> postdiv = pll_data->postdiv;\n" + "> \n" + "> rate /= (prediv + 1);\n" + "> @@ -172,12 +178,21 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl)\n" "> /* assume the PLL has output divider register bits */\n" - "> pll_data->clkod_mask =3D CLKOD_MASK;\n" - "> pll_data->clkod_shift =3D CLKOD_SHIFT;\n" + "> pll_data->clkod_mask = CLKOD_MASK;\n" + "> pll_data->clkod_shift = CLKOD_SHIFT;\n" "> +\n" "> + /*\n" "> + * Check if there is an post-divider register. If not\n" "> + * assume od bits are part of control register.\n" "> + */\n" - "> + i =3D of_property_match_string(node, \"reg-names\",\n" + "> + i = of_property_match_string(node, \"reg-names\",\n" "> + \"post-divider\");\n" - "> + pll_data->pllod =3D of_iomap(node, i);\n" + "> + pll_data->pllod = of_iomap(node, i);\n" "> }\n" - "> =\n" - "\n" - "> i =3D of_property_match_string(node, \"reg-names\", \"control\");\n" - "> pll_data->pll_ctl0 =3D of_iomap(node, i);\n" + "> \n" + "> i = of_property_match_string(node, \"reg-names\", \"control\");\n" + "> pll_data->pll_ctl0 = of_iomap(node, i);\n" "> if (!pll_data->pll_ctl0) {\n" "> pr_err(\"%s: ioremap failed\\n\", __func__);\n" "> + iounmap(pll_data->pllod);\n" "> goto out;\n" "> }\n" - "> =\n" - "\n" - "> @@ -193,6 +208,7 @@ static void __init _of_pll_clk_init(struct device_nod=\n" - "e *node, bool pllctrl)\n" - "> pll_data->pllm =3D of_iomap(node, i);\n" + "> \n" + "> @@ -193,6 +208,7 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl)\n" + "> pll_data->pllm = of_iomap(node, i);\n" "> if (!pll_data->pllm) {\n" "> iounmap(pll_data->pll_ctl0);\n" "> + iounmap(pll_data->pllod);\n" "> goto out;\n" "> }\n" "> }\n" - "> -- =\n" - "\n" + "> -- \n" "> 1.9.1\n" - >=20 + > -490d67df368bdee9595c7e589d7d3b552f683e9856f5d889c08f965591c95c27 +a0c94d46d03e3e18a224b73c0d5476bcc8174b0ccab4175beb05fddc0a5ec4df
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