From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55010) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z7mXh-0001jm-8c for qemu-devel@nongnu.org; Wed, 24 Jun 2015 11:24:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z7mXg-0004rf-0S for qemu-devel@nongnu.org; Wed, 24 Jun 2015 11:24:49 -0400 Received: from [2001:bc8:30d7:101::1] (port=46353 helo=hall.aurel32.net) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z7mXf-0004rY-Q9 for qemu-devel@nongnu.org; Wed, 24 Jun 2015 11:24:47 -0400 Date: Wed, 24 Jun 2015 17:24:45 +0200 From: Aurelien Jarno Message-ID: <20150624152445.GG19635@aurel32.net> References: <1435073928-21830-1-git-send-email-yongbok.kim@imgtec.com> <1435073928-21830-7-git-send-email-yongbok.kim@imgtec.com> <20150624122850.GC15630@aurel32.net> <558ABDA0.2090505@imgtec.com> <20150624145952.GC27653@aurel32.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20150624145952.GC27653@aurel32.net> Subject: Re: [Qemu-devel] [PATCH v3 06/15] target-mips: raise RI exceptions when FIR.PS = 0 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Yongbok Kim Cc: leon.alrae@imgtec.com, qemu-devel@nongnu.org On 2015-06-24 16:59, Aurelien Jarno wrote: > On 2015-06-24 15:24, Yongbok Kim wrote: > > On 24/06/2015 13:28, Aurelien Jarno wrote: > > > On 2015-06-23 16:38, Yongbok Kim wrote: > > >> 64-bit paired-single (PS) floating point data type is optional in the > > >> pre-Release 6. > > >> It has to raise RI exception when PS type is not implemented. (FIR.PS = 0) > > >> (The PS data type is removed in the Release 6.) > > >> > > >> Signed-off-by: Yongbok Kim > > >> Reviewed-by: Leon Alrae > > >> --- > > > > > > > > This change means that the PS instructions are now enabled only when > > > FCR0_PS is set, instead of being enabled when the FPU in 64-bit mode. > > > Have you checked if we need to update a few CPU definitions for it to > > > work? I am thinking for example about all the CPU with FCR0_F64, but > > > without FCR0_PS. > > > > > > Otherwise the patch looks fine to me. > > > > > > > I just checked all the core definitions. All other cores are OK and even > > the patch brought some corrections of behaviour like 24Kf shouldn't support > > PS data type but it was wrongly enabled. > > Great. > > > However Loongson-2E and Loongson-2F might be broken because of the patch. > > The question is that how to allow ps data type for these Loongson cores as > > in the MIPS III architecture all the those FCR0 field is reserved apart > > from implementation and revision numbers. > > (1) I could add few more line in check_ps() to allow Loongson according to > > the Implementation and Revision numbers. (2) Otherwise updating the > > reserved fields against later architectures - F64/PS/D/S. Perhaps that > > would cause another problem if an application is expecting all zeroes on > > the field. > > I think the best would be to add a line in check_ps(). I guess the > easiest is to check if the CPU supports the LOONGSON ISA, that is > testing (ctx->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)). Or probably even better: ctx.ps = ((env->active_fpu.fcr0 >> FCR0_PS) & 1) || (ctx->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)) -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://www.aurel32.net