diff for duplicates of <20150629163201.GA1524@linaro.org> diff --git a/a/1.txt b/N1/1.txt index 1244abc..fc895c3 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -134,86 +134,86 @@ the coherency domain. Would something like that work? >the first cpu core only. The full structure should look like this > > cpus { -> cpu0: cpu@0 { +> cpu0: cpu at 0 { > compatible = "arm,cortex-a15"; > power-domains = <&pd_a2sl>; > next-level-cache = <&L2_CA15>; > }; > -> cpu1: cpu@1 { +> cpu1: cpu at 1 { > compatible = "arm,cortex-a15"; > power-domains = <&pd_a2sl>; > next-level-cache = <&L2_CA15>; > }; > -> cpu2: cpu@2 { +> cpu2: cpu at 2 { > compatible = "arm,cortex-a15"; > power-domains = <&pd_a2sl>; > next-level-cache = <&L2_CA15>; > }; > -> cpu3: cpu@3 { +> cpu3: cpu at 3 { > compatible = "arm,cortex-a15"; > power-domains = <&pd_a2sl>; > next-level-cache = <&L2_CA15>; > }; > -> cpu4: cpu@4 { +> cpu4: cpu at 4 { > compatible = "arm,cortex-a7"; > power-domains = <&pd_a2kl>; > next-level-cache = <&L2_CA7>; > }; > -> cpu5: cpu@5 { +> cpu5: cpu at 5 { > compatible = "arm,cortex-a7"; > power-domains = <&pd_a2kl>; > next-level-cache = <&L2_CA7>; > }; > -> cpu6: cpu@6 { +> cpu6: cpu at 6 { > compatible = "arm,cortex-a7"; > power-domains = <&pd_a2kl>; > next-level-cache = <&L2_CA7>; > }; > -> cpu7: cpu@7 { +> cpu7: cpu at 7 { > compatible = "arm,cortex-a7"; > power-domains = <&pd_a2kl>; > next-level-cache = <&L2_CA7>; > }; > }; > -> L2_CA15: cache-controller@0 { +> L2_CA15: cache-controller at 0 { > compatible = "cache"; > power-domains = <&pd_a3sm>; > }; > -> L2_CA7: cache-controller@1 { +> L2_CA7: cache-controller at 1 { > compatible = "cache"; > power-domains = <&pd_a3km>; > }; > >And the PM Domain part (which is complete in upstream): > -> pd_c4: c4@0 { +> pd_c4: c4 at 0 { > #power-domain-cells = <0>; > -> pd_a3sm: a3sm@20 { +> pd_a3sm: a3sm at 20 { > reg = <20>; > #power-domain-cells = <0>; > -> pd_a2sl: a2sl@21 { +> pd_a2sl: a2sl at 21 { > reg = <21>; > #power-domain-cells = <0>; > }; > }; > -> pd_a3km: a3km@22 { +> pd_a3km: a3km at 22 { > reg = <22>; > #size-cells = <0>; > #power-domain-cells = <0>; > -> pd_a2kl: a2kl@23 { +> pd_a2kl: a2kl at 23 { > reg = <23>; > #power-domain-cells = <0>; > }; diff --git a/a/content_digest b/N1/content_digest index da3e592..29bfbf6 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,18 +1,10 @@ "ref\01435374156-19214-1-git-send-email-lina.iyer@linaro.org\0" "ref\01435374156-19214-10-git-send-email-lina.iyer@linaro.org\0" "ref\0CAMuHMdULThWEZmyLEK_9WeK6DSNhrQdiZQLWNhi1Q6dwZTkkMg@mail.gmail.com\0" - "From\0Lina Iyer <lina.iyer@linaro.org>\0" - "Subject\0Re: [PATCH RFC v2 09/16] arm: domain: Add platform callbacks for domain power on/off\0" + "From\0lina.iyer@linaro.org (Lina Iyer)\0" + "Subject\0[PATCH RFC v2 09/16] arm: domain: Add platform callbacks for domain power on/off\0" "Date\0Mon, 29 Jun 2015 10:32:01 -0600\0" - "To\0Geert Uytterhoeven <geert@linux-m68k.org>\0" - "Cc\0Kevin Hilman <khilman@linaro.org>" - Rafael J. Wysocki <rjw@rjwysocki.net> - Ulf Hansson <ulf.hansson@linaro.org> - " Krzysztof Koz\305\202owski <k.kozlowski@samsung.com>" - Linux PM list <linux-pm@vger.kernel.org> - linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org> - msivasub@codeaurora.org - " agross@codeaurora.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On Mon, Jun 29 2015 at 07:36 -0600, Geert Uytterhoeven wrote:\n" @@ -151,86 +143,86 @@ ">the first cpu core only. The full structure should look like this\n" ">\n" "> cpus {\n" - "> cpu0: cpu@0 {\n" + "> cpu0: cpu at 0 {\n" "> compatible = \"arm,cortex-a15\";\n" "> power-domains = <&pd_a2sl>;\n" "> next-level-cache = <&L2_CA15>;\n" "> };\n" ">\n" - "> cpu1: cpu@1 {\n" + "> cpu1: cpu at 1 {\n" "> compatible = \"arm,cortex-a15\";\n" "> power-domains = <&pd_a2sl>;\n" "> next-level-cache = <&L2_CA15>;\n" "> };\n" ">\n" - "> cpu2: cpu@2 {\n" + "> cpu2: cpu at 2 {\n" "> compatible = \"arm,cortex-a15\";\n" "> power-domains = <&pd_a2sl>;\n" "> next-level-cache = <&L2_CA15>;\n" "> };\n" ">\n" - "> cpu3: cpu@3 {\n" + "> cpu3: cpu at 3 {\n" "> compatible = \"arm,cortex-a15\";\n" "> power-domains = <&pd_a2sl>;\n" "> next-level-cache = <&L2_CA15>;\n" "> };\n" ">\n" - "> cpu4: cpu@4 {\n" + "> cpu4: cpu at 4 {\n" "> compatible = \"arm,cortex-a7\";\n" "> power-domains = <&pd_a2kl>;\n" "> next-level-cache = <&L2_CA7>;\n" "> };\n" ">\n" - "> cpu5: cpu@5 {\n" + "> cpu5: cpu at 5 {\n" "> compatible = \"arm,cortex-a7\";\n" "> power-domains = <&pd_a2kl>;\n" "> next-level-cache = <&L2_CA7>;\n" "> };\n" ">\n" - "> cpu6: cpu@6 {\n" + "> cpu6: cpu at 6 {\n" "> compatible = \"arm,cortex-a7\";\n" "> power-domains = <&pd_a2kl>;\n" "> next-level-cache = <&L2_CA7>;\n" "> };\n" ">\n" - "> cpu7: cpu@7 {\n" + "> cpu7: cpu at 7 {\n" "> compatible = \"arm,cortex-a7\";\n" "> power-domains = <&pd_a2kl>;\n" "> next-level-cache = <&L2_CA7>;\n" "> };\n" "> };\n" ">\n" - "> L2_CA15: cache-controller@0 {\n" + "> L2_CA15: cache-controller at 0 {\n" "> compatible = \"cache\";\n" "> power-domains = <&pd_a3sm>;\n" "> };\n" ">\n" - "> L2_CA7: cache-controller@1 {\n" + "> L2_CA7: cache-controller at 1 {\n" "> compatible = \"cache\";\n" "> power-domains = <&pd_a3km>;\n" "> };\n" ">\n" ">And the PM Domain part (which is complete in upstream):\n" ">\n" - "> pd_c4: c4@0 {\n" + "> pd_c4: c4 at 0 {\n" "> #power-domain-cells = <0>;\n" ">\n" - "> pd_a3sm: a3sm@20 {\n" + "> pd_a3sm: a3sm at 20 {\n" "> reg = <20>;\n" "> #power-domain-cells = <0>;\n" ">\n" - "> pd_a2sl: a2sl@21 {\n" + "> pd_a2sl: a2sl at 21 {\n" "> reg = <21>;\n" "> #power-domain-cells = <0>;\n" "> };\n" "> };\n" ">\n" - "> pd_a3km: a3km@22 {\n" + "> pd_a3km: a3km at 22 {\n" "> reg = <22>;\n" "> #size-cells = <0>;\n" "> #power-domain-cells = <0>;\n" ">\n" - "> pd_a2kl: a2kl@23 {\n" + "> pd_a2kl: a2kl at 23 {\n" "> reg = <23>;\n" "> #power-domain-cells = <0>;\n" "> };\n" @@ -246,4 +238,4 @@ "\n" -- Lina -1c879e7bc7d0bbdcbf32d1378ab1ffcfc18c3af8bb766d69a74b83cff5835026 +c138bccdd166437448b52dccca79110e117c00bb830a246f93c33cc8938a4039
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