From mboxrd@z Thu Jan 1 00:00:00 1970 From: Pavel Machek Subject: Re: [PATCH] drm/i915: apply the PCI_D0/D3 hibernation workaround everywhere on pre GEN6 Date: Tue, 30 Jun 2015 19:27:06 +0200 Message-ID: <20150630172706.GA28262@amd> References: <1435673207-23030-1-git-send-email-imre.deak@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from atrey.karlin.mff.cuni.cz (atrey.karlin.mff.cuni.cz [195.113.26.193]) by gabe.freedesktop.org (Postfix) with ESMTP id 54D756E9DE for ; Tue, 30 Jun 2015 10:27:08 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1435673207-23030-1-git-send-email-imre.deak@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Imre Deak Cc: Paul Bolle , Dirk Griesbach , Jani Nikula , Mikko Rapeli , intel-gfx@lists.freedesktop.org, "Rafael J. Wysocki" , stable@vger.kernel.org, Daniel Vetter , Ilya Tumaykin List-Id: intel-gfx@lists.freedesktop.org SGkhCgo+IGNvbW1pdCBkYTJiYzFiOWRiMzM1MWFkZGQyOTNlNWI4Mjc1N2VmZTFmNzdlZDFkCj4g QXV0aG9yOiBJbXJlIERlYWsgPGltcmUuZGVha0BpbnRlbC5jb20+Cj4gRGF0ZTogICBUaHUgT2N0 IDIzIDE5OjIzOjI2IDIwMTQgKzAzMDAKPiAKPiAgICAgZHJtL2k5MTU6IGFkZCBwb3dlcm9mZl9s YXRlIGhhbmRsZXIKPiAKPiBpbnRyb2R1Y2VkIGEgcmVncmVzc2lvbiBvbiBvbGQgcGxhdGZvcm1z IGR1cmluZyBoaWJlcm5hdGlvbi4gQSB3b3JrYXJvdW5kIHdhcwo+IGFkZGVkIGluCj4gCj4gY29t bWl0IGFiM2JlNzNmYTdiNDNmNGMzNjQ4Y2UyOWI1ZmQ2NDllYTU0ZDNhZGIKPiBBdXRob3I6IElt cmUgRGVhayA8aW1yZS5kZWFrQGludGVsLmNvbT4KPiBEYXRlOiAgIE1vbiBNYXIgMiAxMzowNDo0 MSAyMDE1ICswMjAwCj4gCj4gICAgIGRybS9pOTE1OiBnZW40OiB3b3JrIGFyb3VuZCBoYW5nIGR1 cmluZyBoaWJlcm5hdGlvbgo+IAo+IHVzaW5nIGFuIGV4cGxpY2l0IGJsYWNrbGlzdCBmb3IgdGhl IEdFTnMvQklPUyB2ZW5kb3JzIHdoZXJlIHRoZSBpc3N1ZSB3YXMKPiByZXBvcnRlZC4gTGF0ZXIg dGhlcmUgd2UgaGFkIHJlcG9ydHMgb2YgdGhlIHNhbWUgZmFpbHVyZSBvbiBwbGF0Zm9ybXMgbm90 IG9uCj4gdGhpcyBsaXN0Lgo+IAo+IFRvIG15IGJlc3Qga25vd2xlZGdlIHRoZSBjb3JyZWN0IHRo aW5nIHRvIGRvIGlzIHN0aWxsIHRvIHB1dCB0aGUgZGV2aWNlIHRvIFBDSQo+IEQzIHN0YXRlIGR1 cmluZyBoaWJlcm5hdGlvbiwgc2VlIFsxXSBhbmQgWzJdIGZvciB0aGUgcmVhc29ucy4gVGhpcwo+ IGFsc28gYWxpZ25zCgpIbW0sIHNvIHRoZSByZWFzb25zIGFjY29yZGluZyB0byB5b3UgYXJlOgoK PiAtIEFDUEkgbWFuZGF0ZXMgdGhhdCB0aGUgT1NQTSAodGhlIGtlcm5lbCBpbiBvdXIgY2FzZSkg cHV0cyBhbGwKPiAgIGRldmljZXMKPiAgIGludG8gRDMgdGhhdCBhcmUgbm90IHdha2UtdXAgc291 cmNlcyAoaTkxNSBpcyBub3QpIChLdWRvcyB0byBWaWxsZQo+ICAgZm9yCj4gICBwb2ludGluZyB0 aGlzIG91dCkKCkNsZWFybHksIEJJT1MgdmVuZG9ycyBkaWQgbm90IHJlYWQgdGhpcywgYW5kIHBy ZXR0eSBjbGVhcmx5IFdpbmRvd3MKZG8gbm90IGZvbGxvdyB0aGUgc3BlY3MsIGVpdGhlci4gVGhh dCBtZWFucyB0aGF0IGl0IGlzIGJhZCBpZGVhIGZvciB1cwp0byBmb2xsb3cgdGhlIHNwZWNzLCBh bmQgdHJpZ2dlciBCSU9TIGJ1Z3MuIAoKPiAtIEVtYmVkZGVkIHBhbmVscyBoYXZlIGEgd2VsbCBk ZWZpbmVkIHNodXRkb3duIHNlcXVlbmNlLiBXZSBkb24ndAo+ICAgaGF2ZQo+ICAgYW55IGdvb2Qg cmVhc29uIHRvIG5vdCBmb2xsb3cgdGhpcywgaW4gZmFjdCBmb3Igc29tZSBwYW5lbHMgdGhlCj4g ICBzdWJzZXF1ZW50IHJlaW5pdGlhbGl6YXRpb24gY291bGQgYmUgcHJvYmxlbWF0aWMgaW4gY2Fz ZSBvZiBhIGhhcmQKPiAgIHBvd2VyLW9mZi4gKFRoYW5rcyB0byBKYW5pIGZvciB0aGlzIGluZm8p CgpQbGVhc2UgY2l0ZSBjb25jcmV0ZSBleGFtcGxlLiBJIGhhdmUgeWV0IHRvIHNlZSBtYWNoaW5l IHRoYXQgd291bGQgbm90CnBvd2VyIHVwIG9uIGZvcmNlZCBwb3dlciBkb3duLiBJbiBmYWN0LCBJ IGFyZ3VlIHRoYXQgc3VjaCBtYWNoaW5lCndvdWxkIGJlIHZlcnkgYnJva2VuLCBhbmQgdGhhdCBz dWNoIG1hY2hpbmUgZG9lcyBub3QgZXhpc3QuIFdoaWxlIHdlCmhhdmUgdGhlc2UgcmVhbCBtYWNo aW5lcyBicm9rZW46Cgo+ICsJICogTGVub3ZvIFRoaW5rcGFkIFgzMDEsIFg2MXMsIFg2MCwgVDYw LCBYNDEKPiArCSAqIEZ1aml0c3UgRlNDIFM3MTEwCj4gKwkgKiBBY2VyIEFzcGlyZSAxODMwVAoK V2hhdCBtYWtlcyB5b3UgdGhpbmsgdGhhdCBCSU9TIHdyaXRlcnMgd2lsbCBkbyBzb21ldGhpbmcg ZGlmZmVyZW50IGZvcgpHZW42KyBoYXJkd2FyZT8gWDMwMSBpcyBub3QgdGhhdCBvbGQuCgkJCQkJ CQkJCVBhdmVsCi0tIAooZW5nbGlzaCkgaHR0cDovL3d3dy5saXZlam91cm5hbC5jb20vfnBhdmVs bWFjaGVrCihjZXNreSwgcGljdHVyZXMpIGh0dHA6Ly9hdHJleS5rYXJsaW4ubWZmLmN1bmkuY3ov fnBhdmVsL3BpY3R1cmUvaG9yc2VzL2Jsb2cuaHRtbApfX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fXwpJbnRlbC1nZnggbWFpbGluZyBsaXN0CkludGVsLWdmeEBs aXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cDovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFu L2xpc3RpbmZvL2ludGVsLWdmeAo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from atrey.karlin.mff.cuni.cz ([195.113.26.193]:37592 "EHLO atrey.karlin.mff.cuni.cz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751344AbbF3R1I (ORCPT ); Tue, 30 Jun 2015 13:27:08 -0400 Date: Tue, 30 Jun 2015 19:27:06 +0200 From: Pavel Machek To: Imre Deak Cc: intel-gfx@lists.freedesktop.org, "Rafael J. Wysocki" , Ilya Tumaykin , Dirk Griesbach , Mikko Rapeli , Paul Bolle , Ville =?iso-8859-1?Q?Syrj=E4l=E4?= , Jani Nikula , Daniel Vetter , stable@vger.kernel.org Subject: Re: [PATCH] drm/i915: apply the PCI_D0/D3 hibernation workaround everywhere on pre GEN6 Message-ID: <20150630172706.GA28262@amd> References: <1435673207-23030-1-git-send-email-imre.deak@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1435673207-23030-1-git-send-email-imre.deak@intel.com> Sender: stable-owner@vger.kernel.org List-ID: Hi! > commit da2bc1b9db3351addd293e5b82757efe1f77ed1d > Author: Imre Deak > Date: Thu Oct 23 19:23:26 2014 +0300 > > drm/i915: add poweroff_late handler > > introduced a regression on old platforms during hibernation. A workaround was > added in > > commit ab3be73fa7b43f4c3648ce29b5fd649ea54d3adb > Author: Imre Deak > Date: Mon Mar 2 13:04:41 2015 +0200 > > drm/i915: gen4: work around hang during hibernation > > using an explicit blacklist for the GENs/BIOS vendors where the issue was > reported. Later there we had reports of the same failure on platforms not on > this list. > > To my best knowledge the correct thing to do is still to put the device to PCI > D3 state during hibernation, see [1] and [2] for the reasons. This > also aligns Hmm, so the reasons according to you are: > - ACPI mandates that the OSPM (the kernel in our case) puts all > devices > into D3 that are not wake-up sources (i915 is not) (Kudos to Ville > for > pointing this out) Clearly, BIOS vendors did not read this, and pretty clearly Windows do not follow the specs, either. That means that it is bad idea for us to follow the specs, and trigger BIOS bugs. > - Embedded panels have a well defined shutdown sequence. We don't > have > any good reason to not follow this, in fact for some panels the > subsequent reinitialization could be problematic in case of a hard > power-off. (Thanks to Jani for this info) Please cite concrete example. I have yet to see machine that would not power up on forced power down. In fact, I argue that such machine would be very broken, and that such machine does not exist. While we have these real machines broken: > + * Lenovo Thinkpad X301, X61s, X60, T60, X41 > + * Fujitsu FSC S7110 > + * Acer Aspire 1830T What makes you think that BIOS writers will do something different for Gen6+ hardware? X301 is not that old. Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html