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diff for duplicates of <20150702193826.GA885@linaro.org>

diff --git a/a/1.txt b/N1/1.txt
index 7d0f78f..6094839 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -42,11 +42,11 @@ Another option, that might be cleaner, is that we could have a PM domain
 for CPUs that would set up the compatibility flag to "arm,pd" and you
 could nest that domain inside pd_a2sl and pd_a2kl.
 
-pd_c4: c4@0 {
+pd_c4: c4 at 0 {
 	[...]
-	pd_a3sm: a3sm@20 {
+	pd_a3sm: a3sm at 20 {
 		[...]
-		pd_a2sl: a2sl@21 {
+		pd_a2sl: a2sl at 21 {
 			reg = <21>;
 			#power-domain-cells = <0>;
 			pd_cpu_sl: pd1 { <-- Virtual PM domain
@@ -57,7 +57,7 @@ pd_c4: c4@0 {
 };
 
 cpus {
-	cpu0: cpu@0 {
+	cpu0: cpu at 0 {
 		compatible = "arm,cortex-a15";
 		power-domains = <&pd_cpu_sl>; <-- here we refer to the
 						  virtual PM domain
diff --git a/a/content_digest b/N1/content_digest
index fa8c941..d7a8786 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -3,18 +3,10 @@
  "ref\0CAMuHMdULThWEZmyLEK_9WeK6DSNhrQdiZQLWNhi1Q6dwZTkkMg@mail.gmail.com\0"
  "ref\020150629163201.GA1524@linaro.org\0"
  "ref\0CAMuHMdWL09Loe2EFUMc-kRML7Ckn7a6G1_hvPnaqkDYnhkXjog@mail.gmail.com\0"
- "From\0Lina Iyer <lina.iyer@linaro.org>\0"
- "Subject\0Re: [PATCH RFC v2 09/16] arm: domain: Add platform callbacks for domain power on/off\0"
+ "From\0lina.iyer@linaro.org (Lina Iyer)\0"
+ "Subject\0[PATCH RFC v2 09/16] arm: domain: Add platform callbacks for domain power on/off\0"
  "Date\0Thu, 2 Jul 2015 13:38:26 -0600\0"
- "To\0Geert Uytterhoeven <geert@linux-m68k.org>\0"
- "Cc\0Kevin Hilman <khilman@linaro.org>"
-  Rafael J. Wysocki <rjw@rjwysocki.net>
-  Ulf Hansson <ulf.hansson@linaro.org>
- " Krzysztof Koz\305\202owski <k.kozlowski@samsung.com>"
-  Linux PM list <linux-pm@vger.kernel.org>
-  linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>
-  msivasub@codeaurora.org
- " agross@codeaurora.org\0"
+ "To\0linux-arm-kernel@lists.infradead.org\0"
  "\00:1\0"
  "b\0"
  "On Tue, Jun 30 2015 at 09:10 -0600, Geert Uytterhoeven wrote:\n"
@@ -61,11 +53,11 @@
  "for CPUs that would set up the compatibility flag to \"arm,pd\" and you\n"
  "could nest that domain inside pd_a2sl and pd_a2kl.\n"
  "\n"
- "pd_c4: c4@0 {\n"
+ "pd_c4: c4 at 0 {\n"
  "\t[...]\n"
- "\tpd_a3sm: a3sm@20 {\n"
+ "\tpd_a3sm: a3sm at 20 {\n"
  "\t\t[...]\n"
- "\t\tpd_a2sl: a2sl@21 {\n"
+ "\t\tpd_a2sl: a2sl at 21 {\n"
  "\t\t\treg = <21>;\n"
  "\t\t\t#power-domain-cells = <0>;\n"
  "\t\t\tpd_cpu_sl: pd1 { <-- Virtual PM domain\n"
@@ -76,7 +68,7 @@
  "};\n"
  "\n"
  "cpus {\n"
- "\tcpu0: cpu@0 {\n"
+ "\tcpu0: cpu at 0 {\n"
  "\t\tcompatible = \"arm,cortex-a15\";\n"
  "\t\tpower-domains = <&pd_cpu_sl>; <-- here we refer to the\n"
  "\t\t\t\t\t\t  virtual PM domain\n"
@@ -100,4 +92,4 @@
  "\n"
  [1]. http://www.spinics.net/lists/arm-kernel/msg423430.html
 
-3449d50c30eec261d82f90bc463a3ec649e0db46a6b7acdf39895b5d5abbf21e
+d2f532dc6adb4071627f96babbf02d1e5a8f37bc8ca6ac1d984d5557c0bc7b07

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