From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52776) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZC1xO-0008UH-8E for qemu-devel@nongnu.org; Mon, 06 Jul 2015 04:40:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZC1xM-0000CI-Mm for qemu-devel@nongnu.org; Mon, 06 Jul 2015 04:40:54 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:47135) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZC1xM-0000CB-Gw for qemu-devel@nongnu.org; Mon, 06 Jul 2015 04:40:52 -0400 Date: Mon, 6 Jul 2015 10:40:51 +0200 From: Aurelien Jarno Message-ID: <20150706084051.GU931@aurel32.net> References: <3e0f5249da1e943da65e0cea0f907a1c7bc3271a.1435723168.git.serge.vakulenko@gmail.com> <20150701133732.GA8793@aurel32.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Subject: Re: [Qemu-devel] [PATCH pic32 v2 4/5] Two new processor variants: M4K and microAptivP. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Serge Vakulenko Cc: Leon Alrae , qemu-devel@nongnu.org On 2015-07-05 20:48, Serge Vakulenko wrote: > On Wed, Jul 1, 2015 at 6:37 AM, Aurelien Jarno wrote: > > On 2015-06-30 21:12, Serge Vakulenko wrote: > >> Signed-off-by: Serge Vakulenko > >> --- > >> target-mips/cpu.h | 2 ++ > >> target-mips/translate_init.c | 46 ++++++++++++++++++++++++++++++++++++++++++++ > >> 2 files changed, 48 insertions(+) > >> > >> diff --git a/target-mips/cpu.h b/target-mips/cpu.h > >> index ab830ee..9f5890c 100644 > >> --- a/target-mips/cpu.h > >> +++ b/target-mips/cpu.h > >> @@ -394,6 +394,7 @@ struct CPUMIPSState { > >> #define CP0C0_M 31 > >> #define CP0C0_K23 28 > >> #define CP0C0_KU 25 > >> +#define CP0C0_SB 21 > > > > Bits in the range 16:24 are implementation specific, so I do wonder if > > we want to have this bit there. At least we should mark it as > > implementation specific. > > I tried to make the configuration as close as possible to a real PIC32 > microcontroller - that's why I added Config0.SB and Config7.WII bits. > These bits are described in appropriate Microchip docs. As they are > not relevant for the simulation purposes, I'll better remove them for > simplicity. It's fine if they are needed, but I suggest in that case to chose a name showing it's PIC32 specific, something like CP0C0_PIC32_SB. -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://www.aurel32.net