From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41628) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZC2hb-0003p2-0F for qemu-devel@nongnu.org; Mon, 06 Jul 2015 05:28:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZC2hZ-0008KO-Lz for qemu-devel@nongnu.org; Mon, 06 Jul 2015 05:28:38 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:47363) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZC2hZ-0008Ju-FU for qemu-devel@nongnu.org; Mon, 06 Jul 2015 05:28:37 -0400 Date: Mon, 6 Jul 2015 11:28:35 +0200 From: Aurelien Jarno Message-ID: <20150706092835.GY931@aurel32.net> References: <20150701110709.GC11361@aurel32.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Subject: Re: [Qemu-devel] [PATCH pic32 v2 3/5] Added support for external interrupt controller (EIC) mode. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Serge Vakulenko Cc: Leon Alrae , qemu-devel@nongnu.org On 2015-07-05 20:05, Serge Vakulenko wrote: > >> } else { > >> /* A MIPS configured with compatibility or VInt (Vectored Interrupts) > >> diff --git a/target-mips/helper.c b/target-mips/helper.c > >> index 8e3204a..7e25998 100644 > >> --- a/target-mips/helper.c > >> +++ b/target-mips/helper.c > >> @@ -574,23 +574,31 @@ void mips_cpu_do_interrupt(CPUState *cs) > >> unsigned int vector; > >> unsigned int pending = (env->CP0_Cause & CP0Ca_IP_mask) >> 8; > >> > >> - pending &= env->CP0_Status >> 8; > >> /* Compute the Vector Spacing. */ > >> spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & ((1 << 6) - 1); > >> spacing <<= 5; > >> > >> - if (env->CP0_Config3 & (1 << CP0C3_VInt)) { > >> + if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { > >> + /* For VEIC mode, the external interrupt controller feeds the > >> + * vector through the CP0Cause IP lines. */ > >> + vector = pending; > >> + > >> + /* Architecturally, this is chip-specific behavior. > >> + * TODO: some processors, like PIC32MZ, > >> + * provide vector in a different way. > >> + * Some processors, like PIC32, have a separate > >> + * bit INTCON.MVEC to explicitly enable vectored mode, > >> + * disabled by default. */ > >> + spacing = 0; > >> + } else { > >> /* For VInt mode, the MIPS computes the vector internally. */ > >> + pending &= env->CP0_Status >> 8; > >> for (vector = 7; vector > 0; vector--) { > >> if (pending & (1 << vector)) { > >> /* Found it. */ > >> break; > >> } > >> } > >> - } else { > >> - /* For VEIC mode, the external interrupt controller feeds the > >> - vector through the CP0Cause IP lines. */ > >> - vector = pending; > >> } > > > > The changes looks correct, but I do wonder why you swap the test on > > CP0_Config3. It would be less changes to just move the pending masking > > with CP0_Status inside the VInt mode. > > According to MIPS PRA spec (MD00090), VInt bit becomes do-not-care > when Config3.VEIC is enabled. So it makes little sense to rely on it's > value here. And it makes it easier to understand this way. EIC and > VInt modes are quite different: better not to mix them up. Ok I understand now. -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://www.aurel32.net