From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42594) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZC2k2-0005pj-NC for qemu-devel@nongnu.org; Mon, 06 Jul 2015 05:31:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZC2jy-00032C-MF for qemu-devel@nongnu.org; Mon, 06 Jul 2015 05:31:10 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:47380) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZC2jy-00031p-GA for qemu-devel@nongnu.org; Mon, 06 Jul 2015 05:31:06 -0400 Date: Mon, 6 Jul 2015 11:31:05 +0200 From: Aurelien Jarno Message-ID: <20150706093105.GZ931@aurel32.net> References: <20150701110709.GC11361@aurel32.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Subject: Re: [Qemu-devel] [PATCH pic32 v2 3/5] Added support for external interrupt controller (EIC) mode. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Serge Vakulenko Cc: Leon Alrae , qemu-devel@nongnu.org On 2015-07-05 20:31, Serge Vakulenko wrote: > On Sun, Jul 5, 2015 at 8:05 PM, Serge Vakulenko > wrote: > > On Wed, Jul 1, 2015 at 4:07 AM, Aurelien Jarno wrote: > >> On 2015-06-30 21:12, Serge Vakulenko wrote: > >>> diff --git a/target-mips/cpu.h b/target-mips/cpu.h > >>> index c476166..ab830ee 100644 > >>> --- a/target-mips/cpu.h > >>> +++ b/target-mips/cpu.h > >>> @@ -664,7 +669,9 @@ static inline int cpu_mips_hw_interrupts_pending(CPUMIPSState *env) > >>> if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { > >>> /* A MIPS configured with a vectorizing external interrupt controller > >>> will feed a vector into the Cause pending lines. The core treats > >>> - the status lines as a vector level, not as indiviual masks. */ > >>> + the status lines as a vector level, not as individual masks. */ > >>> + pending >>= CP0Ca_IP + 2; > >>> + status >>= CP0Ca_IP + 2; > >>> r = pending > status; > >> > >> I don't think it's needed. As the pending and status field have been > >> masked above, we don't need to shift them to do the comparison. > > This is not true. The values still need to be shifted to get rid of > soft interrupt bits, otherwise the comparison becomes incorrect. It means we need to have a different mask with the internal interrupt controller and with the external one. I therefore think it's better to do the masking differently. For that you can add a CP0Ca_RIPL_mask constant and use it for the VEIC case, and move the current masking in the non VEIC case. -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://www.aurel32.net