Re: [PATCH] x86: Fix detection of GCC -mpreferred-stack-boundary support

[Ingo Molnar <mingo@kernel.org>]

* Andy Lutomirski <luto@amacapital.net> wrote:

> > My reasoning: on modern uarchs there's no penalty for 32-bit misalignment of 
> > 64-bit variables, only if they cross 64-byte cache lines, which should be rare 
> > with a chance of 1:16. This small penalty (of at most +1 cycle in some 
> > circumstances IIRC) should be more than counterbalanced by the compression of 
> > the stack by 5% on average.
> 
> I'll counter with: what's the benefit?  There are no operations that will 
> naturally change RSP by anything that isn't a multiple of 8 (there's no pushl in 
> 64-bit mode, or at least not on AMD chips -- the Intel manual is a bit vague on 
> this point), so we'll end up with RSP being a multiple of 8 regardless.  Even if 
> we somehow shaved 4 bytes off in asm, that still wouldn't buy us anything, as a 
> dangling 4 bytes at the bottom of the stack isn't useful for anything.

Yeah, so it might be utilized in frame-pointer less builds (which we might be able 
to utilize in the future if sane Dwarf code comes around), which does not use 
push/pop to manage the stack but often has patterns like:

ffffffff8102aa90 <SyS_getpriority>:
ffffffff8102aa90:       48 83 ec 18             sub    $0x18,%rsp

and uses MOVs to manage the stack. Those kinds of stack frames could be 4-byte 
granular as well.

But yeah ... it's pretty marginal.

Thanks,

	Ingo