diff for duplicates of <20150709070207.GB23464@tiger>

diff --git a/a/1.txt b/N1/1.txt
index 3c18c8f..d8018a7 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -1,4 +1,4 @@
-On Wed, Jun 17, 2015 at 11:39:27PM +0800, Frank.Li@freescale.com wrote:
+On Wed, Jun 17, 2015 at 11:39:27PM +0800, Frank.Li at freescale.com wrote:
 > From: Frank Li <Frank.Li@freescale.com>
 > 
 > Add new SOC i.MX6UL dtb file support, including evk board
@@ -82,7 +82,7 @@ On Wed, Jun 17, 2015 at 11:39:27PM +0800, Frank.Li@freescale.com wrote:
 > +		#address-cells = <1>;
 > +		#size-cells = <0>;
 > +
-> +		reg_sd1_vmmc: regulator@1 {
+> +		reg_sd1_vmmc: regulator at 1 {
 
 There should be a 'reg' property when unit-address is coded in node
 name.  Also, the numbering starts from 0.
@@ -479,7 +479,7 @@ Use an explicit pad configuration value.
 > +		#address-cells = <1>;
 > +		#size-cells = <0>;
 > +
-> +		cpu0: cpu@0 {
+> +		cpu0: cpu at 0 {
 > +			compatible = "arm,cortex-a7";
 > +			device_type = "cpu";
 > +			reg = <0>;
@@ -515,7 +515,7 @@ Wrap these two lines to make them a bit shorter.
 > +		};
 > +	};
 > +
-> +	intc: interrupt-controller@00a01000 {
+> +	intc: interrupt-controller at 00a01000 {
 > +		compatible = "arm,cortex-a7-gic";
 > +		#interrupt-cells = <3>;
 > +		interrupt-controller;
@@ -566,21 +566,21 @@ Wrap these two lines to make them a bit shorter.
 > +			status = "disabled";
 > +		};
 > +
-> +		aips1: aips-bus@02000000 {
+> +		aips1: aips-bus at 02000000 {
 > +			compatible = "fsl,aips-bus", "simple-bus";
 > +			#address-cells = <1>;
 > +			#size-cells = <1>;
 > +			reg = <0x02000000 0x100000>;
 > +			ranges;
 > +
-> +			spba-bus@02000000 {
+> +			spba-bus at 02000000 {
 > +				compatible = "fsl,spba-bus", "simple-bus";
 > +				#address-cells = <1>;
 > +				#size-cells = <1>;
 > +				reg = <0x02000000 0x40000>;
 > +				ranges;
 > +
-> +				ecspi1: ecspi@02008000 {
+> +				ecspi1: ecspi at 02008000 {
 > +					#address-cells = <1>;
 > +					#size-cells = <0>;
 > +					compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
@@ -592,7 +592,7 @@ Wrap these two lines to make them a bit shorter.
 > +					status = "disabled";
 > +				};
 > +
-> +				ecspi2: ecspi@0200c000 {
+> +				ecspi2: ecspi at 0200c000 {
 > +					#address-cells = <1>;
 > +					#size-cells = <0>;
 > +					compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
@@ -604,7 +604,7 @@ Wrap these two lines to make them a bit shorter.
 > +					status = "disabled";
 > +				};
 > +
-> +				ecspi3: ecspi@02010000 {
+> +				ecspi3: ecspi at 02010000 {
 > +					#address-cells = <1>;
 > +					#size-cells = <0>;
 > +					compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
@@ -616,7 +616,7 @@ Wrap these two lines to make them a bit shorter.
 > +					status = "disabled";
 > +				};
 > +
-> +				ecspi4: ecspi@02014000 {
+> +				ecspi4: ecspi at 02014000 {
 > +					#address-cells = <1>;
 > +					#size-cells = <0>;
 > +					compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
@@ -628,7 +628,7 @@ Wrap these two lines to make them a bit shorter.
 > +					status = "disabled";
 > +				};
 > +
-> +				uart7: serial@02018000 {
+> +				uart7: serial at 02018000 {
 > +					compatible = "fsl,imx6ul-uart",
 > +						     "fsl,imx6q-uart", "fsl,imx21-uart";
 
@@ -642,7 +642,7 @@ Wrap these two lines to make them a bit shorter.
 > +					status = "disabled";
 > +				};
 > +
-> +				uart1: serial@02020000 {
+> +				uart1: serial at 02020000 {
 > +					compatible = "fsl,imx6ul-uart",
 > +						     "fsl,imx6q-uart", "fsl,imx21-uart";
 > +					reg = <0x02020000 0x4000>;
@@ -653,7 +653,7 @@ Wrap these two lines to make them a bit shorter.
 > +					status = "disabled";
 > +				};
 > +
-> +				uart8: serial@02024000 {
+> +				uart8: serial at 02024000 {
 > +					compatible = "fsl,imx6ul-uart",
 > +						     "fsl,imx6q-uart", "fsl,imx21-uart";
 > +					reg = <0x02024000 0x4000>;
@@ -669,7 +669,7 @@ Wrap these two lines to make them a bit shorter.
 
 One new line is enough.
 
-> +			pwm1: pwm@02080000 {
+> +			pwm1: pwm at 02080000 {
 > +				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 > +				reg = <0x02080000 0x4000>;
 > +				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
@@ -679,7 +679,7 @@ One new line is enough.
 > +				#pwm-cells = <2>;
 > +			};
 > +
-> +			pwm2: pwm@02084000 {
+> +			pwm2: pwm at 02084000 {
 > +				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 > +				reg = <0x02084000 0x4000>;
 > +				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
@@ -692,7 +692,7 @@ Why all other pwm devices except pwm1 are using dummy clock?
 > +				#pwm-cells = <2>;
 > +			};
 > +
-> +			pwm3: pwm@02088000 {
+> +			pwm3: pwm at 02088000 {
 > +				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 > +				reg = <0x02088000 0x4000>;
 > +				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
@@ -702,7 +702,7 @@ Why all other pwm devices except pwm1 are using dummy clock?
 > +				#pwm-cells = <2>;
 > +			};
 > +
-> +			pwm4: pwm@0208c000 {
+> +			pwm4: pwm at 0208c000 {
 > +				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 > +				reg = <0x0208c000 0x4000>;
 > +				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
@@ -712,7 +712,7 @@ Why all other pwm devices except pwm1 are using dummy clock?
 > +				#pwm-cells = <2>;
 > +			};
 > +
-> +			gpt1: gpt@02098000 {
+> +			gpt1: gpt at 02098000 {
 > +				compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
 > +				reg = <0x02098000 0x4000>;
 > +				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
@@ -721,7 +721,7 @@ Why all other pwm devices except pwm1 are using dummy clock?
 > +				clock-names = "ipg", "per";
 > +			};
 > +
-> +			gpio1: gpio@0209c000 {
+> +			gpio1: gpio at 0209c000 {
 > +				compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 > +				reg = <0x0209c000 0x4000>;
 > +				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
@@ -732,7 +732,7 @@ Why all other pwm devices except pwm1 are using dummy clock?
 > +				#interrupt-cells = <2>;
 > +			};
 > +
-> +			gpio2: gpio@020a0000 {
+> +			gpio2: gpio at 020a0000 {
 > +				compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 > +				reg = <0x020a0000 0x4000>;
 > +				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
@@ -743,7 +743,7 @@ Why all other pwm devices except pwm1 are using dummy clock?
 > +				#interrupt-cells = <2>;
 > +			};
 > +
-> +			gpio3: gpio@020a4000 {
+> +			gpio3: gpio at 020a4000 {
 > +				compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 > +				reg = <0x020a4000 0x4000>;
 > +				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
@@ -754,7 +754,7 @@ Why all other pwm devices except pwm1 are using dummy clock?
 > +				#interrupt-cells = <2>;
 > +			};
 > +
-> +			gpio4: gpio@020a8000 {
+> +			gpio4: gpio at 020a8000 {
 > +				compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 > +				reg = <0x020a8000 0x4000>;
 > +				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
@@ -765,7 +765,7 @@ Why all other pwm devices except pwm1 are using dummy clock?
 > +				#interrupt-cells = <2>;
 > +			};
 > +
-> +			gpio5: gpio@020ac000 {
+> +			gpio5: gpio at 020ac000 {
 > +				compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 > +				reg = <0x020ac000 0x4000>;
 > +				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
@@ -776,14 +776,14 @@ Why all other pwm devices except pwm1 are using dummy clock?
 > +				#interrupt-cells = <2>;
 > +			};
 > +
-> +			wdog1: wdog@020bc000 {
+> +			wdog1: wdog at 020bc000 {
 > +				compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 > +				reg = <0x020bc000 0x4000>;
 > +				interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 > +				clocks = <&clks IMX6UL_CLK_WDOG1>;
 > +			};
 > +
-> +			wdog2: wdog@020c0000 {
+> +			wdog2: wdog at 020c0000 {
 > +				compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 > +				reg = <0x020c0000 0x4000>;
 > +				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
@@ -791,7 +791,7 @@ Why all other pwm devices except pwm1 are using dummy clock?
 > +				status = "disabled";
 > +			};
 > +
-> +			clks: ccm@020c4000 {
+> +			clks: ccm at 020c4000 {
 > +				compatible = "fsl,imx6ul-ccm";
 > +				reg = <0x020c4000 0x4000>;
 > +				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
@@ -801,7 +801,7 @@ Why all other pwm devices except pwm1 are using dummy clock?
 > +				clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
 > +			};
 > +
-> +			anatop: anatop@020c8000 {
+> +			anatop: anatop at 020c8000 {
 > +				compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
 > +					     "syscon", "simple-bus";
 > +				reg = <0x020c8000 0x1000>;
@@ -809,7 +809,7 @@ Why all other pwm devices except pwm1 are using dummy clock?
 > +					     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 > +					     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 > +
-> +				reg_3p0: regulator-3p0@120 {
+> +				reg_3p0: regulator-3p0 at 120 {
 > +					compatible = "fsl,anatop-regulator";
 > +					regulator-name = "vdd3p0";
 > +					regulator-min-microvolt = <2625000>;
@@ -823,7 +823,7 @@ Why all other pwm devices except pwm1 are using dummy clock?
 > +					anatop-enable-bit = <0>;
 > +				};
 > +
-> +				reg_arm: regulator-vddcore@140 {
+> +				reg_arm: regulator-vddcore at 140 {
 > +					compatible = "fsl,anatop-regulator";
 > +					regulator-name = "cpu";
 > +					regulator-min-microvolt = <725000>;
@@ -840,7 +840,7 @@ Why all other pwm devices except pwm1 are using dummy clock?
 > +					anatop-max-voltage = <1450000>;
 > +				};
 > +
-> +				reg_soc: regulator-vddsoc@140 {
+> +				reg_soc: regulator-vddsoc at 140 {
 > +					compatible = "fsl,anatop-regulator";
 > +					regulator-name = "vddsoc";
 > +					regulator-min-microvolt = <725000>;
@@ -858,7 +858,7 @@ Why all other pwm devices except pwm1 are using dummy clock?
 > +				};
 > +			};
 > +
-> +			usbphy1: usbphy@020c9000 {
+> +			usbphy1: usbphy at 020c9000 {
 > +				compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
 > +				reg = <0x020c9000 0x1000>;
 > +				interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
@@ -867,7 +867,7 @@ Why all other pwm devices except pwm1 are using dummy clock?
 > +				fsl,anatop = <&anatop>;
 > +			};
 > +
-> +			usbphy2: usbphy@020ca000 {
+> +			usbphy2: usbphy at 020ca000 {
 > +				compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
 > +				reg = <0x020ca000 0x1000>;
 > +				interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
@@ -876,17 +876,17 @@ Why all other pwm devices except pwm1 are using dummy clock?
 > +				fsl,anatop = <&anatop>;
 > +			};
 > +
-> +			epit1: epit@020d0000 {
+> +			epit1: epit at 020d0000 {
 > +				reg = <0x020d0000 0x4000>;
 > +				interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 > +			};
 > +
-> +			epit2: epit@020d4000 {
+> +			epit2: epit at 020d4000 {
 > +				reg = <0x020d4000 0x4000>;
 > +				interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 > +			};
 > +
-> +			src: src@020d8000 {
+> +			src: src at 020d8000 {
 > +				compatible = "fsl,imx6ul-src", "fsl,imx51-src";
 > +				reg = <0x020d8000 0x4000>;
 > +				interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
@@ -894,7 +894,7 @@ Why all other pwm devices except pwm1 are using dummy clock?
 > +				#reset-cells = <1>;
 > +			};
 > +
-> +			gpc: gpc@020dc000 {
+> +			gpc: gpc at 020dc000 {
 > +				compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
 > +				reg = <0x020dc000 0x4000>;
 > +				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
@@ -906,17 +906,17 @@ Shawn
 
 > +			};
 > +
-> +			iomuxc: iomuxc@020e0000 {
+> +			iomuxc: iomuxc at 020e0000 {
 > +				compatible = "fsl,imx6ul-iomuxc";
 > +				reg = <0x020e0000 0x4000>;
 > +			};
 > +
-> +			gpr: iomuxc-gpr@020e4000 {
+> +			gpr: iomuxc-gpr at 020e4000 {
 > +				compatible = "fsl,imx6ul-iomuxc-gpr", "syscon";
 > +				reg = <0x020e4000 0x4000>;
 > +			};
 > +
-> +			gpt2: gpt@020e8000 {
+> +			gpt2: gpt at 020e8000 {
 > +				compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
 > +				reg = <0x020e8000 0x4000>;
 > +				interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
@@ -925,7 +925,7 @@ Shawn
 > +				clock-names = "ipg", "per";
 > +			};
 > +
-> +			pwm5: pwm@020f0000 {
+> +			pwm5: pwm at 020f0000 {
 > +				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 > +				reg = <0x020f0000 0x4000>;
 > +				interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
@@ -935,7 +935,7 @@ Shawn
 > +				#pwm-cells = <2>;
 > +			};
 > +
-> +			pwm6: pwm@020f4000 {
+> +			pwm6: pwm at 020f4000 {
 > +				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 > +				reg = <0x020f4000 0x4000>;
 > +				interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
@@ -945,7 +945,7 @@ Shawn
 > +				#pwm-cells = <2>;
 > +			};
 > +
-> +			pwm7: pwm@020f8000 {
+> +			pwm7: pwm at 020f8000 {
 > +				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 > +				reg = <0x020f8000 0x4000>;
 > +				interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
@@ -955,7 +955,7 @@ Shawn
 > +				#pwm-cells = <2>;
 > +			};
 > +
-> +			pwm8: pwm@020fc000 {
+> +			pwm8: pwm at 020fc000 {
 > +				compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 > +				reg = <0x020fc000 0x4000>;
 > +				interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
@@ -966,14 +966,14 @@ Shawn
 > +			};
 > +		};
 > +
-> +		aips2: aips-bus@02100000 {
+> +		aips2: aips-bus at 02100000 {
 > +			compatible = "fsl,aips-bus", "simple-bus";
 > +			#address-cells = <1>;
 > +			#size-cells = <1>;
 > +			reg = <0x02100000 0x100000>;
 > +			ranges;
 > +
-> +			usdhc1: usdhc@02190000 {
+> +			usdhc1: usdhc at 02190000 {
 > +				compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
 > +				reg = <0x02190000 0x4000>;
 > +				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
@@ -985,7 +985,7 @@ Shawn
 > +				status = "disabled";
 > +			};
 > +
-> +			usdhc2: usdhc@02194000 {
+> +			usdhc2: usdhc at 02194000 {
 > +				compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
 > +				reg = <0x02194000 0x4000>;
 > +				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
@@ -997,7 +997,7 @@ Shawn
 > +				status = "disabled";
 > +			};
 > +
-> +			i2c1: i2c@021a0000 {
+> +			i2c1: i2c at 021a0000 {
 > +				#address-cells = <1>;
 > +				#size-cells = <0>;
 > +				compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
@@ -1007,7 +1007,7 @@ Shawn
 > +				status = "disabled";
 > +			};
 > +
-> +			i2c2: i2c@021a4000 {
+> +			i2c2: i2c at 021a4000 {
 > +				#address-cells = <1>;
 > +				#size-cells = <0>;
 > +				compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
@@ -1017,7 +1017,7 @@ Shawn
 > +				status = "disabled";
 > +			};
 > +
-> +			i2c3: i2c@021a8000 {
+> +			i2c3: i2c at 021a8000 {
 > +				#address-cells = <1>;
 > +				#size-cells = <0>;
 > +				compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
@@ -1027,7 +1027,7 @@ Shawn
 > +				status = "disabled";
 > +			};
 > +
-> +			uart2: serial@021e8000 {
+> +			uart2: serial at 021e8000 {
 > +				compatible = "fsl,imx6ul-uart",
 > +					     "fsl,imx6q-uart", "fsl,imx21-uart";
 > +				reg = <0x021e8000 0x4000>;
@@ -1038,7 +1038,7 @@ Shawn
 > +				status = "disabled";
 > +			};
 > +
-> +			uart3: serial@021ec000 {
+> +			uart3: serial at 021ec000 {
 > +				compatible = "fsl,imx6ul-uart",
 > +					     "fsl,imx6q-uart", "fsl,imx21-uart";
 > +				reg = <0x021ec000 0x4000>;
@@ -1049,7 +1049,7 @@ Shawn
 > +				status = "disabled";
 > +			};
 > +
-> +			uart4: serial@021f0000 {
+> +			uart4: serial at 021f0000 {
 > +				compatible = "fsl,imx6ul-uart",
 > +					     "fsl,imx6q-uart", "fsl,imx21-uart";
 > +				reg = <0x021f0000 0x4000>;
@@ -1060,7 +1060,7 @@ Shawn
 > +				status = "disabled";
 > +			};
 > +
-> +			uart5: serial@021f4000 {
+> +			uart5: serial at 021f4000 {
 > +				compatible = "fsl,imx6ul-uart",
 > +					     "fsl,imx6q-uart", "fsl,imx21-uart";
 > +				reg = <0x021f4000 0x4000>;
@@ -1071,7 +1071,7 @@ Shawn
 > +				status = "disabled";
 > +			};
 > +
-> +			i2c4: i2c@021f8000 {
+> +			i2c4: i2c at 021f8000 {
 > +				#address-cells = <1>;
 > +				#size-cells = <0>;
 > +				compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
@@ -1081,7 +1081,7 @@ Shawn
 > +				status = "disabled";
 > +			};
 > +
-> +			uart6: serial@021fc000 {
+> +			uart6: serial at 021fc000 {
 > +				compatible = "fsl,imx6ul-uart",
 > +					     "fsl,imx6q-uart", "fsl,imx21-uart";
 > +				reg = <0x021fc000 0x4000>;
@@ -1100,6 +1100,6 @@ Shawn
 > 
 > _______________________________________________
 > linux-arm-kernel mailing list
-> linux-arm-kernel@lists.infradead.org
+> linux-arm-kernel at lists.infradead.org
 > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
 >
diff --git a/a/content_digest b/N1/content_digest
index b46e5ae..5e20ed0 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -1,22 +1,12 @@
  "ref\01434555569-8237-1-git-send-email-Frank.Li@freescale.com\0"
  "ref\01434555569-8237-7-git-send-email-Frank.Li@freescale.com\0"
- "From\0Shawn Guo <shawnguo@kernel.org>\0"
- "Subject\0Re: [PATCH 6/8] ARM: dts: imx: add imx6ul and imx6ul evk board support\0"
+ "From\0shawnguo@kernel.org (Shawn Guo)\0"
+ "Subject\0[PATCH 6/8] ARM: dts: imx: add imx6ul and imx6ul evk board support\0"
  "Date\0Thu, 9 Jul 2015 15:02:07 +0800\0"
- "To\0Frank.Li@freescale.com\0"
- "Cc\0linux-arm-kernel@lists.infradead.org"
-  shawn.guo@linaro.org
-  linus.walleij@linaro.org
-  lznuaa@gmail.com
-  devicetree@vger.kernel.org
-  Fancy Fang <chen.fang@freescale.com>
-  linux-gpio@vger.kernel.org
-  robh+dt@kernel.org
-  Fugang Duan <B38611@freescale.com>
- " Anson Huang <b20788@freescale.com>\0"
+ "To\0linux-arm-kernel@lists.infradead.org\0"
  "\00:1\0"
  "b\0"
- "On Wed, Jun 17, 2015 at 11:39:27PM +0800, Frank.Li@freescale.com wrote:\n"
+ "On Wed, Jun 17, 2015 at 11:39:27PM +0800, Frank.Li at freescale.com wrote:\n"
  "> From: Frank Li <Frank.Li@freescale.com>\n"
  "> \n"
  "> Add new SOC i.MX6UL dtb file support, including evk board\n"
@@ -100,7 +90,7 @@
  "> +\t\t#address-cells = <1>;\n"
  "> +\t\t#size-cells = <0>;\n"
  "> +\n"
- "> +\t\treg_sd1_vmmc: regulator@1 {\n"
+ "> +\t\treg_sd1_vmmc: regulator at 1 {\n"
  "\n"
  "There should be a 'reg' property when unit-address is coded in node\n"
  "name.  Also, the numbering starts from 0.\n"
@@ -497,7 +487,7 @@
  "> +\t\t#address-cells = <1>;\n"
  "> +\t\t#size-cells = <0>;\n"
  "> +\n"
- "> +\t\tcpu0: cpu@0 {\n"
+ "> +\t\tcpu0: cpu at 0 {\n"
  "> +\t\t\tcompatible = \"arm,cortex-a7\";\n"
  "> +\t\t\tdevice_type = \"cpu\";\n"
  "> +\t\t\treg = <0>;\n"
@@ -533,7 +523,7 @@
  "> +\t\t};\n"
  "> +\t};\n"
  "> +\n"
- "> +\tintc: interrupt-controller@00a01000 {\n"
+ "> +\tintc: interrupt-controller at 00a01000 {\n"
  "> +\t\tcompatible = \"arm,cortex-a7-gic\";\n"
  "> +\t\t#interrupt-cells = <3>;\n"
  "> +\t\tinterrupt-controller;\n"
@@ -584,21 +574,21 @@
  "> +\t\t\tstatus = \"disabled\";\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\taips1: aips-bus@02000000 {\n"
+ "> +\t\taips1: aips-bus at 02000000 {\n"
  "> +\t\t\tcompatible = \"fsl,aips-bus\", \"simple-bus\";\n"
  "> +\t\t\t#address-cells = <1>;\n"
  "> +\t\t\t#size-cells = <1>;\n"
  "> +\t\t\treg = <0x02000000 0x100000>;\n"
  "> +\t\t\tranges;\n"
  "> +\n"
- "> +\t\t\tspba-bus@02000000 {\n"
+ "> +\t\t\tspba-bus at 02000000 {\n"
  "> +\t\t\t\tcompatible = \"fsl,spba-bus\", \"simple-bus\";\n"
  "> +\t\t\t\t#address-cells = <1>;\n"
  "> +\t\t\t\t#size-cells = <1>;\n"
  "> +\t\t\t\treg = <0x02000000 0x40000>;\n"
  "> +\t\t\t\tranges;\n"
  "> +\n"
- "> +\t\t\t\tecspi1: ecspi@02008000 {\n"
+ "> +\t\t\t\tecspi1: ecspi at 02008000 {\n"
  "> +\t\t\t\t\t#address-cells = <1>;\n"
  "> +\t\t\t\t\t#size-cells = <0>;\n"
  "> +\t\t\t\t\tcompatible = \"fsl,imx6ul-ecspi\", \"fsl,imx51-ecspi\";\n"
@@ -610,7 +600,7 @@
  "> +\t\t\t\t\tstatus = \"disabled\";\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tecspi2: ecspi@0200c000 {\n"
+ "> +\t\t\t\tecspi2: ecspi at 0200c000 {\n"
  "> +\t\t\t\t\t#address-cells = <1>;\n"
  "> +\t\t\t\t\t#size-cells = <0>;\n"
  "> +\t\t\t\t\tcompatible = \"fsl,imx6ul-ecspi\", \"fsl,imx51-ecspi\";\n"
@@ -622,7 +612,7 @@
  "> +\t\t\t\t\tstatus = \"disabled\";\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tecspi3: ecspi@02010000 {\n"
+ "> +\t\t\t\tecspi3: ecspi at 02010000 {\n"
  "> +\t\t\t\t\t#address-cells = <1>;\n"
  "> +\t\t\t\t\t#size-cells = <0>;\n"
  "> +\t\t\t\t\tcompatible = \"fsl,imx6ul-ecspi\", \"fsl,imx51-ecspi\";\n"
@@ -634,7 +624,7 @@
  "> +\t\t\t\t\tstatus = \"disabled\";\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tecspi4: ecspi@02014000 {\n"
+ "> +\t\t\t\tecspi4: ecspi at 02014000 {\n"
  "> +\t\t\t\t\t#address-cells = <1>;\n"
  "> +\t\t\t\t\t#size-cells = <0>;\n"
  "> +\t\t\t\t\tcompatible = \"fsl,imx6ul-ecspi\", \"fsl,imx51-ecspi\";\n"
@@ -646,7 +636,7 @@
  "> +\t\t\t\t\tstatus = \"disabled\";\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tuart7: serial@02018000 {\n"
+ "> +\t\t\t\tuart7: serial at 02018000 {\n"
  "> +\t\t\t\t\tcompatible = \"fsl,imx6ul-uart\",\n"
  "> +\t\t\t\t\t\t     \"fsl,imx6q-uart\", \"fsl,imx21-uart\";\n"
  "\n"
@@ -660,7 +650,7 @@
  "> +\t\t\t\t\tstatus = \"disabled\";\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tuart1: serial@02020000 {\n"
+ "> +\t\t\t\tuart1: serial at 02020000 {\n"
  "> +\t\t\t\t\tcompatible = \"fsl,imx6ul-uart\",\n"
  "> +\t\t\t\t\t\t     \"fsl,imx6q-uart\", \"fsl,imx21-uart\";\n"
  "> +\t\t\t\t\treg = <0x02020000 0x4000>;\n"
@@ -671,7 +661,7 @@
  "> +\t\t\t\t\tstatus = \"disabled\";\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\tuart8: serial@02024000 {\n"
+ "> +\t\t\t\tuart8: serial at 02024000 {\n"
  "> +\t\t\t\t\tcompatible = \"fsl,imx6ul-uart\",\n"
  "> +\t\t\t\t\t\t     \"fsl,imx6q-uart\", \"fsl,imx21-uart\";\n"
  "> +\t\t\t\t\treg = <0x02024000 0x4000>;\n"
@@ -687,7 +677,7 @@
  "\n"
  "One new line is enough.\n"
  "\n"
- "> +\t\t\tpwm1: pwm@02080000 {\n"
+ "> +\t\t\tpwm1: pwm at 02080000 {\n"
  "> +\t\t\t\tcompatible = \"fsl,imx6ul-pwm\", \"fsl,imx27-pwm\";\n"
  "> +\t\t\t\treg = <0x02080000 0x4000>;\n"
  "> +\t\t\t\tinterrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -697,7 +687,7 @@
  "> +\t\t\t\t#pwm-cells = <2>;\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tpwm2: pwm@02084000 {\n"
+ "> +\t\t\tpwm2: pwm at 02084000 {\n"
  "> +\t\t\t\tcompatible = \"fsl,imx6ul-pwm\", \"fsl,imx27-pwm\";\n"
  "> +\t\t\t\treg = <0x02084000 0x4000>;\n"
  "> +\t\t\t\tinterrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -710,7 +700,7 @@
  "> +\t\t\t\t#pwm-cells = <2>;\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tpwm3: pwm@02088000 {\n"
+ "> +\t\t\tpwm3: pwm at 02088000 {\n"
  "> +\t\t\t\tcompatible = \"fsl,imx6ul-pwm\", \"fsl,imx27-pwm\";\n"
  "> +\t\t\t\treg = <0x02088000 0x4000>;\n"
  "> +\t\t\t\tinterrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -720,7 +710,7 @@
  "> +\t\t\t\t#pwm-cells = <2>;\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tpwm4: pwm@0208c000 {\n"
+ "> +\t\t\tpwm4: pwm at 0208c000 {\n"
  "> +\t\t\t\tcompatible = \"fsl,imx6ul-pwm\", \"fsl,imx27-pwm\";\n"
  "> +\t\t\t\treg = <0x0208c000 0x4000>;\n"
  "> +\t\t\t\tinterrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -730,7 +720,7 @@
  "> +\t\t\t\t#pwm-cells = <2>;\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tgpt1: gpt@02098000 {\n"
+ "> +\t\t\tgpt1: gpt at 02098000 {\n"
  "> +\t\t\t\tcompatible = \"fsl,imx6ul-gpt\", \"fsl,imx6sx-gpt\";\n"
  "> +\t\t\t\treg = <0x02098000 0x4000>;\n"
  "> +\t\t\t\tinterrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -739,7 +729,7 @@
  "> +\t\t\t\tclock-names = \"ipg\", \"per\";\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tgpio1: gpio@0209c000 {\n"
+ "> +\t\t\tgpio1: gpio at 0209c000 {\n"
  "> +\t\t\t\tcompatible = \"fsl,imx6ul-gpio\", \"fsl,imx35-gpio\";\n"
  "> +\t\t\t\treg = <0x0209c000 0x4000>;\n"
  "> +\t\t\t\tinterrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,\n"
@@ -750,7 +740,7 @@
  "> +\t\t\t\t#interrupt-cells = <2>;\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tgpio2: gpio@020a0000 {\n"
+ "> +\t\t\tgpio2: gpio at 020a0000 {\n"
  "> +\t\t\t\tcompatible = \"fsl,imx6ul-gpio\", \"fsl,imx35-gpio\";\n"
  "> +\t\t\t\treg = <0x020a0000 0x4000>;\n"
  "> +\t\t\t\tinterrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,\n"
@@ -761,7 +751,7 @@
  "> +\t\t\t\t#interrupt-cells = <2>;\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tgpio3: gpio@020a4000 {\n"
+ "> +\t\t\tgpio3: gpio at 020a4000 {\n"
  "> +\t\t\t\tcompatible = \"fsl,imx6ul-gpio\", \"fsl,imx35-gpio\";\n"
  "> +\t\t\t\treg = <0x020a4000 0x4000>;\n"
  "> +\t\t\t\tinterrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,\n"
@@ -772,7 +762,7 @@
  "> +\t\t\t\t#interrupt-cells = <2>;\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tgpio4: gpio@020a8000 {\n"
+ "> +\t\t\tgpio4: gpio at 020a8000 {\n"
  "> +\t\t\t\tcompatible = \"fsl,imx6ul-gpio\", \"fsl,imx35-gpio\";\n"
  "> +\t\t\t\treg = <0x020a8000 0x4000>;\n"
  "> +\t\t\t\tinterrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,\n"
@@ -783,7 +773,7 @@
  "> +\t\t\t\t#interrupt-cells = <2>;\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tgpio5: gpio@020ac000 {\n"
+ "> +\t\t\tgpio5: gpio at 020ac000 {\n"
  "> +\t\t\t\tcompatible = \"fsl,imx6ul-gpio\", \"fsl,imx35-gpio\";\n"
  "> +\t\t\t\treg = <0x020ac000 0x4000>;\n"
  "> +\t\t\t\tinterrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,\n"
@@ -794,14 +784,14 @@
  "> +\t\t\t\t#interrupt-cells = <2>;\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\twdog1: wdog@020bc000 {\n"
+ "> +\t\t\twdog1: wdog at 020bc000 {\n"
  "> +\t\t\t\tcompatible = \"fsl,imx6ul-wdt\", \"fsl,imx21-wdt\";\n"
  "> +\t\t\t\treg = <0x020bc000 0x4000>;\n"
  "> +\t\t\t\tinterrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;\n"
  "> +\t\t\t\tclocks = <&clks IMX6UL_CLK_WDOG1>;\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\twdog2: wdog@020c0000 {\n"
+ "> +\t\t\twdog2: wdog at 020c0000 {\n"
  "> +\t\t\t\tcompatible = \"fsl,imx6ul-wdt\", \"fsl,imx21-wdt\";\n"
  "> +\t\t\t\treg = <0x020c0000 0x4000>;\n"
  "> +\t\t\t\tinterrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -809,7 +799,7 @@
  "> +\t\t\t\tstatus = \"disabled\";\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tclks: ccm@020c4000 {\n"
+ "> +\t\t\tclks: ccm at 020c4000 {\n"
  "> +\t\t\t\tcompatible = \"fsl,imx6ul-ccm\";\n"
  "> +\t\t\t\treg = <0x020c4000 0x4000>;\n"
  "> +\t\t\t\tinterrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,\n"
@@ -819,7 +809,7 @@
  "> +\t\t\t\tclock-names = \"ckil\", \"osc\", \"ipp_di0\", \"ipp_di1\";\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tanatop: anatop@020c8000 {\n"
+ "> +\t\t\tanatop: anatop at 020c8000 {\n"
  "> +\t\t\t\tcompatible = \"fsl,imx6ul-anatop\", \"fsl,imx6q-anatop\",\n"
  "> +\t\t\t\t\t     \"syscon\", \"simple-bus\";\n"
  "> +\t\t\t\treg = <0x020c8000 0x1000>;\n"
@@ -827,7 +817,7 @@
  "> +\t\t\t\t\t     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,\n"
  "> +\t\t\t\t\t     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;\n"
  "> +\n"
- "> +\t\t\t\treg_3p0: regulator-3p0@120 {\n"
+ "> +\t\t\t\treg_3p0: regulator-3p0 at 120 {\n"
  "> +\t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n"
  "> +\t\t\t\t\tregulator-name = \"vdd3p0\";\n"
  "> +\t\t\t\t\tregulator-min-microvolt = <2625000>;\n"
@@ -841,7 +831,7 @@
  "> +\t\t\t\t\tanatop-enable-bit = <0>;\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\treg_arm: regulator-vddcore@140 {\n"
+ "> +\t\t\t\treg_arm: regulator-vddcore at 140 {\n"
  "> +\t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n"
  "> +\t\t\t\t\tregulator-name = \"cpu\";\n"
  "> +\t\t\t\t\tregulator-min-microvolt = <725000>;\n"
@@ -858,7 +848,7 @@
  "> +\t\t\t\t\tanatop-max-voltage = <1450000>;\n"
  "> +\t\t\t\t};\n"
  "> +\n"
- "> +\t\t\t\treg_soc: regulator-vddsoc@140 {\n"
+ "> +\t\t\t\treg_soc: regulator-vddsoc at 140 {\n"
  "> +\t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n"
  "> +\t\t\t\t\tregulator-name = \"vddsoc\";\n"
  "> +\t\t\t\t\tregulator-min-microvolt = <725000>;\n"
@@ -876,7 +866,7 @@
  "> +\t\t\t\t};\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tusbphy1: usbphy@020c9000 {\n"
+ "> +\t\t\tusbphy1: usbphy at 020c9000 {\n"
  "> +\t\t\t\tcompatible = \"fsl,imx6ul-usbphy\", \"fsl,imx23-usbphy\";\n"
  "> +\t\t\t\treg = <0x020c9000 0x1000>;\n"
  "> +\t\t\t\tinterrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -885,7 +875,7 @@
  "> +\t\t\t\tfsl,anatop = <&anatop>;\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tusbphy2: usbphy@020ca000 {\n"
+ "> +\t\t\tusbphy2: usbphy at 020ca000 {\n"
  "> +\t\t\t\tcompatible = \"fsl,imx6ul-usbphy\", \"fsl,imx23-usbphy\";\n"
  "> +\t\t\t\treg = <0x020ca000 0x1000>;\n"
  "> +\t\t\t\tinterrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -894,17 +884,17 @@
  "> +\t\t\t\tfsl,anatop = <&anatop>;\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tepit1: epit@020d0000 {\n"
+ "> +\t\t\tepit1: epit at 020d0000 {\n"
  "> +\t\t\t\treg = <0x020d0000 0x4000>;\n"
  "> +\t\t\t\tinterrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tepit2: epit@020d4000 {\n"
+ "> +\t\t\tepit2: epit at 020d4000 {\n"
  "> +\t\t\t\treg = <0x020d4000 0x4000>;\n"
  "> +\t\t\t\tinterrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tsrc: src@020d8000 {\n"
+ "> +\t\t\tsrc: src at 020d8000 {\n"
  "> +\t\t\t\tcompatible = \"fsl,imx6ul-src\", \"fsl,imx51-src\";\n"
  "> +\t\t\t\treg = <0x020d8000 0x4000>;\n"
  "> +\t\t\t\tinterrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,\n"
@@ -912,7 +902,7 @@
  "> +\t\t\t\t#reset-cells = <1>;\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tgpc: gpc@020dc000 {\n"
+ "> +\t\t\tgpc: gpc at 020dc000 {\n"
  "> +\t\t\t\tcompatible = \"fsl,imx6ul-gpc\", \"fsl,imx6q-gpc\";\n"
  "> +\t\t\t\treg = <0x020dc000 0x4000>;\n"
  "> +\t\t\t\tinterrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -924,17 +914,17 @@
  "\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tiomuxc: iomuxc@020e0000 {\n"
+ "> +\t\t\tiomuxc: iomuxc at 020e0000 {\n"
  "> +\t\t\t\tcompatible = \"fsl,imx6ul-iomuxc\";\n"
  "> +\t\t\t\treg = <0x020e0000 0x4000>;\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tgpr: iomuxc-gpr@020e4000 {\n"
+ "> +\t\t\tgpr: iomuxc-gpr at 020e4000 {\n"
  "> +\t\t\t\tcompatible = \"fsl,imx6ul-iomuxc-gpr\", \"syscon\";\n"
  "> +\t\t\t\treg = <0x020e4000 0x4000>;\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tgpt2: gpt@020e8000 {\n"
+ "> +\t\t\tgpt2: gpt at 020e8000 {\n"
  "> +\t\t\t\tcompatible = \"fsl,imx6ul-gpt\", \"fsl,imx6sx-gpt\";\n"
  "> +\t\t\t\treg = <0x020e8000 0x4000>;\n"
  "> +\t\t\t\tinterrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -943,7 +933,7 @@
  "> +\t\t\t\tclock-names = \"ipg\", \"per\";\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tpwm5: pwm@020f0000 {\n"
+ "> +\t\t\tpwm5: pwm at 020f0000 {\n"
  "> +\t\t\t\tcompatible = \"fsl,imx6ul-pwm\", \"fsl,imx27-pwm\";\n"
  "> +\t\t\t\treg = <0x020f0000 0x4000>;\n"
  "> +\t\t\t\tinterrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -953,7 +943,7 @@
  "> +\t\t\t\t#pwm-cells = <2>;\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tpwm6: pwm@020f4000 {\n"
+ "> +\t\t\tpwm6: pwm at 020f4000 {\n"
  "> +\t\t\t\tcompatible = \"fsl,imx6ul-pwm\", \"fsl,imx27-pwm\";\n"
  "> +\t\t\t\treg = <0x020f4000 0x4000>;\n"
  "> +\t\t\t\tinterrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -963,7 +953,7 @@
  "> +\t\t\t\t#pwm-cells = <2>;\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tpwm7: pwm@020f8000 {\n"
+ "> +\t\t\tpwm7: pwm at 020f8000 {\n"
  "> +\t\t\t\tcompatible = \"fsl,imx6ul-pwm\", \"fsl,imx27-pwm\";\n"
  "> +\t\t\t\treg = <0x020f8000 0x4000>;\n"
  "> +\t\t\t\tinterrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -973,7 +963,7 @@
  "> +\t\t\t\t#pwm-cells = <2>;\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tpwm8: pwm@020fc000 {\n"
+ "> +\t\t\tpwm8: pwm at 020fc000 {\n"
  "> +\t\t\t\tcompatible = \"fsl,imx6ul-pwm\", \"fsl,imx27-pwm\";\n"
  "> +\t\t\t\treg = <0x020fc000 0x4000>;\n"
  "> +\t\t\t\tinterrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -984,14 +974,14 @@
  "> +\t\t\t};\n"
  "> +\t\t};\n"
  "> +\n"
- "> +\t\taips2: aips-bus@02100000 {\n"
+ "> +\t\taips2: aips-bus at 02100000 {\n"
  "> +\t\t\tcompatible = \"fsl,aips-bus\", \"simple-bus\";\n"
  "> +\t\t\t#address-cells = <1>;\n"
  "> +\t\t\t#size-cells = <1>;\n"
  "> +\t\t\treg = <0x02100000 0x100000>;\n"
  "> +\t\t\tranges;\n"
  "> +\n"
- "> +\t\t\tusdhc1: usdhc@02190000 {\n"
+ "> +\t\t\tusdhc1: usdhc at 02190000 {\n"
  "> +\t\t\t\tcompatible = \"fsl,imx6ul-usdhc\", \"fsl,imx6sx-usdhc\";\n"
  "> +\t\t\t\treg = <0x02190000 0x4000>;\n"
  "> +\t\t\t\tinterrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -1003,7 +993,7 @@
  "> +\t\t\t\tstatus = \"disabled\";\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tusdhc2: usdhc@02194000 {\n"
+ "> +\t\t\tusdhc2: usdhc at 02194000 {\n"
  "> +\t\t\t\tcompatible = \"fsl,imx6ul-usdhc\", \"fsl,imx6sx-usdhc\";\n"
  "> +\t\t\t\treg = <0x02194000 0x4000>;\n"
  "> +\t\t\t\tinterrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -1015,7 +1005,7 @@
  "> +\t\t\t\tstatus = \"disabled\";\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\ti2c1: i2c@021a0000 {\n"
+ "> +\t\t\ti2c1: i2c at 021a0000 {\n"
  "> +\t\t\t\t#address-cells = <1>;\n"
  "> +\t\t\t\t#size-cells = <0>;\n"
  "> +\t\t\t\tcompatible = \"fsl,imx6ul-i2c\", \"fsl,imx21-i2c\";\n"
@@ -1025,7 +1015,7 @@
  "> +\t\t\t\tstatus = \"disabled\";\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\ti2c2: i2c@021a4000 {\n"
+ "> +\t\t\ti2c2: i2c at 021a4000 {\n"
  "> +\t\t\t\t#address-cells = <1>;\n"
  "> +\t\t\t\t#size-cells = <0>;\n"
  "> +\t\t\t\tcompatible = \"fsl,imx6ul-i2c\", \"fsl,imx21-i2c\";\n"
@@ -1035,7 +1025,7 @@
  "> +\t\t\t\tstatus = \"disabled\";\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\ti2c3: i2c@021a8000 {\n"
+ "> +\t\t\ti2c3: i2c at 021a8000 {\n"
  "> +\t\t\t\t#address-cells = <1>;\n"
  "> +\t\t\t\t#size-cells = <0>;\n"
  "> +\t\t\t\tcompatible = \"fsl,imx6ul-i2c\", \"fsl,imx21-i2c\";\n"
@@ -1045,7 +1035,7 @@
  "> +\t\t\t\tstatus = \"disabled\";\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tuart2: serial@021e8000 {\n"
+ "> +\t\t\tuart2: serial at 021e8000 {\n"
  "> +\t\t\t\tcompatible = \"fsl,imx6ul-uart\",\n"
  "> +\t\t\t\t\t     \"fsl,imx6q-uart\", \"fsl,imx21-uart\";\n"
  "> +\t\t\t\treg = <0x021e8000 0x4000>;\n"
@@ -1056,7 +1046,7 @@
  "> +\t\t\t\tstatus = \"disabled\";\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tuart3: serial@021ec000 {\n"
+ "> +\t\t\tuart3: serial at 021ec000 {\n"
  "> +\t\t\t\tcompatible = \"fsl,imx6ul-uart\",\n"
  "> +\t\t\t\t\t     \"fsl,imx6q-uart\", \"fsl,imx21-uart\";\n"
  "> +\t\t\t\treg = <0x021ec000 0x4000>;\n"
@@ -1067,7 +1057,7 @@
  "> +\t\t\t\tstatus = \"disabled\";\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tuart4: serial@021f0000 {\n"
+ "> +\t\t\tuart4: serial at 021f0000 {\n"
  "> +\t\t\t\tcompatible = \"fsl,imx6ul-uart\",\n"
  "> +\t\t\t\t\t     \"fsl,imx6q-uart\", \"fsl,imx21-uart\";\n"
  "> +\t\t\t\treg = <0x021f0000 0x4000>;\n"
@@ -1078,7 +1068,7 @@
  "> +\t\t\t\tstatus = \"disabled\";\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tuart5: serial@021f4000 {\n"
+ "> +\t\t\tuart5: serial at 021f4000 {\n"
  "> +\t\t\t\tcompatible = \"fsl,imx6ul-uart\",\n"
  "> +\t\t\t\t\t     \"fsl,imx6q-uart\", \"fsl,imx21-uart\";\n"
  "> +\t\t\t\treg = <0x021f4000 0x4000>;\n"
@@ -1089,7 +1079,7 @@
  "> +\t\t\t\tstatus = \"disabled\";\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\ti2c4: i2c@021f8000 {\n"
+ "> +\t\t\ti2c4: i2c at 021f8000 {\n"
  "> +\t\t\t\t#address-cells = <1>;\n"
  "> +\t\t\t\t#size-cells = <0>;\n"
  "> +\t\t\t\tcompatible = \"fsl,imx6ul-i2c\", \"fsl,imx21-i2c\";\n"
@@ -1099,7 +1089,7 @@
  "> +\t\t\t\tstatus = \"disabled\";\n"
  "> +\t\t\t};\n"
  "> +\n"
- "> +\t\t\tuart6: serial@021fc000 {\n"
+ "> +\t\t\tuart6: serial at 021fc000 {\n"
  "> +\t\t\t\tcompatible = \"fsl,imx6ul-uart\",\n"
  "> +\t\t\t\t\t     \"fsl,imx6q-uart\", \"fsl,imx21-uart\";\n"
  "> +\t\t\t\treg = <0x021fc000 0x4000>;\n"
@@ -1118,8 +1108,8 @@
  "> \n"
  "> _______________________________________________\n"
  "> linux-arm-kernel mailing list\n"
- "> linux-arm-kernel@lists.infradead.org\n"
+ "> linux-arm-kernel at lists.infradead.org\n"
  "> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel\n"
  >
 
-31f157a5bf776981e7fd90ea74e94d20ecb3917318ff22af482f4317462f0e89
+277b8f9ecb314a387ff2fc42a7609b4a263c54c19334feb9ac92ae395ec69b29
