diff for duplicates of <20150722164737.2824053e@xhacker> diff --git a/a/1.txt b/N1/1.txt index 0155e74..f76b985 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -193,28 +193,28 @@ Jisheng > + #address-cells = <1>; > + #size-cells = <0>; > + -> + cpu0: cpu at 0 { +> + cpu0: cpu@0 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0>; > + enable-method = "psci"; > + }; > + -> + cpu1: cpu at 1 { +> + cpu1: cpu@1 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <0x1>; > + enable-method = "psci"; > + }; > + -> + cpu2: cpu at 2 { +> + cpu2: cpu@2 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <0x2>; > + enable-method = "psci"; > + }; > + -> + cpu3: cpu at 3 { +> + cpu3: cpu@3 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <0x3>; @@ -254,7 +254,7 @@ Jisheng > + clock-frequency = <25000000>; > + }; > + -> + gic: interrupt-controller at 901000 { +> + gic: interrupt-controller@901000 { > + compatible = "arm,gic-400"; > + #interrupt-cells = <3>; > + interrupt-controller; @@ -265,14 +265,14 @@ Jisheng > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > + }; > + -> + apb at fc0000 { +> + apb@fc0000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0xfc0000 0x10000>; > + interrupt-parent = <&sic>; > + -> + sic: interrupt-controller at 1000 { +> + sic: interrupt-controller@1000 { > + compatible = "snps,dw-apb-ictl"; > + reg = <0x1000 0x30>; > + interrupt-controller; @@ -281,7 +281,7 @@ Jisheng > + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; > + }; > + -> + uart0: uart at d000 { +> + uart0: uart@d000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0xd000 0x100>; > + interrupts = <8>; diff --git a/a/content_digest b/N1/content_digest index 351753e..566ac76 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,9 +1,21 @@ "ref\01437554657-5367-1-git-send-email-jszhang@marvell.com\0" "ref\01437554657-5367-2-git-send-email-jszhang@marvell.com\0" - "From\0jszhang@marvell.com (Jisheng Zhang)\0" - "Subject\0[PATCH v2 1/2] arm64: dts: Add dts files for Marvell Berlin4CT SoC\0" + "From\0Jisheng Zhang <jszhang@marvell.com>\0" + "Subject\0Re: [PATCH v2 1/2] arm64: dts: Add dts files for Marvell Berlin4CT SoC\0" "Date\0Wed, 22 Jul 2015 16:47:37 +0800\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0catalin.marinas@arm.com" + will.deacon@arm.com + khilman@linaro.org + arnd@arndb.de + olof@lixom.net + mark.rutland@arm.com + sudeep.holla@arm.com + robh+dt@kernel.org + galak@codeaurora.org + " pawel.moll@arm.com\0" + "Cc\0linux-arm-kernel@lists.infradead.org" + linux-kernel@vger.kernel.org + " devicetree@vger.kernel.org\0" "\00:1\0" "b\0" "On Wed, 22 Jul 2015 16:44:16 +0800\n" @@ -201,28 +213,28 @@ "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\tcpu0: cpu at 0 {\n" + "> +\t\tcpu0: cpu@0 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu1: cpu at 1 {\n" + "> +\t\tcpu1: cpu@1 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x1>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu2: cpu at 2 {\n" + "> +\t\tcpu2: cpu@2 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x2>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu3: cpu at 3 {\n" + "> +\t\tcpu3: cpu@3 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x3>;\n" @@ -262,7 +274,7 @@ "> +\t\t\tclock-frequency = <25000000>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tgic: interrupt-controller at 901000 {\n" + "> +\t\tgic: interrupt-controller@901000 {\n" "> +\t\t\tcompatible = \"arm,gic-400\";\n" "> +\t\t\t#interrupt-cells = <3>;\n" "> +\t\t\tinterrupt-controller;\n" @@ -273,14 +285,14 @@ "> +\t\t\tinterrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb at fc0000 {\n" + "> +\t\tapb@fc0000 {\n" "> +\t\t\tcompatible = \"simple-bus\";\n" "> +\t\t\t#address-cells = <1>;\n" "> +\t\t\t#size-cells = <1>;\n" "> +\t\t\tranges = <0 0xfc0000 0x10000>;\n" "> +\t\t\tinterrupt-parent = <&sic>;\n" "> +\n" - "> +\t\t\tsic: interrupt-controller at 1000 {\n" + "> +\t\t\tsic: interrupt-controller@1000 {\n" "> +\t\t\t\tcompatible = \"snps,dw-apb-ictl\";\n" "> +\t\t\t\treg = <0x1000 0x30>;\n" "> +\t\t\t\tinterrupt-controller;\n" @@ -289,7 +301,7 @@ "> +\t\t\t\tinterrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart0: uart at d000 {\n" + "> +\t\t\tuart0: uart@d000 {\n" "> +\t\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\t\treg = <0xd000 0x100>;\n" "> +\t\t\t\tinterrupts = <8>;\n" @@ -301,4 +313,4 @@ "> +\t};\n" > +}; -1b6f8f87b75dc5a5398c2653b84257b80cb1f6c8652fc7900898686641fbf288 +5d8c2e263ca3100325916ed890ddefdb4ad5b1c3b2b71493ca4fe33867316995
diff --git a/a/1.txt b/N2/1.txt index 0155e74..f76b985 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -193,28 +193,28 @@ Jisheng > + #address-cells = <1>; > + #size-cells = <0>; > + -> + cpu0: cpu at 0 { +> + cpu0: cpu@0 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <0x0>; > + enable-method = "psci"; > + }; > + -> + cpu1: cpu at 1 { +> + cpu1: cpu@1 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <0x1>; > + enable-method = "psci"; > + }; > + -> + cpu2: cpu at 2 { +> + cpu2: cpu@2 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <0x2>; > + enable-method = "psci"; > + }; > + -> + cpu3: cpu at 3 { +> + cpu3: cpu@3 { > + compatible = "arm,cortex-a53", "arm,armv8"; > + device_type = "cpu"; > + reg = <0x3>; @@ -254,7 +254,7 @@ Jisheng > + clock-frequency = <25000000>; > + }; > + -> + gic: interrupt-controller at 901000 { +> + gic: interrupt-controller@901000 { > + compatible = "arm,gic-400"; > + #interrupt-cells = <3>; > + interrupt-controller; @@ -265,14 +265,14 @@ Jisheng > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > + }; > + -> + apb at fc0000 { +> + apb@fc0000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0xfc0000 0x10000>; > + interrupt-parent = <&sic>; > + -> + sic: interrupt-controller at 1000 { +> + sic: interrupt-controller@1000 { > + compatible = "snps,dw-apb-ictl"; > + reg = <0x1000 0x30>; > + interrupt-controller; @@ -281,7 +281,7 @@ Jisheng > + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; > + }; > + -> + uart0: uart at d000 { +> + uart0: uart@d000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0xd000 0x100>; > + interrupts = <8>; diff --git a/a/content_digest b/N2/content_digest index 351753e..e2f0253 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,9 +1,21 @@ "ref\01437554657-5367-1-git-send-email-jszhang@marvell.com\0" "ref\01437554657-5367-2-git-send-email-jszhang@marvell.com\0" - "From\0jszhang@marvell.com (Jisheng Zhang)\0" - "Subject\0[PATCH v2 1/2] arm64: dts: Add dts files for Marvell Berlin4CT SoC\0" + "From\0Jisheng Zhang <jszhang@marvell.com>\0" + "Subject\0Re: [PATCH v2 1/2] arm64: dts: Add dts files for Marvell Berlin4CT SoC\0" "Date\0Wed, 22 Jul 2015 16:47:37 +0800\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0<catalin.marinas@arm.com>" + <will.deacon@arm.com> + <khilman@linaro.org> + <arnd@arndb.de> + <olof@lixom.net> + <mark.rutland@arm.com> + <sudeep.holla@arm.com> + <robh+dt@kernel.org> + <galak@codeaurora.org> + " <pawel.moll@arm.com>\0" + "Cc\0<linux-arm-kernel@lists.infradead.org>" + <linux-kernel@vger.kernel.org> + " <devicetree@vger.kernel.org>\0" "\00:1\0" "b\0" "On Wed, 22 Jul 2015 16:44:16 +0800\n" @@ -201,28 +213,28 @@ "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\tcpu0: cpu at 0 {\n" + "> +\t\tcpu0: cpu@0 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x0>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu1: cpu at 1 {\n" + "> +\t\tcpu1: cpu@1 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x1>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu2: cpu at 2 {\n" + "> +\t\tcpu2: cpu@2 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x2>;\n" "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu3: cpu at 3 {\n" + "> +\t\tcpu3: cpu@3 {\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0x3>;\n" @@ -262,7 +274,7 @@ "> +\t\t\tclock-frequency = <25000000>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tgic: interrupt-controller at 901000 {\n" + "> +\t\tgic: interrupt-controller@901000 {\n" "> +\t\t\tcompatible = \"arm,gic-400\";\n" "> +\t\t\t#interrupt-cells = <3>;\n" "> +\t\t\tinterrupt-controller;\n" @@ -273,14 +285,14 @@ "> +\t\t\tinterrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb at fc0000 {\n" + "> +\t\tapb@fc0000 {\n" "> +\t\t\tcompatible = \"simple-bus\";\n" "> +\t\t\t#address-cells = <1>;\n" "> +\t\t\t#size-cells = <1>;\n" "> +\t\t\tranges = <0 0xfc0000 0x10000>;\n" "> +\t\t\tinterrupt-parent = <&sic>;\n" "> +\n" - "> +\t\t\tsic: interrupt-controller at 1000 {\n" + "> +\t\t\tsic: interrupt-controller@1000 {\n" "> +\t\t\t\tcompatible = \"snps,dw-apb-ictl\";\n" "> +\t\t\t\treg = <0x1000 0x30>;\n" "> +\t\t\t\tinterrupt-controller;\n" @@ -289,7 +301,7 @@ "> +\t\t\t\tinterrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart0: uart at d000 {\n" + "> +\t\t\tuart0: uart@d000 {\n" "> +\t\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\t\treg = <0xd000 0x100>;\n" "> +\t\t\t\tinterrupts = <8>;\n" @@ -301,4 +313,4 @@ "> +\t};\n" > +}; -1b6f8f87b75dc5a5398c2653b84257b80cb1f6c8652fc7900898686641fbf288 +79e15aad2b3da311142cd70e6152c053f6ddfd2f7ded8292f2b18f2c53f801a9
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