From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58166) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZIGrO-0003vN-Hq for qemu-devel@nongnu.org; Thu, 23 Jul 2015 09:48:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZIGrK-0005z0-DZ for qemu-devel@nongnu.org; Thu, 23 Jul 2015 09:48:30 -0400 Received: from mx1.redhat.com ([209.132.183.28]:36542) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZIGrK-0005yA-8s for qemu-devel@nongnu.org; Thu, 23 Jul 2015 09:48:26 -0400 Date: Thu, 23 Jul 2015 15:48:19 +0200 From: Marc =?UTF-8?B?TWFyw60=?= Message-ID: <20150723154819.39ad7501@markmb_rh> In-Reply-To: <55B0EFF5.1050608@redhat.com> References: <1437494626-3773-1-git-send-email-markmb@redhat.com> <1437494626-3773-3-git-send-email-markmb@redhat.com> <20150722042434.GB27877@morn.localdomain> <20150722103112.1d97386b@markmb_rh> <20150722171804.GA2717@morn.localdomain> <55B0E86E.2030209@redhat.com> <55B0EFF5.1050608@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [RFC 2/7] fw_cfg dma interface List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Laszlo Ersek Cc: Peter Maydell , Stefan Hajnoczi , "Richard W.M. Jones" , QEMU Developers , Kevin O'Connor , Gerd Hoffmann , Paolo Bonzini On Thu, 23 Jul 2015 15:45:25 +0200 Laszlo Ersek wrote: > On 07/23/15 15:35, Peter Maydell wrote: > > On 23 July 2015 at 14:13, Laszlo Ersek wrote: > >> On 07/22/15 19:18, Kevin O'Connor wrote: > >>> Another possibility would be to place the new fw_cfg dma register > >>> address into a named fw_cfg "file" (eg, "fw_cfg_dma"). The > >>> firmware could then use the existing select/data fw_cfg interface > >>> to check if the new dma interface is available by scanning for > >>> that "fw_cfg_dma" file. This has the advantage of not requiring > >>> a new "magic address", but has the disadvantage of a more complex > >>> probe. > >> > >> I like this one so much that I'm worried I'm missing some > >> details. :) > > > > This requires the device itself to know its own address, which > > is in QEMU possible but ugly enough to be worth avoiding. > > > > For ARM MMIO the obvious answer is "the new register should > > just go next to the first one". Does x86 do something that > > means we can't put it somewhere equally straightforward > > or do discovery via whatever x86 uses for discovering MMIO? > > I don't know how x86 determines the MMIO mapping. As far as I gather > from the SeaBIOS patches and this QEMU series, 0xfef00000 is a > hand-picked fixed address. (See BIOS_CFG_DMA_ADDR in 7/7.) > > 0xfef00000 seems to fall right above the 1MB LAPIC range; I guess > there's no conflict with anything else... > For the x86 part, I chose a completely arbitrary "magic address". Ideally, this address should be discoverable by the BIOS, so it can be moved around if some specification is changed. But a lot of device configuration used in SeaBIOS comes from fw_cfg. That might be the reason why the IO port was also hardcoded. It would be good if somebody comes with an idea on how to make it discoverable by the BIOS in x86.