From mboxrd@z Thu Jan 1 00:00:00 1970 From: Will Deacon Subject: Re: [PATCH v3 5/6] iommu/mediatek: Add mt8173 IOMMU driver Date: Fri, 24 Jul 2015 17:55:10 +0100 Message-ID: <20150724165509.GD21177@arm.com> References: <1437037475-9065-1-git-send-email-yong.wu@mediatek.com> <1437037475-9065-6-git-send-email-yong.wu@mediatek.com> <20150721145910.GG31095@arm.com> <1437716593.23932.73.camel@mhfsdcap03> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <1437716593.23932.73.camel@mhfsdcap03> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Yong Wu Cc: Mark Rutland , Catalin Marinas , "cloud.chou-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org" , "frederic.chen-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org" , "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "arnd-r2nGTMty4D4@public.gmane.org" , Tomasz Figa , Rob Herring , "linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" , Matthias Brugger , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" , "pebolle-IWqWACnzNjzz+pZb47iToQ@public.gmane.org" , Thierry Reding , "srv_heupstream-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org" , "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org" , Daniel Kurtz , Sasha Hauer List-Id: iommu@lists.linux-foundation.org On Fri, Jul 24, 2015 at 06:43:13AM +0100, Yong Wu wrote: > On Tue, 2015-07-21 at 15:59 +0100, Will Deacon wrote: > > On Thu, Jul 16, 2015 at 10:04:34AM +0100, Yong Wu wrote: > > > +static void mtk_iommu_tlb_flush_all(void *cookie) > > > +{ > > > + struct mtk_iommu_domain *domain = cookie; > > > + void __iomem *base; > > > + > > > + base = domain->data->base; > > > + writel(F_INVLD_EN1 | F_INVLD_EN0, base + REG_MMU_INV_SEL); > > > + writel(F_ALL_INVLD, base + REG_MMU_INVALIDATE); > > > > This needs to be synchronous, so you probably want to call > > mtk_iommu_tlb_sync at the end. > > From our spec, we have to wait until HW done after tlb flush range. > But it don't need wait after tlb flush all. > so It isn't necessary to add mtk_iommu_tlb_sync in tlb_flush_all here. Okey doke, but I'm surprised you don't need a subsequent DSB or read-back. What if the writel is buffered on the way to the IOMMU? Will From mboxrd@z Thu Jan 1 00:00:00 1970 From: will.deacon@arm.com (Will Deacon) Date: Fri, 24 Jul 2015 17:55:10 +0100 Subject: [PATCH v3 5/6] iommu/mediatek: Add mt8173 IOMMU driver In-Reply-To: <1437716593.23932.73.camel@mhfsdcap03> References: <1437037475-9065-1-git-send-email-yong.wu@mediatek.com> <1437037475-9065-6-git-send-email-yong.wu@mediatek.com> <20150721145910.GG31095@arm.com> <1437716593.23932.73.camel@mhfsdcap03> Message-ID: <20150724165509.GD21177@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Fri, Jul 24, 2015 at 06:43:13AM +0100, Yong Wu wrote: > On Tue, 2015-07-21 at 15:59 +0100, Will Deacon wrote: > > On Thu, Jul 16, 2015 at 10:04:34AM +0100, Yong Wu wrote: > > > +static void mtk_iommu_tlb_flush_all(void *cookie) > > > +{ > > > + struct mtk_iommu_domain *domain = cookie; > > > + void __iomem *base; > > > + > > > + base = domain->data->base; > > > + writel(F_INVLD_EN1 | F_INVLD_EN0, base + REG_MMU_INV_SEL); > > > + writel(F_ALL_INVLD, base + REG_MMU_INVALIDATE); > > > > This needs to be synchronous, so you probably want to call > > mtk_iommu_tlb_sync at the end. > > From our spec, we have to wait until HW done after tlb flush range. > But it don't need wait after tlb flush all. > so It isn't necessary to add mtk_iommu_tlb_sync in tlb_flush_all here. Okey doke, but I'm surprised you don't need a subsequent DSB or read-back. What if the writel is buffered on the way to the IOMMU? Will From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754578AbbGXQzO (ORCPT ); Fri, 24 Jul 2015 12:55:14 -0400 Received: from foss.arm.com ([217.140.101.70]:46248 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754527AbbGXQzM (ORCPT ); Fri, 24 Jul 2015 12:55:12 -0400 Date: Fri, 24 Jul 2015 17:55:10 +0100 From: Will Deacon To: Yong Wu Cc: Joerg Roedel , Thierry Reding , Mark Rutland , Matthias Brugger , Robin Murphy , Daniel Kurtz , Tomasz Figa , Lucas Stach , Rob Herring , Catalin Marinas , "linux-mediatek@lists.infradead.org" , Sasha Hauer , "srv_heupstream@mediatek.com" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "iommu@lists.linux-foundation.org" , "pebolle@tiscali.nl" , "arnd@arndb.de" , "mitchelh@codeaurora.org" , "cloud.chou@mediatek.com" , "frederic.chen@mediatek.com" Subject: Re: [PATCH v3 5/6] iommu/mediatek: Add mt8173 IOMMU driver Message-ID: <20150724165509.GD21177@arm.com> References: <1437037475-9065-1-git-send-email-yong.wu@mediatek.com> <1437037475-9065-6-git-send-email-yong.wu@mediatek.com> <20150721145910.GG31095@arm.com> <1437716593.23932.73.camel@mhfsdcap03> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1437716593.23932.73.camel@mhfsdcap03> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jul 24, 2015 at 06:43:13AM +0100, Yong Wu wrote: > On Tue, 2015-07-21 at 15:59 +0100, Will Deacon wrote: > > On Thu, Jul 16, 2015 at 10:04:34AM +0100, Yong Wu wrote: > > > +static void mtk_iommu_tlb_flush_all(void *cookie) > > > +{ > > > + struct mtk_iommu_domain *domain = cookie; > > > + void __iomem *base; > > > + > > > + base = domain->data->base; > > > + writel(F_INVLD_EN1 | F_INVLD_EN0, base + REG_MMU_INV_SEL); > > > + writel(F_ALL_INVLD, base + REG_MMU_INVALIDATE); > > > > This needs to be synchronous, so you probably want to call > > mtk_iommu_tlb_sync at the end. > > From our spec, we have to wait until HW done after tlb flush range. > But it don't need wait after tlb flush all. > so It isn't necessary to add mtk_iommu_tlb_sync in tlb_flush_all here. Okey doke, but I'm surprised you don't need a subsequent DSB or read-back. What if the writel is buffered on the way to the IOMMU? Will