From mboxrd@z Thu Jan 1 00:00:00 1970 From: Benjamin Tissoires Subject: Re: [PATCH 3/3] drm/i915: Support DDI lane reversal for DP Date: Wed, 29 Jul 2015 11:22:40 -0400 Message-ID: <20150729152240.GD2743@mail.corp.redhat.com> References: <1438099409-25456-1-git-send-email-benjamin.tissoires@redhat.com> <1438099409-25456-4-git-send-email-benjamin.tissoires@redhat.com> <55B88E25.6000006@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5FE0488099 for ; Wed, 29 Jul 2015 08:22:44 -0700 (PDT) Content-Disposition: inline In-Reply-To: <55B88E25.6000006@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Sivakumar Thulasimani Cc: Daniel Vetter , intel-gfx@lists.freedesktop.org, Todd Broch , linux-kernel@vger.kernel.org List-Id: intel-gfx@lists.freedesktop.org T24gSnVsIDI5IDIwMTUgb3IgdGhlcmVhYm91dHMsIFNpdmFrdW1hciBUaHVsYXNpbWFuaSB3cm90 ZToKPiB3aHkgbm90IGRldGVjdCByZXZlcnNlIGluIGludGVsX2RwX2RldGVjdC9pbnRlbF9ocGRf cHVsc2UgPyB0aGF0IHdheSB5b3UgY2FuCj4gaWRlbnRpZnkgYm90aCBsYW5lIGNvdW50IGFuZCBy ZXZlcnNhbCBzdGF0ZSB3aXRob3V0IHRvdWNoaW5nIGFueXRoaW5nIGluIHRoZQo+IGxpbmsgdHJh aW5pbmcgY29kZS4gaSBhbSB5ZXQgdG8gdXBzdHJlYW0gbXkgY2hhbmdlcyBmb3IgQ0hUIHRoYXQg aSBjYW4gc2hhcmUKPiBpZiByZXF1aXJlZCB0aGF0IGRvZXMgdGhlIHNhbWUgaW4gaW50ZWxfZHBf ZGV0ZWN0IHdpdGhvdXQgdG91Y2hpbmcgYW55IGxpbmUKPiBpbiBsaW5rIHRyYWluaW5nIHBhdGgu CgpXaXRoIG15IGN1cnJlbnQgbGltaXRlZCBrbm93bGVkZ2Ugb2YgdGhlIGRwIGhvdHBsdWcgKGFu ZCBpOTE1IGRyaXZlcikgSQphbSBub3Qgc3VyZSB3ZSBjb3VsZCBkZXRlY3QgdGhlIHJldmVyc2Vk IHN0YXRlIHdpdGhvdXQgdHJ5aW5nIHRvIHRyYWluIDEKbGFuZSBvbmx5LiBJJ2QgYmUgZ2xhZCB0 byBsb29rIGF0IHlvdXIgY2hhbmdlcyBhbmQgdGVzdCB0aGVtIG9uIG15CnN5c3RlbSBpZiB5b3Ug dGhpbmsgdGhhdCBjb3VsZCBoZWxwIGhhdmluZyBhIGNsZWFuZXIgc29sdXRpb24uCgpDaGVlcnMs CkJlbmphbWluCgo+IAo+IE9uIDcvMjgvMjAxNSA5OjMzIFBNLCBCZW5qYW1pbiBUaXNzb2lyZXMg d3JvdGU6Cj4gPlRoZSBEUCBvdXRwdXRzIGNvbm5lY3RlZCB0aHJvdWdoIGEgVVNCIFR5cGUtQyBw b3J0IGNhbiBoYXZlIGludmVydGVkCj4gPmxhbmVzLiBUbyBkZXRlY3QgdGhhdCBjYXNlLCB3ZSBp bXBsZW1lbnQgYXV0b2RldGVjdGlvbiBieSB0cmFpbmluZyBvbmx5Cj4gPnRoZSBmaXJzdCBsYW5l IGlmIGl0IGRvZXNuJ3Qgd29yaywgd2UgYXNzdW1lIHRoYXQgd2UgbmVlZCB0byBpbnZlcnQKPiA+ dGhlIGxhbmVzLgo+ID4KPiA+VGVzdGVkIG9uIGEgQ2hyb21lYm9vayBQaXhlbCAyMDE1IChzYW11 cykgd2l0aCBhIFVTQiBUeXBlLUMgdG8gSERNSQo+ID5hZGFwdGVyIGFuZCBhIERlbGwgNEsgYW5k IHNvbWUgdmFyaW91cyByZWd1bGFyIG1vbml0b3JzLgo+ID4KPiA+QmFzZWQgb24gMiBwYXRjaGVz IGZyb20gdGhlIENocm9tZU9TIHRyZWUgYnk6Cj4gPlN0w6lwaGFuZSBNYXJjaGVzaW4gPG1hcmNo ZXVAY2hyb21pdW0ub3JnPgo+ID5Ub2RkIEJyb2NoIDx0YnJvY2hAY2hyb21pdW0ub3JnPgo+ID4K PiA+U2lnbmVkLW9mZi1ieTogQmVuamFtaW4gVGlzc29pcmVzIDxiZW5qYW1pbi50aXNzb2lyZXNA cmVkaGF0LmNvbT4KPiA+LS0tCj4gPiAgZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfZGRpLmMg fCAxMyArKysrKysrKysrKysrCj4gPiAgZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfZHAuYyAg fCAzNiArKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysKPiA+ICBkcml2ZXJzL2dw dS9kcm0vaTkxNS9pbnRlbF9kcnYuaCB8ICAxICsKPiA+ICAzIGZpbGVzIGNoYW5nZWQsIDUwIGlu c2VydGlvbnMoKykKPiA+Cj4gPmRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRl bF9kZGkuYyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2RkaS5jCj4gPmluZGV4IDlhNDBi ZmIuLjBiMGMxZWMgMTAwNjQ0Cj4gPi0tLSBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2Rk aS5jCj4gPisrKyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2RkaS5jCj4gPkBAIC0yMjQ5 LDYgKzIyNDksNyBAQCBzdGF0aWMgdm9pZCBpbnRlbF9kZGlfcHJlX2VuYWJsZShzdHJ1Y3QgaW50 ZWxfZW5jb2RlciAqaW50ZWxfZW5jb2RlcikKPiA+ICAJZW51bSBwb3J0IHBvcnQgPSBpbnRlbF9k ZGlfZ2V0X2VuY29kZXJfcG9ydChpbnRlbF9lbmNvZGVyKTsKPiA+ICAJaW50IHR5cGUgPSBpbnRl bF9lbmNvZGVyLT50eXBlOwo+ID4gIAlpbnQgaGRtaV9sZXZlbDsKPiA+Kwlib29sIHJldmVyc2Vk ID0gZmFsc2U7Cj4gPiAgCWlmICh0eXBlID09IElOVEVMX09VVFBVVF9FRFApIHsKPiA+ICAJCXN0 cnVjdCBpbnRlbF9kcCAqaW50ZWxfZHAgPSBlbmNfdG9faW50ZWxfZHAoZW5jb2Rlcik7Cj4gPkBA IC0yMjk1LDggKzIyOTYsMjAgQEAgc3RhdGljIHZvaWQgaW50ZWxfZGRpX3ByZV9lbmFibGUoc3Ry dWN0IGludGVsX2VuY29kZXIgKmludGVsX2VuY29kZXIpCj4gPiAgCWlmICh0eXBlID09IElOVEVM X09VVFBVVF9ESVNQTEFZUE9SVCB8fCB0eXBlID09IElOVEVMX09VVFBVVF9FRFApIHsKPiA+ICAJ CXN0cnVjdCBpbnRlbF9kcCAqaW50ZWxfZHAgPSBlbmNfdG9faW50ZWxfZHAoZW5jb2Rlcik7Cj4g PisJCWlmIChJU19CUk9BRFdFTEwoZGV2KSAmJiB0eXBlID09IElOVEVMX09VVFBVVF9ESVNQTEFZ UE9SVCkgewo+ID4rCQkJaW50ZWxfZGRpX2luaXRfZHBfYnVmX3JlZyhpbnRlbF9lbmNvZGVyKTsK PiA+KwkJCXJldmVyc2VkID0gaW50ZWxfZHBfaXNfcmV2ZXJzZWQoaW50ZWxfZHApOwo+ID4rCQl9 Cj4gPisKPiA+ICAJCWludGVsX2RkaV9pbml0X2RwX2J1Zl9yZWcoaW50ZWxfZW5jb2Rlcik7Cj4g PisJCWlmIChJU19CUk9BRFdFTEwoZGV2KSkgewo+ID4rCQkJaWYgKHJldmVyc2VkKQo+ID4rCQkJ CWludGVsX2RwLT5EUCB8PSBERElfQlVGX1BPUlRfUkVWRVJTQUw7Cj4gPisJCQllbHNlCj4gPisJ CQkJaW50ZWxfZHAtPkRQICY9IH5ERElfQlVGX1BPUlRfUkVWRVJTQUw7Cj4gPisJCX0KPiA+Kwo+ ID4gIAkJaW50ZWxfZHBfc2lua19kcG1zKGludGVsX2RwLCBEUk1fTU9ERV9EUE1TX09OKTsKPiA+ ICAJCWludGVsX2RwX3N0YXJ0X2xpbmtfdHJhaW4oaW50ZWxfZHApOwo+ID4gIAkJaW50ZWxfZHBf Y29tcGxldGVfbGlua190cmFpbihpbnRlbF9kcCk7Cj4gPmRpZmYgLS1naXQgYS9kcml2ZXJzL2dw dS9kcm0vaTkxNS9pbnRlbF9kcC5jIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfZHAuYwo+ ID5pbmRleCBiNzQwOTg3Li4xODI4MGNjIDEwMDY0NAo+ID4tLS0gYS9kcml2ZXJzL2dwdS9kcm0v aTkxNS9pbnRlbF9kcC5jCj4gPisrKyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2RwLmMK PiA+QEAgLTM4MjAsNiArMzgyMCw0MiBAQCBpbnRlbF9kcF9jb21wbGV0ZV9saW5rX3RyYWluKHN0 cnVjdCBpbnRlbF9kcCAqaW50ZWxfZHApCj4gPiAgCQlpbnRlbF9kcC0+RFAgPSBEUDsKPiA+ICB9 Cj4gPitib29sIGludGVsX2RwX2lzX3JldmVyc2VkKHN0cnVjdCBpbnRlbF9kcCAqaW50ZWxfZHAp Cj4gPit7Cj4gPisJc3RydWN0IGRybV9lbmNvZGVyICplbmNvZGVyID0gJmRwX3RvX2RpZ19wb3J0 KGludGVsX2RwKS0+YmFzZS5iYXNlOwo+ID4rCXN0cnVjdCBkcm1fZGV2aWNlICpkZXYgPSBlbmNv ZGVyLT5kZXY7Cj4gPisJc3RydWN0IGRybV9pOTE1X3ByaXZhdGUgKmRldl9wcml2ID0gZGV2LT5k ZXZfcHJpdmF0ZTsKPiA+Kwl1aW50MzJfdCBEUCA9IGludGVsX2RwLT5EUDsKPiA+Kwo+ID4rCS8q Cj4gPisJICogVHJhaW4gd2l0aCAxIGxhbmUuIFRoZXJlIGlzIG5vIGd1YXJhbnRlZSB0aGF0IHRo ZSBtb25pdG9yIHN1cHBvcnRzCj4gPisJICogMiBvciA0IGxhbmVzLCBhbmQgd2Ugd291bGRuJ3Qg c2VlIGFueSBhc3ltZXRyaWNpdHkgd2l0aCA0IGxhbmVzLgo+ID4rCSAqLwo+ID4rCWNvbnN0IHVp bnQ4X3QgbGFuZV9jb3VudCA9IDE7Cj4gPisJYm9vbCByZXZlcnNlZDsKPiA+Kwo+ID4rCWlmICgh SEFTX0RESShkZXYpKQo+ID4rCQlyZXR1cm4gZmFsc2U7Cj4gPisKPiA+KwlEUCAmPSB+KERESV9C VUZfUE9SVF9SRVZFUlNBTCB8IERESV9QT1JUX1dJRFRIKDQpKTsKPiA+KwlEUCB8PSBERElfUE9S VF9XSURUSChsYW5lX2NvdW50KTsKPiA+Kwo+ID4rCUk5MTVfV1JJVEUoaW50ZWxfZHAtPm91dHB1 dF9yZWcsIERQKTsKPiA+KwlQT1NUSU5HX1JFQUQoaW50ZWxfZHAtPm91dHB1dF9yZWcpOwo+ID4r CXVkZWxheSg2MDApOwo+ID4rCj4gPisJaWYgKCFfaW50ZWxfZHBfc3RhcnRfbGlua190cmFpbihp bnRlbF9kcCwgbGFuZV9jb3VudCwgJkRQLCB0cnVlKSkKPiA+KwkJcmV0dXJuIHRydWU7Cj4gPisK PiA+KwlyZXZlcnNlZCA9ICFfaW50ZWxfZHBfY29tcGxldGVfbGlua190cmFpbihpbnRlbF9kcCwg bGFuZV9jb3VudCwgJkRQLCB0cnVlKTsKPiA+Kwo+ID4rCS8qIGNsZWFyIHRyYWluaW5nLCB3ZSBo YWQgb25seSBvbmUgbGFuZSAqLwo+ID4rCWludGVsX2RwLT50cmFpbl9zZXRfdmFsaWQgPSBmYWxz ZTsKPiA+Kwo+ID4rCXJldHVybiByZXZlcnNlZDsKPiA+Kwo+ID4rfQo+ID4rCj4gPiAgdm9pZCBp bnRlbF9kcF9zdG9wX2xpbmtfdHJhaW4oc3RydWN0IGludGVsX2RwICppbnRlbF9kcCkKPiA+ICB7 Cj4gPiAgCWludGVsX2RwX3NldF9saW5rX3RyYWluKGludGVsX2RwLCAmaW50ZWxfZHAtPkRQLAo+ ID5kaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfZHJ2LmggYi9kcml2ZXJz L2dwdS9kcm0vaTkxNS9pbnRlbF9kcnYuaAo+ID5pbmRleCAzMjBjOWU2Li5jYmEwMGM2IDEwMDY0 NAo+ID4tLS0gYS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9kcnYuaAo+ID4rKysgYi9kcml2 ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9kcnYuaAo+ID5AQCAtMTE2OSw2ICsxMTY5LDcgQEAgaW50 IGludGVsX2RwX3NpbmtfY3JjKHN0cnVjdCBpbnRlbF9kcCAqaW50ZWxfZHAsIHU4ICpjcmMpOwo+ ID4gIGJvb2wgaW50ZWxfZHBfY29tcHV0ZV9jb25maWcoc3RydWN0IGludGVsX2VuY29kZXIgKmVu Y29kZXIsCj4gPiAgCQkJICAgICBzdHJ1Y3QgaW50ZWxfY3J0Y19zdGF0ZSAqcGlwZV9jb25maWcp Owo+ID4gIGJvb2wgaW50ZWxfZHBfaXNfZWRwKHN0cnVjdCBkcm1fZGV2aWNlICpkZXYsIGVudW0g cG9ydCBwb3J0KTsKPiA+K2Jvb2wgaW50ZWxfZHBfaXNfcmV2ZXJzZWQoc3RydWN0IGludGVsX2Rw ICppbnRlbF9kcCk7Cj4gPiAgZW51bSBpcnFyZXR1cm4gaW50ZWxfZHBfaHBkX3B1bHNlKHN0cnVj dCBpbnRlbF9kaWdpdGFsX3BvcnQgKmludGVsX2RpZ19wb3J0LAo+ID4gIAkJCQkgIGJvb2wgbG9u Z19ocGQpOwo+ID4gIHZvaWQgaW50ZWxfZWRwX2JhY2tsaWdodF9vbihzdHJ1Y3QgaW50ZWxfZHAg KmludGVsX2RwKTsKPiAKPiAtLSAKPiByZWdhcmRzLAo+IFNpdmFrdW1hcgo+IApfX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpJbnRlbC1nZnggbWFpbGluZyBs aXN0CkludGVsLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cDovL2xpc3RzLmZyZWVkZXNr dG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2ludGVsLWdmeAo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753141AbbG2PWp (ORCPT ); Wed, 29 Jul 2015 11:22:45 -0400 Received: from mx1.redhat.com ([209.132.183.28]:53928 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751291AbbG2PWo (ORCPT ); Wed, 29 Jul 2015 11:22:44 -0400 Date: Wed, 29 Jul 2015 11:22:40 -0400 From: Benjamin Tissoires To: Sivakumar Thulasimani Cc: Daniel Vetter , intel-gfx@lists.freedesktop.org, Todd Broch , linux-kernel@vger.kernel.org Subject: Re: [Intel-gfx] [PATCH 3/3] drm/i915: Support DDI lane reversal for DP Message-ID: <20150729152240.GD2743@mail.corp.redhat.com> References: <1438099409-25456-1-git-send-email-benjamin.tissoires@redhat.com> <1438099409-25456-4-git-send-email-benjamin.tissoires@redhat.com> <55B88E25.6000006@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <55B88E25.6000006@intel.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Jul 29 2015 or thereabouts, Sivakumar Thulasimani wrote: > why not detect reverse in intel_dp_detect/intel_hpd_pulse ? that way you can > identify both lane count and reversal state without touching anything in the > link training code. i am yet to upstream my changes for CHT that i can share > if required that does the same in intel_dp_detect without touching any line > in link training path. With my current limited knowledge of the dp hotplug (and i915 driver) I am not sure we could detect the reversed state without trying to train 1 lane only. I'd be glad to look at your changes and test them on my system if you think that could help having a cleaner solution. Cheers, Benjamin > > On 7/28/2015 9:33 PM, Benjamin Tissoires wrote: > >The DP outputs connected through a USB Type-C port can have inverted > >lanes. To detect that case, we implement autodetection by training only > >the first lane if it doesn't work, we assume that we need to invert > >the lanes. > > > >Tested on a Chromebook Pixel 2015 (samus) with a USB Type-C to HDMI > >adapter and a Dell 4K and some various regular monitors. > > > >Based on 2 patches from the ChromeOS tree by: > >Stéphane Marchesin > >Todd Broch > > > >Signed-off-by: Benjamin Tissoires > >--- > > drivers/gpu/drm/i915/intel_ddi.c | 13 +++++++++++++ > > drivers/gpu/drm/i915/intel_dp.c | 36 ++++++++++++++++++++++++++++++++++++ > > drivers/gpu/drm/i915/intel_drv.h | 1 + > > 3 files changed, 50 insertions(+) > > > >diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > >index 9a40bfb..0b0c1ec 100644 > >--- a/drivers/gpu/drm/i915/intel_ddi.c > >+++ b/drivers/gpu/drm/i915/intel_ddi.c > >@@ -2249,6 +2249,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) > > enum port port = intel_ddi_get_encoder_port(intel_encoder); > > int type = intel_encoder->type; > > int hdmi_level; > >+ bool reversed = false; > > if (type == INTEL_OUTPUT_EDP) { > > struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > >@@ -2295,8 +2296,20 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) > > if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { > > struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > >+ if (IS_BROADWELL(dev) && type == INTEL_OUTPUT_DISPLAYPORT) { > >+ intel_ddi_init_dp_buf_reg(intel_encoder); > >+ reversed = intel_dp_is_reversed(intel_dp); > >+ } > >+ > > intel_ddi_init_dp_buf_reg(intel_encoder); > >+ if (IS_BROADWELL(dev)) { > >+ if (reversed) > >+ intel_dp->DP |= DDI_BUF_PORT_REVERSAL; > >+ else > >+ intel_dp->DP &= ~DDI_BUF_PORT_REVERSAL; > >+ } > >+ > > intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); > > intel_dp_start_link_train(intel_dp); > > intel_dp_complete_link_train(intel_dp); > >diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > >index b740987..18280cc 100644 > >--- a/drivers/gpu/drm/i915/intel_dp.c > >+++ b/drivers/gpu/drm/i915/intel_dp.c > >@@ -3820,6 +3820,42 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp) > > intel_dp->DP = DP; > > } > >+bool intel_dp_is_reversed(struct intel_dp *intel_dp) > >+{ > >+ struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; > >+ struct drm_device *dev = encoder->dev; > >+ struct drm_i915_private *dev_priv = dev->dev_private; > >+ uint32_t DP = intel_dp->DP; > >+ > >+ /* > >+ * Train with 1 lane. There is no guarantee that the monitor supports > >+ * 2 or 4 lanes, and we wouldn't see any asymetricity with 4 lanes. > >+ */ > >+ const uint8_t lane_count = 1; > >+ bool reversed; > >+ > >+ if (!HAS_DDI(dev)) > >+ return false; > >+ > >+ DP &= ~(DDI_BUF_PORT_REVERSAL | DDI_PORT_WIDTH(4)); > >+ DP |= DDI_PORT_WIDTH(lane_count); > >+ > >+ I915_WRITE(intel_dp->output_reg, DP); > >+ POSTING_READ(intel_dp->output_reg); > >+ udelay(600); > >+ > >+ if (!_intel_dp_start_link_train(intel_dp, lane_count, &DP, true)) > >+ return true; > >+ > >+ reversed = !_intel_dp_complete_link_train(intel_dp, lane_count, &DP, true); > >+ > >+ /* clear training, we had only one lane */ > >+ intel_dp->train_set_valid = false; > >+ > >+ return reversed; > >+ > >+} > >+ > > void intel_dp_stop_link_train(struct intel_dp *intel_dp) > > { > > intel_dp_set_link_train(intel_dp, &intel_dp->DP, > >diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > >index 320c9e6..cba00c6 100644 > >--- a/drivers/gpu/drm/i915/intel_drv.h > >+++ b/drivers/gpu/drm/i915/intel_drv.h > >@@ -1169,6 +1169,7 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc); > > bool intel_dp_compute_config(struct intel_encoder *encoder, > > struct intel_crtc_state *pipe_config); > > bool intel_dp_is_edp(struct drm_device *dev, enum port port); > >+bool intel_dp_is_reversed(struct intel_dp *intel_dp); > > enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, > > bool long_hpd); > > void intel_edp_backlight_on(struct intel_dp *intel_dp); > > -- > regards, > Sivakumar >