diff for duplicates of <20150730162444.25e4f360@xhacker> diff --git a/a/1.txt b/N1/1.txt index de20df9..5cd344a 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,5 +1,5 @@ On Thu, 30 Jul 2015 10:06:38 +0200 -Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> wrote: +Sebastian Hesselbarth <sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote: > On 07/22/2015 11:39 AM, Jisheng Zhang wrote: > > Add initial dtsi file to support Marvell Berlin4CT SoC with @@ -8,7 +8,7 @@ Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> wrote: > > It also adds dts file for Marvell Berlin4CT DMP board which is > > based on Berlin4CT SoC. > > -> > Signed-off-by: Jisheng Zhang <jszhang@marvell.com> +> > Signed-off-by: Jisheng Zhang <jszhang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org> > > --- > [...] > > diff --git a/arch/arm64/boot/dts/marvell/berlin4ct-dmp.dts b/arch/arm64/boot/dts/marvell/berlin4ct-dmp.dts @@ -20,7 +20,7 @@ Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> wrote: > > +/* > > + * Copyright (C) 2015 Marvell Technology Group Ltd. > > + * -> > + * Author: Jisheng Zhang <jszhang@marvell.com> +> > + * Author: Jisheng Zhang <jszhang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org> > [...] > > +/ { > @@ -61,7 +61,7 @@ It doesn't matter, will do in newer version. > > +/* > > + * Copyright (C) 2015 Marvell Technology Group Ltd. > > + * -> > + * Author: Jisheng Zhang <jszhang@marvell.com> +> > + * Author: Jisheng Zhang <jszhang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org> > [...] > > + > > +/ { @@ -103,7 +103,7 @@ Jisheng > > Sebastian > -> > + gic: interrupt-controller at 901000 { +> > + gic: interrupt-controller@901000 { > > + compatible = "arm,gic-400"; > > + #interrupt-cells = <3>; > > + interrupt-controller; @@ -114,14 +114,14 @@ Jisheng > > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > > + }; > > + -> > + apb at fc0000 { +> > + apb@fc0000 { > > + compatible = "simple-bus"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges = <0 0xfc0000 0x10000>; > > + interrupt-parent = <&sic>; > > + -> > + sic: interrupt-controller at 1000 { +> > + sic: interrupt-controller@1000 { > > + compatible = "snps,dw-apb-ictl"; > > + reg = <0x1000 0x30>; > > + interrupt-controller; @@ -130,7 +130,7 @@ Jisheng > > + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; > > + }; > > + -> > + uart0: uart at d000 { +> > + uart0: uart@d000 { > > + compatible = "snps,dw-apb-uart"; > > + reg = <0xd000 0x100>; > > + interrupts = <8>; @@ -142,3 +142,8 @@ Jisheng > > + }; > > +}; > > + +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index e38f170..2d852b9 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,14 +1,28 @@ "ref\01437557992-7111-1-git-send-email-jszhang@marvell.com\0" "ref\01437557992-7111-2-git-send-email-jszhang@marvell.com\0" "ref\055B9DB0E.7010303@gmail.com\0" - "From\0jszhang@marvell.com (Jisheng Zhang)\0" - "Subject\0[PATCH v4 1/2] arm64: dts: Add dts files for Marvell Berlin4CT SoC\0" + "ref\055B9DB0E.7010303-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org\0" + "From\0Jisheng Zhang <jszhang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>\0" + "Subject\0Re: [PATCH v4 1/2] arm64: dts: Add dts files for Marvell Berlin4CT SoC\0" "Date\0Thu, 30 Jul 2015 16:24:44 +0800\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Sebastian Hesselbarth <sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0" + "Cc\0catalin.marinas-5wv7dgnIgG8@public.gmane.org" + will.deacon-5wv7dgnIgG8@public.gmane.org + khilman-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org + arnd-r2nGTMty4D4@public.gmane.org + olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org + mark.rutland-5wv7dgnIgG8@public.gmane.org + sudeep.holla-5wv7dgnIgG8@public.gmane.org + robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org + galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org + pawel.moll-5wv7dgnIgG8@public.gmane.org + linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + " devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" "\00:1\0" "b\0" "On Thu, 30 Jul 2015 10:06:38 +0200\n" - "Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> wrote:\n" + "Sebastian Hesselbarth <sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:\n" "\n" "> On 07/22/2015 11:39 AM, Jisheng Zhang wrote:\n" "> > Add initial dtsi file to support Marvell Berlin4CT SoC with\n" @@ -17,7 +31,7 @@ "> > It also adds dts file for Marvell Berlin4CT DMP board which is\n" "> > based on Berlin4CT SoC.\n" "> >\n" - "> > Signed-off-by: Jisheng Zhang <jszhang@marvell.com>\n" + "> > Signed-off-by: Jisheng Zhang <jszhang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>\n" "> > ---\n" "> [...]\n" "> > diff --git a/arch/arm64/boot/dts/marvell/berlin4ct-dmp.dts b/arch/arm64/boot/dts/marvell/berlin4ct-dmp.dts\n" @@ -29,7 +43,7 @@ "> > +/*\n" "> > + * Copyright (C) 2015 Marvell Technology Group Ltd.\n" "> > + *\n" - "> > + * Author: Jisheng Zhang <jszhang@marvell.com>\n" + "> > + * Author: Jisheng Zhang <jszhang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>\n" "> [...]\n" "> > +/ {\n" "> \n" @@ -70,7 +84,7 @@ "> > +/*\n" "> > + * Copyright (C) 2015 Marvell Technology Group Ltd.\n" "> > + *\n" - "> > + * Author: Jisheng Zhang <jszhang@marvell.com>\n" + "> > + * Author: Jisheng Zhang <jszhang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>\n" "> [...]\n" "> > +\n" "> > +/ {\n" @@ -112,7 +126,7 @@ "> \n" "> Sebastian\n" "> \n" - "> > +\t\tgic: interrupt-controller at 901000 {\n" + "> > +\t\tgic: interrupt-controller@901000 {\n" "> > +\t\t\tcompatible = \"arm,gic-400\";\n" "> > +\t\t\t#interrupt-cells = <3>;\n" "> > +\t\t\tinterrupt-controller;\n" @@ -123,14 +137,14 @@ "> > +\t\t\tinterrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;\n" "> > +\t\t};\n" "> > +\n" - "> > +\t\tapb at fc0000 {\n" + "> > +\t\tapb@fc0000 {\n" "> > +\t\t\tcompatible = \"simple-bus\";\n" "> > +\t\t\t#address-cells = <1>;\n" "> > +\t\t\t#size-cells = <1>;\n" "> > +\t\t\tranges = <0 0xfc0000 0x10000>;\n" "> > +\t\t\tinterrupt-parent = <&sic>;\n" "> > +\n" - "> > +\t\t\tsic: interrupt-controller at 1000 {\n" + "> > +\t\t\tsic: interrupt-controller@1000 {\n" "> > +\t\t\t\tcompatible = \"snps,dw-apb-ictl\";\n" "> > +\t\t\t\treg = <0x1000 0x30>;\n" "> > +\t\t\t\tinterrupt-controller;\n" @@ -139,7 +153,7 @@ "> > +\t\t\t\tinterrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;\n" "> > +\t\t\t};\n" "> > +\n" - "> > +\t\t\tuart0: uart at d000 {\n" + "> > +\t\t\tuart0: uart@d000 {\n" "> > +\t\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> > +\t\t\t\treg = <0xd000 0x100>;\n" "> > +\t\t\t\tinterrupts = <8>;\n" @@ -150,6 +164,11 @@ "> > +\t\t};\n" "> > +\t};\n" "> > +};\n" - > > + "> >\n" + "\n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -42987513fd3ea39bc10cba39df0b872e3d21a0ad5483e9623b7120342a40fdc3 +5ba89326762d943c1071697999f60c3d9dc24b72a1e94b28dad0aebd5700308c
diff --git a/a/1.txt b/N2/1.txt index de20df9..5d59748 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -103,7 +103,7 @@ Jisheng > > Sebastian > -> > + gic: interrupt-controller at 901000 { +> > + gic: interrupt-controller@901000 { > > + compatible = "arm,gic-400"; > > + #interrupt-cells = <3>; > > + interrupt-controller; @@ -114,14 +114,14 @@ Jisheng > > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > > + }; > > + -> > + apb at fc0000 { +> > + apb@fc0000 { > > + compatible = "simple-bus"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges = <0 0xfc0000 0x10000>; > > + interrupt-parent = <&sic>; > > + -> > + sic: interrupt-controller at 1000 { +> > + sic: interrupt-controller@1000 { > > + compatible = "snps,dw-apb-ictl"; > > + reg = <0x1000 0x30>; > > + interrupt-controller; @@ -130,7 +130,7 @@ Jisheng > > + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; > > + }; > > + -> > + uart0: uart at d000 { +> > + uart0: uart@d000 { > > + compatible = "snps,dw-apb-uart"; > > + reg = <0xd000 0x100>; > > + interrupts = <8>; diff --git a/a/content_digest b/N2/content_digest index e38f170..2f90506 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,10 +1,23 @@ "ref\01437557992-7111-1-git-send-email-jszhang@marvell.com\0" "ref\01437557992-7111-2-git-send-email-jszhang@marvell.com\0" "ref\055B9DB0E.7010303@gmail.com\0" - "From\0jszhang@marvell.com (Jisheng Zhang)\0" - "Subject\0[PATCH v4 1/2] arm64: dts: Add dts files for Marvell Berlin4CT SoC\0" + "From\0Jisheng Zhang <jszhang@marvell.com>\0" + "Subject\0Re: [PATCH v4 1/2] arm64: dts: Add dts files for Marvell Berlin4CT SoC\0" "Date\0Thu, 30 Jul 2015 16:24:44 +0800\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>\0" + "Cc\0<catalin.marinas@arm.com>" + <will.deacon@arm.com> + <khilman@linaro.org> + <arnd@arndb.de> + <olof@lixom.net> + <mark.rutland@arm.com> + <sudeep.holla@arm.com> + <robh+dt@kernel.org> + <galak@codeaurora.org> + <pawel.moll@arm.com> + <linux-arm-kernel@lists.infradead.org> + <linux-kernel@vger.kernel.org> + " <devicetree@vger.kernel.org>\0" "\00:1\0" "b\0" "On Thu, 30 Jul 2015 10:06:38 +0200\n" @@ -112,7 +125,7 @@ "> \n" "> Sebastian\n" "> \n" - "> > +\t\tgic: interrupt-controller at 901000 {\n" + "> > +\t\tgic: interrupt-controller@901000 {\n" "> > +\t\t\tcompatible = \"arm,gic-400\";\n" "> > +\t\t\t#interrupt-cells = <3>;\n" "> > +\t\t\tinterrupt-controller;\n" @@ -123,14 +136,14 @@ "> > +\t\t\tinterrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;\n" "> > +\t\t};\n" "> > +\n" - "> > +\t\tapb at fc0000 {\n" + "> > +\t\tapb@fc0000 {\n" "> > +\t\t\tcompatible = \"simple-bus\";\n" "> > +\t\t\t#address-cells = <1>;\n" "> > +\t\t\t#size-cells = <1>;\n" "> > +\t\t\tranges = <0 0xfc0000 0x10000>;\n" "> > +\t\t\tinterrupt-parent = <&sic>;\n" "> > +\n" - "> > +\t\t\tsic: interrupt-controller at 1000 {\n" + "> > +\t\t\tsic: interrupt-controller@1000 {\n" "> > +\t\t\t\tcompatible = \"snps,dw-apb-ictl\";\n" "> > +\t\t\t\treg = <0x1000 0x30>;\n" "> > +\t\t\t\tinterrupt-controller;\n" @@ -139,7 +152,7 @@ "> > +\t\t\t\tinterrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;\n" "> > +\t\t\t};\n" "> > +\n" - "> > +\t\t\tuart0: uart at d000 {\n" + "> > +\t\t\tuart0: uart@d000 {\n" "> > +\t\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> > +\t\t\t\treg = <0xd000 0x100>;\n" "> > +\t\t\t\tinterrupts = <8>;\n" @@ -152,4 +165,4 @@ "> > +};\n" > > -42987513fd3ea39bc10cba39df0b872e3d21a0ad5483e9623b7120342a40fdc3 +87be386fb9505e49d1c439e69bc9bbb03bfddd79500ab7666ba0c438be2cd4f5
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