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diff for duplicates of <20150730184523.GC16663@arm.com>

diff --git a/a/1.txt b/N1/1.txt
index add60ac..a49a97f 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -1,7 +1,7 @@
 Hello,
 
-On Thu, Jul 30, 2015 at 06:55:06PM +0100, tchalamarla-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org wrote:
-> From: Tirumalesh Chalamarla <tchalamarla-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
+On Thu, Jul 30, 2015 at 06:55:06PM +0100, tchalamarla at caviumnetworks.com wrote:
+> From: Tirumalesh Chalamarla <tchalamarla@caviumnetworks.com>
 > 
 > The SMMU architecture defines two different behaviors when 64-bit
 > registers are written with 32-bit writes.  The first behavior causes
@@ -18,7 +18,7 @@ On Thu, Jul 30, 2015 at 06:55:06PM +0100, tchalamarla-M3mlKVOIwJVv6pq1l3V1OdBPR1
 >   SMMU()_CB()_TTBR1
 >   SMMU()_CB()_FAR
 > 
-> Signed-off-by: Tirumalesh Chalamarla <tchalamarla-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
+> Signed-off-by: Tirumalesh Chalamarla <tchalamarla@caviumnetworks.com>
 > ---
 >  drivers/iommu/arm-smmu.c | 51 ++++++++++++++++++++++++++++++++++--------------
 >  1 file changed, 36 insertions(+), 15 deletions(-)
diff --git a/a/content_digest b/N1/content_digest
index c08ee6b..41186ba 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -1,19 +1,14 @@
  "ref\01438278906-29627-1-git-send-email-tchalamarla@caviumnetworks.com\0"
- "ref\01438278906-29627-1-git-send-email-tchalamarla-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org\0"
- "From\0Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>\0"
- "Subject\0Re: [PATCH] iommu/arm-smmu-v2: ThunderX(errata-23399) mis-extends 64bit registers\0"
+ "From\0will.deacon@arm.com (Will Deacon)\0"
+ "Subject\0[PATCH] iommu/arm-smmu-v2: ThunderX(errata-23399) mis-extends 64bit registers\0"
  "Date\0Thu, 30 Jul 2015 19:45:23 +0100\0"
- "To\0tchalamarla-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org <tchalamarla-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>\0"
- "Cc\0iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org <iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org>"
-  robert.richter-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org <robert.richter-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>
-  linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>
- " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>\0"
+ "To\0linux-arm-kernel@lists.infradead.org\0"
  "\00:1\0"
  "b\0"
  "Hello,\n"
  "\n"
- "On Thu, Jul 30, 2015 at 06:55:06PM +0100, tchalamarla-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org wrote:\n"
- "> From: Tirumalesh Chalamarla <tchalamarla-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>\n"
+ "On Thu, Jul 30, 2015 at 06:55:06PM +0100, tchalamarla at caviumnetworks.com wrote:\n"
+ "> From: Tirumalesh Chalamarla <tchalamarla@caviumnetworks.com>\n"
  "> \n"
  "> The SMMU architecture defines two different behaviors when 64-bit\n"
  "> registers are written with 32-bit writes.  The first behavior causes\n"
@@ -30,7 +25,7 @@
  ">   SMMU()_CB()_TTBR1\n"
  ">   SMMU()_CB()_FAR\n"
  "> \n"
- "> Signed-off-by: Tirumalesh Chalamarla <tchalamarla-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>\n"
+ "> Signed-off-by: Tirumalesh Chalamarla <tchalamarla@caviumnetworks.com>\n"
  "> ---\n"
  ">  drivers/iommu/arm-smmu.c | 51 ++++++++++++++++++++++++++++++++++--------------\n"
  ">  1 file changed, 36 insertions(+), 15 deletions(-)\n"
@@ -88,4 +83,4 @@
  "\n"
  Will
 
-2b1a855d2a8952d048753b93e0514d301f9c1ff7d31292ce230c35526664b0af
+fde8f16849f3f576306111cce37286cb262bc7c8bf683ec8e8aace0a2b483c37

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