* [PATCH v2 1/8] MIPS: Loongson: Add basic Loongson-1A CPU support
2015-06-17 10:32 [PATCH v2 0/8] MIPS: Loongson: Add the Loongson-1A processor support Binbin Zhou
@ 2015-06-17 10:32 ` Binbin Zhou
2015-06-17 10:32 ` [PATCH v2 2/8] MIPS: Loongson: Add Loongson-1A Kconfig options Binbin Zhou
` (6 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Binbin Zhou @ 2015-06-17 10:32 UTC (permalink / raw)
To: Ralf Baechle
Cc: John Crispin, Steven J. Hill, linux-mips, Fuxin Zhang,
Zhangjin Wu, Kelvin Cheung, Binbin Zhou, Chunbo Cui, Huacai Chen
The Loongson 1A is similar with Loongson 1B, which is a 32-bit SoC.
It implements the MIPS32 release 2 instruction set.
They share the same PRID, so we rewrite the PRID_REV_LOONGSON1B to
PRID_REV_LOONGSON1A_1B, and use their CPU macros to distinguish.
Signed-off-by: Chunbo Cui <cuicb@lemote.com>
Signed-off-by: Binbin Zhou <zhoubb@lemote.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
arch/mips/include/asm/cpu-type.h | 3 ++-
arch/mips/include/asm/cpu.h | 2 +-
arch/mips/kernel/cpu-probe.c | 6 +++++-
arch/mips/loongson32/Platform | 1 +
arch/mips/loongson32/common/setup.c | 6 +++++-
arch/mips/mm/c-r4k.c | 7 +++++++
6 files changed, 21 insertions(+), 4 deletions(-)
diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
index d41e8e2..b05908c 100644
--- a/arch/mips/include/asm/cpu-type.h
+++ b/arch/mips/include/asm/cpu-type.h
@@ -24,7 +24,8 @@ static inline int __pure __get_cpu_type(const int cpu_type)
case CPU_LOONGSON3:
#endif
-#ifdef CONFIG_SYS_HAS_CPU_LOONGSON1B
+#if defined(CONFIG_SYS_HAS_CPU_LOONGSON1A) || \
+ defined(CONFIG_SYS_HAS_CPU_LOONGSON1B)
case CPU_LOONGSON1:
#endif
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index e46e406..a868441 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -233,7 +233,7 @@
#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */
#define PRID_REV_VR4130 0x0080
#define PRID_REV_34K_V1_0_2 0x0022
-#define PRID_REV_LOONGSON1B 0x0020
+#define PRID_REV_LOONGSON1A_1B 0x0020
#define PRID_REV_LOONGSON2E 0x0002
#define PRID_REV_LOONGSON2F 0x0003
#define PRID_REV_LOONGSON3A 0x0005
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index dbe0792..fa5c33e 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1006,8 +1006,12 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
c->cputype = CPU_LOONGSON1;
switch (c->processor_id & PRID_REV_MASK) {
- case PRID_REV_LOONGSON1B:
+ case PRID_REV_LOONGSON1A_1B:
+#ifdef CONFIG_CPU_LOONGSON1A
+ __cpu_name[cpu] = "Loongson 1A";
+#else
__cpu_name[cpu] = "Loongson 1B";
+#endif
break;
}
diff --git a/arch/mips/loongson32/Platform b/arch/mips/loongson32/Platform
index ebb6dc2..e114c85 100644
--- a/arch/mips/loongson32/Platform
+++ b/arch/mips/loongson32/Platform
@@ -4,4 +4,5 @@ cflags-$(CONFIG_CPU_LOONGSON1) += \
platform-$(CONFIG_MACH_LOONGSON32) += loongson32/
cflags-$(CONFIG_MACH_LOONGSON32) += -I$(srctree)/arch/mips/include/asm/mach-loongson32
+load-$(CONFIG_LOONGSON1_LS1A) += 0xffffffff80200000
load-$(CONFIG_LOONGSON1_LS1B) += 0xffffffff80100000
diff --git a/arch/mips/loongson32/common/setup.c b/arch/mips/loongson32/common/setup.c
index 62f41af..c3d2036 100644
--- a/arch/mips/loongson32/common/setup.c
+++ b/arch/mips/loongson32/common/setup.c
@@ -21,8 +21,12 @@ const char *get_system_type(void)
unsigned int processor_id = (¤t_cpu_data)->processor_id;
switch (processor_id & PRID_REV_MASK) {
- case PRID_REV_LOONGSON1B:
+ case PRID_REV_LOONGSON1A_1B:
+#ifdef CONFIG_CPU_LOONGSON1A
+ return "LOONGSON LS1A";
+#else
return "LOONGSON LS1B";
+#endif
default:
return "LOONGSON (unknown)";
}
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 7f660dc..cec179f 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1277,6 +1277,13 @@ static void probe_pcache(void)
c->dcache.flags |= MIPS_CACHE_PINDEX;
break;
}
+ case CPU_LOONGSON1:
+ if ((read_c0_config7() & (1 << 16))) {
+ /* effectively physically indexed dcache,
+ thus no virtual aliases. */
+ c->dcache.flags |= MIPS_CACHE_PINDEX;
+ break;
+ }
default:
if (has_74k_erratum || c->dcache.waysize > PAGE_SIZE)
c->dcache.flags |= MIPS_CACHE_ALIASES;
--
1.9.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v2 2/8] MIPS: Loongson: Add Loongson-1A Kconfig options
2015-06-17 10:32 [PATCH v2 0/8] MIPS: Loongson: Add the Loongson-1A processor support Binbin Zhou
2015-06-17 10:32 ` [PATCH v2 1/8] MIPS: Loongson: Add basic Loongson-1A CPU support Binbin Zhou
@ 2015-06-17 10:32 ` Binbin Zhou
2015-06-17 10:32 ` [PATCH v2 3/8] MIPS: Loongson: Add platform devices for Loongson-1A/1B Binbin Zhou
` (5 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Binbin Zhou @ 2015-06-17 10:32 UTC (permalink / raw)
To: Ralf Baechle
Cc: John Crispin, Steven J. Hill, linux-mips, Fuxin Zhang,
Zhangjin Wu, Kelvin Cheung, Binbin Zhou, Chunbo Cui, Huacai Chen
Added Kconfig options include: Loongson-1A CPU and machine definition,
CPU cache features, 32-bit kernel and early printk support.
Signed-off-by: Chunbo Cui <cuicb@lemote.com>
Signed-off-by: Binbin Zhou <zhoubb@lemote.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
arch/mips/Kconfig | 11 +++++++++++
arch/mips/loongson32/Kconfig | 20 ++++++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index cf09f42..0918915 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1327,6 +1327,14 @@ config CPU_LOONGSON2F
have a similar programming interface with FPGA northbridge used in
Loongson2E.
+config CPU_LOONGSON1A
+ bool "Loongson 1A"
+ depends on SYS_HAS_CPU_LOONGSON1A
+ select CPU_LOONGSON1
+ help
+ The Loongson 1A is a 32-bit SoC, which implements the MIPS32
+ release 2 instruction set.
+
config CPU_LOONGSON1B
bool "Loongson 1B"
depends on SYS_HAS_CPU_LOONGSON1B
@@ -1770,6 +1778,9 @@ config SYS_HAS_CPU_LOONGSON2F
select CPU_SUPPORTS_ADDRWINCFG if 64BIT
select CPU_SUPPORTS_UNCACHED_ACCELERATED
+config SYS_HAS_CPU_LOONGSON1A
+ bool
+
config SYS_HAS_CPU_LOONGSON1B
bool
diff --git a/arch/mips/loongson32/Kconfig b/arch/mips/loongson32/Kconfig
index 7704f20..741867c 100644
--- a/arch/mips/loongson32/Kconfig
+++ b/arch/mips/loongson32/Kconfig
@@ -1,8 +1,28 @@
if MACH_LOONGSON32
+config ZONE_DMA
+ prompt "Zone DMA"
+ bool
+
choice
prompt "Machine Type"
+config LOONGSON1_LS1A
+ bool "Loongson LS1A board"
+ select CEVT_R4K
+ select CSRC_R4K
+ select SYS_HAS_CPU_LOONGSON1A
+ select DMA_NONCOHERENT
+ select BOOT_ELF32
+ select IRQ_MIPS_CPU
+ select SYS_SUPPORTS_32BIT_KERNEL
+ select SYS_SUPPORTS_LITTLE_ENDIAN
+ select SYS_SUPPORTS_HIGHMEM
+ select SYS_SUPPORTS_MIPS16
+ select SYS_HAS_EARLY_PRINTK
+ select USE_GENERIC_EARLY_PRINTK_8250
+ select COMMON_CLK
+
config LOONGSON1_LS1B
bool "Loongson LS1B board"
select CEVT_R4K if !MIPS_EXTERNAL_TIMER
--
1.9.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v2 3/8] MIPS: Loongson: Add platform devices for Loongson-1A/1B
2015-06-17 10:32 [PATCH v2 0/8] MIPS: Loongson: Add the Loongson-1A processor support Binbin Zhou
2015-06-17 10:32 ` [PATCH v2 1/8] MIPS: Loongson: Add basic Loongson-1A CPU support Binbin Zhou
2015-06-17 10:32 ` [PATCH v2 2/8] MIPS: Loongson: Add Loongson-1A Kconfig options Binbin Zhou
@ 2015-06-17 10:32 ` Binbin Zhou
2015-08-03 15:21 ` Ralf Baechle
2015-06-17 10:32 ` [PATCH v2 4/8] MIPS: Loongson: Add loongson-1A board support Binbin Zhou
` (4 subsequent siblings)
7 siblings, 1 reply; 11+ messages in thread
From: Binbin Zhou @ 2015-06-17 10:32 UTC (permalink / raw)
To: Ralf Baechle
Cc: John Crispin, Steven J. Hill, linux-mips, Fuxin Zhang,
Zhangjin Wu, Kelvin Cheung, Binbin Zhou, Chunbo Cui, Huacai Chen
Added basic platform devices for Loongson 1A, including serial port,
ethernet, AHCI, USB, RTC, SPI and so on.
Most of the devices are shared with Loongson 1B, like serial port,
ethernet, USB and so on.
Specially, something like AHCI is only used in Loonson 1A.
Signed-off-by: Chunbo Cui <cuicb@lemote.com>
Signed-off-by: Binbin Zhou <zhoubb@lemote.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
arch/mips/include/asm/mach-loongson32/irq.h | 1 +
arch/mips/include/asm/mach-loongson32/loongson1.h | 167 +++++++++++--
arch/mips/include/asm/mach-loongson32/platform.h | 11 +
arch/mips/loongson32/common/platform.c | 290 +++++++++++++++++++++-
4 files changed, 441 insertions(+), 28 deletions(-)
diff --git a/arch/mips/include/asm/mach-loongson32/irq.h b/arch/mips/include/asm/mach-loongson32/irq.h
index 0d35b99..326e541 100644
--- a/arch/mips/include/asm/mach-loongson32/irq.h
+++ b/arch/mips/include/asm/mach-loongson32/irq.h
@@ -65,6 +65,7 @@
#define LS1X_OHCI_IRQ LS1X_IRQ(1, 1)
#define LS1X_GMAC0_IRQ LS1X_IRQ(1, 2)
#define LS1X_GMAC1_IRQ LS1X_IRQ(1, 3)
+#define LS1X_AHCI_IRQ LS1X_IRQ(1, 4)
#define LS1X_IRQS (LS1X_IRQ(4, 31) + 1 - LS1X_IRQ_BASE)
diff --git a/arch/mips/include/asm/mach-loongson32/loongson1.h b/arch/mips/include/asm/mach-loongson32/loongson1.h
index 12aa129..5c1ba48 100644
--- a/arch/mips/include/asm/mach-loongson32/loongson1.h
+++ b/arch/mips/include/asm/mach-loongson32/loongson1.h
@@ -15,32 +15,147 @@
#define DEFAULT_MEMSIZE 256 /* If no memsize provided */
-/* Loongson 1 Register Bases */
-#define LS1X_MUX_BASE 0x1fd00420
-#define LS1X_INTC_BASE 0x1fd01040
-#define LS1X_EHCI_BASE 0x1fe00000
-#define LS1X_OHCI_BASE 0x1fe08000
-#define LS1X_GMAC0_BASE 0x1fe10000
-#define LS1X_GMAC1_BASE 0x1fe20000
-
-#define LS1X_UART0_BASE 0x1fe40000
-#define LS1X_UART1_BASE 0x1fe44000
-#define LS1X_UART2_BASE 0x1fe48000
-#define LS1X_UART3_BASE 0x1fe4c000
-#define LS1X_CAN0_BASE 0x1fe50000
-#define LS1X_CAN1_BASE 0x1fe54000
-#define LS1X_I2C0_BASE 0x1fe58000
-#define LS1X_I2C1_BASE 0x1fe68000
-#define LS1X_I2C2_BASE 0x1fe70000
-#define LS1X_PWM0_BASE 0x1fe5c000
-#define LS1X_PWM1_BASE 0x1fe5c010
-#define LS1X_PWM2_BASE 0x1fe5c020
-#define LS1X_PWM3_BASE 0x1fe5c030
-#define LS1X_WDT_BASE 0x1fe5c060
-#define LS1X_RTC_BASE 0x1fe64000
-#define LS1X_AC97_BASE 0x1fe74000
-#define LS1X_NAND_BASE 0x1fe78000
-#define LS1X_CLK_BASE 0x1fe78030
+#define LS1X_DC_REG_BASE 0x1c200000
+#define LS1X_MUX_REG_BASE 0x1f000000
+
+#define LS1X_CFG_REG_BASE (LS1X_MUX_REG_BASE + 0x00d00000)
+
+#define LS1X_INTC_BASE (LS1X_CFG_REG_BASE + 0x1040)
+
+/* GPIO regs */
+#define LS1X_GPIO_REG_BASE (LS1X_CFG_REG_BASE + 0x1000)
+#define LS1X_GPIO_CFG0_REG (LS1X_GPIO_REG_BASE + 0xc0)
+#define LS1X_GPIO_CFG1_REG (LS1X_GPIO_REG_BASE + 0xc4)
+#define LS1X_GPIO_CFG2_REG (LS1X_GPIO_REG_BASE + 0xc8)
+#define LS1X_GPIO_OE0_REG (LS1X_GPIO_REG_BASE + 0xd0)
+#define LS1X_GPIO_OE1_REG (LS1X_GPIO_REG_BASE + 0xd4)
+#define LS1X_GPIO_OE2_REG (LS1X_GPIO_REG_BASE + 0xd8)
+#define LS1X_GPIO_IN0_REG (LS1X_GPIO_REG_BASE + 0xe0)
+#define LS1X_GPIO_IN1_REG (LS1X_GPIO_REG_BASE + 0xe4)
+#define LS1X_GPIO_IN2_REG (LS1X_GPIO_REG_BASE + 0xe8)
+#define LS1X_GPIO_OUT0_REG (LS1X_GPIO_REG_BASE + 0xf0)
+#define LS1X_GPIO_OUT1_REG (LS1X_GPIO_REG_BASE + 0xf4)
+#define LS1X_GPIO_OUT2_REG (LS1X_GPIO_REG_BASE + 0xf8)
+
+#define LS1X_DMA_ORDER_REG (LS1X_CFG_REG_BASE + 0x1160)
+
+#define LS1X_MUX_BASE (LS1X_CFG_REG_BASE + 0x0420)
+
+/* USB regs */
+#define LS1X_EHCI_BASE (LS1X_MUX_REG_BASE + 0x00e00000)
+#define LS1X_OHCI_BASE (LS1X_MUX_REG_BASE + 0x00e08000)
+
+/* GMAC regs */
+#define LS1X_GMAC0_BASE (LS1X_MUX_REG_BASE + 0x00e10000)
+#define LS1X_GMAC0_DMA_REG (LS1X_GMAC0_BASE + 0x1000)
+#define LS1X_GMAC1_BASE (LS1X_MUX_REG_BASE + 0x00e20000)
+#define LS1X_GMAC1_DMA_REG (LS1X_GMAC1_BASE + 0x1000)
+
+/* SATA regs */
+#define LS1X_AHCI_BASE (LS1X_MUX_REG_BASE + 0x00e30000)
+
+/* APB regs */
+#define LS1X_APB_REG_BASE (LS1X_MUX_REG_BASE + 0x00e40000)
+
+/* UART regs */
+#define LS1X_UART0_BASE (LS1X_APB_REG_BASE + 0x0000)
+#define LS1X_UART1_BASE (LS1X_APB_REG_BASE + 0x4000)
+#define LS1X_UART2_BASE (LS1X_APB_REG_BASE + 0x8000)
+#define LS1X_UART3_BASE (LS1X_APB_REG_BASE + 0xc000)
+
+/* CAN regs */
+#define LS1X_CAN0_BASE (LS1X_APB_REG_BASE + 0x10000)
+#define LS1X_CAN1_BASE (LS1X_APB_REG_BASE + 0x14000)
+
+#define LS1X_I2C0_BASE (LS1X_APB_REG_BASE + 0x18000)
+#define LS1X_I2C0_PRER_LO_REG (LS1X_I2C0_BASE + 0x0)
+#define LS1X_I2C0_PRER_HI_REG (LS1X_I2C0_BASE + 0x1)
+#define LS1X_I2C0_CTR_REG (LS1X_I2C0_BASE + 0x2)
+#define LS1X_I2C0_TXR_REG (LS1X_I2C0_BASE + 0x3)
+#define LS1X_I2C0_RXR_REG (LS1X_I2C0_BASE + 0x3)
+#define LS1X_I2C0_CR_REG (LS1X_I2C0_BASE + 0x4)
+#define LS1X_I2C0_SR_REG (LS1X_I2C0_BASE + 0x4)
+
+#define LS1X_I2C1_BASE (LS1X_APB_REG_BASE + 0x28000)
+#define LS1X_I2C1_PRER_LO_REG (LS1X_I2C1_BASE + 0x0)
+#define LS1X_I2C1_PRER_HI_REG (LS1X_I2C1_BASE + 0x1)
+#define LS1X_I2C1_CTR_REG (LS1X_I2C1_BASE + 0x2)
+#define LS1X_I2C1_TXR_REG (LS1X_I2C1_BASE + 0x3)
+#define LS1X_I2C1_RXR_REG (LS1X_I2C1_BASE + 0x3)
+#define LS1X_I2C1_CR_REG (LS1X_I2C1_BASE + 0x4)
+#define LS1X_I2C1_SR_REG (LS1X_I2C1_BASE + 0x4)
+
+#define LS1X_I2C2_BASE (LS1X_APB_REG_BASE + 0x30000)
+#define LS1X_I2C2_PRER_LO_REG (LS1X_I2C2_BASE + 0x0)
+#define LS1X_I2C2_PRER_HI_REG (LS1X_I2C2_BASE + 0x1)
+#define LS1X_I2C2_CTR_REG (LS1X_I2C2_BASE + 0x2)
+#define LS1X_I2C2_TXR_REG (LS1X_I2C2_BASE + 0x3)
+#define LS1X_I2C2_RXR_REG (LS1X_I2C2_BASE + 0x3)
+#define LS1X_I2C2_CR_REG (LS1X_I2C2_BASE + 0x4)
+#define LS1X_I2C2_SR_REG (LS1X_I2C2_BASE + 0x4)
+
+#define LS1X_PWM_REG_BASE (LS1X_APB_REG_BASE + 0x1c000)
+#define LS1X_PWM0_BASE (LS1X_PWM_REG_BASE + 0x00)
+#define LS1X_PWM1_BASE (LS1X_PWM_REG_BASE + 0x10)
+#define LS1X_PWM2_BASE (LS1X_PWM_REG_BASE + 0x20)
+#define LS1X_PWM3_BASE (LS1X_PWM_REG_BASE + 0x30)
+
+/* RTC regs */
+#define LS1X_RTC_BASE (LS1X_APB_REG_BASE + 0x24000)
+
+/* AC97 regs */
+#define LS1X_AC97_BASE (LS1X_APB_REG_BASE + 0x34000)
+
+/* Watchdog regs */
+#ifdef CONFIG_CPU_LOONGSON1A
+#define LS1X_WDT_BASE (LS1X_MUX_REG_BASE + 0x00e7c060)
+#else
+#define LS1X_WDT_BASE (LS1X_MUX_REG_BASE + 0x00e5c060)
+#endif
+
+/* CLK regs */
+#define LS1X_CLK_BASE (LS1X_MUX_REG_BASE + 0x00e78030)
+
+/* NAND regs */
+#define LS1X_NAND_REG_BASE (LS1X_APB_REG_BASE + 0x38000)
+#define LS1X_NAND_CMD_REG (LS1X_NAND_REG_BASE + 0x0000)
+#define LS1X_NAND_ADDR_C_REG (LS1X_NAND_REG_BASE + 0x0004)
+#define LS1X_NAND_ADDR_R_REG (LS1X_NAND_REG_BASE + 0x0008)
+#define LS1X_NAND_TIMING_REG (LS1X_NAND_REG_BASE + 0x000c)
+#define LS1X_NAND_IDL_REG (LS1X_NAND_REG_BASE + 0x0010)
+#define LS1X_NAND_STA_IDH_REG (LS1X_NAND_REG_BASE + 0x0014)
+#define LS1X_NAND_PARAM_REG (LS1X_NAND_REG_BASE + 0x0018)
+#define LS1X_NAND_OP_NUM_REG (LS1X_NAND_REG_BASE + 0x001c)
+#define LS1X_NAND_CSRDY_MAP_REG (LS1X_NAND_REG_BASE + 0x0020)
+#define LS1X_NAND_DMA_ACC_REG (LS1X_NAND_REG_BASE + 0x0040)
+
+/* ACPI regs for ls1a */
+#define LS1X_ACPI_REG_BASE (LS1X_APB_REG_BASE + 0x3c000)
+#define LS1X_PM1_STS_REG (LS1X_ACPI_REG_BASE + 0x0000)
+#define LS1X_PM1_EN_REG (LS1X_ACPI_REG_BASE + 0x0004)
+#define LS1X_PM1_CNT_REG (LS1X_ACPI_REG_BASE + 0x0008)
+#define LS1X_PM1_TMR_REG (LS1X_ACPI_REG_BASE + 0x000c)
+#define LS1X_P_CNT_REG (LS1X_ACPI_REG_BASE + 0x0010)
+#define LS1X_P_LVL2_REG (LS1X_ACPI_REG_BASE + 0x0014)
+#define LS1X_P_LVL3_REG (LS1X_ACPI_REG_BASE + 0x0018)
+#define LS1X_GPE0_STS_REG (LS1X_ACPI_REG_BASE + 0x0020)
+#define LS1X_GPE0_EN_REG (LS1X_ACPI_REG_BASE + 0x0024)
+#define LS1X_PM_CONF1_REG (LS1X_ACPI_REG_BASE + 0x0030)
+#define LS1X_PM_CONF2_REG (LS1X_ACPI_REG_BASE + 0x0034)
+#define LS1X_PM_CONF3_REG (LS1X_ACPI_REG_BASE + 0x0038)
+#define LS1X_RST_CNT_REG (LS1X_ACPI_REG_BASE + 0x0044)
+#define LS1X_CPU_INIT_REG (LS1X_ACPI_REG_BASE + 0x0050)
+
+#define LS1X_SPI0_REG_BASE (LS1X_MUX_REG_BASE + 0x00e80000)
+#define LS1X_SPI1_REG_BASE (LS1X_MUX_REG_BASE + 0x00ec0000)
+
+/* LPC regs */
+#define LS1X_LPC_IO_BASE (LS1X_MUX_REG_BASE + 0x00f00000)
+#define LS1X_LPC_REG_BASE (LS1X_MUX_REG_BASE + 0x00f10200)
+#define LS1X_LPC_CFG0_REG (LS1X_LPC_REG_BASE + 0x0)
+#define LS1X_LPC_CFG1_REG (LS1X_LPC_REG_BASE + 0x4)
+#define LS1X_LPC_CFG2_REG (LS1X_LPC_REG_BASE + 0x8)
+#define LS1X_LPC_CFG3_REG (LS1X_LPC_REG_BASE + 0xc)
#include <regs-clk.h>
#include <regs-mux.h>
diff --git a/arch/mips/include/asm/mach-loongson32/platform.h b/arch/mips/include/asm/mach-loongson32/platform.h
index c32f03f..f25398c 100644
--- a/arch/mips/include/asm/mach-loongson32/platform.h
+++ b/arch/mips/include/asm/mach-loongson32/platform.h
@@ -19,6 +19,17 @@ extern struct platform_device ls1x_eth0_pdev;
extern struct platform_device ls1x_eth1_pdev;
extern struct platform_device ls1x_ehci_pdev;
extern struct platform_device ls1x_rtc_pdev;
+extern struct platform_device ls1x_fb_pdev;
+extern struct platform_device ls1x_i2c0_pdev;
+extern struct platform_device ls1x_i2c1_pdev;
+extern struct platform_device ls1x_i2c2_pdev;
+extern struct platform_device ls1x_ahci_pdev;
+extern struct platform_device ls1x_ohci_pdev;
+extern struct platform_device ls1x_wat_pdev;
+extern struct platform_device ls1x_audio_pdev;
+extern struct platform_device ls1x_spi0_pdev;
+extern struct platform_device ls1x_spi1_pdev;
+extern struct platform_device ls1x_nand_pdev;
extern void __init ls1x_clk_init(void);
extern void __init ls1x_serial_setup(struct platform_device *pdev);
diff --git a/arch/mips/loongson32/common/platform.c b/arch/mips/loongson32/common/platform.c
index ddf1d4c..97d8c01 100644
--- a/arch/mips/loongson32/common/platform.c
+++ b/arch/mips/loongson32/common/platform.c
@@ -8,12 +8,27 @@
*/
#include <linux/clk.h>
+#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/err.h>
#include <linux/phy.h>
#include <linux/serial_8250.h>
#include <linux/stmmac.h>
#include <linux/usb/ehci_pdriver.h>
+#include <linux/usb/ohci_pdriver.h>
+#include <linux/platform_device.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/resource.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+#include <linux/i2c.h>
+#include <linux/delay.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/sizes.h>
#include <asm-generic/sizes.h>
#include <cpufreq.h>
@@ -23,6 +38,7 @@
#define LS1X_UART(_id) \
{ \
.mapbase = LS1X_UART ## _id ## _BASE, \
+ .membase = (u8 *)KSEG1ADDR(LS1X_UART ## _id ## _BASE), \
.irq = LS1X_UART ## _id ## _IRQ, \
.iotype = UPIO_MEM, \
.flags = UPF_IOREMAP | UPF_FIXED_TYPE, \
@@ -138,7 +154,9 @@ static struct plat_stmmacenet_data ls1x_eth0_pdata = {
.dma_cfg = &ls1x_eth_dma_cfg,
.has_gmac = 1,
.tx_coe = 1,
+#ifndef CONFIG_CPU_LOONGSON1A
.init = ls1x_eth_mux_init,
+#endif
};
static struct resource ls1x_eth0_resources[] = {
@@ -172,7 +190,9 @@ static struct plat_stmmacenet_data ls1x_eth1_pdata = {
.dma_cfg = &ls1x_eth_dma_cfg,
.has_gmac = 1,
.tx_coe = 1,
+#ifndef CONFIG_CPU_LOONGSON1A
.init = ls1x_eth_mux_init,
+#endif
};
static struct resource ls1x_eth1_resources[] = {
@@ -199,7 +219,7 @@ struct platform_device ls1x_eth1_pdev = {
};
/* USB EHCI */
-static u64 ls1x_ehci_dmamask = DMA_BIT_MASK(32);
+static u64 platform_dma_mask = DMA_BIT_MASK(32);
static struct resource ls1x_ehci_resources[] = {
[0] = {
@@ -222,13 +242,279 @@ struct platform_device ls1x_ehci_pdev = {
.num_resources = ARRAY_SIZE(ls1x_ehci_resources),
.resource = ls1x_ehci_resources,
.dev = {
- .dma_mask = &ls1x_ehci_dmamask,
+ .dma_mask = &platform_dma_mask,
.platform_data = &ls1x_ehci_pdata,
},
};
+/* USB OHCI */
+static struct resource ls1x_ohci_resources[] = {
+ [0] = {
+ .start = LS1X_OHCI_BASE,
+ .end = LS1X_OHCI_BASE + SZ_32K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = LS1X_OHCI_IRQ,
+ .end = LS1X_OHCI_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct usb_ohci_pdata ls1x_ohci_data = {
+};
+
+struct platform_device ls1x_ohci_pdev = {
+ .name = "ohci-platform",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(ls1x_ohci_resources),
+ .resource = ls1x_ohci_resources,
+ .dev = {
+ .dma_mask = &platform_dma_mask,
+ .platform_data = &ls1x_ohci_data,
+ },
+};
+
+/* AHCI */
+static struct resource ls1x_ahci_resources[] = {
+ [0] = {
+ .start = LS1X_AHCI_BASE,
+ .end = LS1X_AHCI_BASE + SZ_64K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = LS1X_AHCI_IRQ,
+ .end = LS1X_AHCI_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device ls1x_ahci_pdev = {
+ .name = "ahci",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(ls1x_ahci_resources),
+ .resource = ls1x_ahci_resources,
+ .dev = {
+ .dma_mask = &platform_dma_mask,
+ },
+};
+
/* Real Time Clock */
+static struct resource ls1x_rtc_resource[] = {
+ [0] = {
+ .start = LS1X_RTC_BASE,
+ .end = LS1X_RTC_BASE + SZ_16K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = LS1X_TOY_INT2_IRQ,
+ .end = LS1X_TOY_INT2_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
struct platform_device ls1x_rtc_pdev = {
.name = "ls1x-rtc",
.id = -1,
+ .num_resources = ARRAY_SIZE(ls1x_rtc_resource),
+ .resource = ls1x_rtc_resource,
+};
+
+/* FrameBuffer */
+static struct resource ls1x_fb_resources[] = {
+ [0] = {
+ .start = LS1X_DC_REG_BASE,
+ .end = LS1X_DC_REG_BASE + SZ_1M - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+struct platform_device ls1x_fb_pdev = {
+ .name = "ls1x-fb",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(ls1x_fb_resources),
+ .resource = ls1x_fb_resources,
+};
+
+/* I2C */
+static struct resource ls1x_i2c0_resource[] = {
+ [0] = {
+ .start = LS1X_I2C0_BASE,
+ .end = LS1X_I2C0_BASE + SZ_16K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+struct platform_device ls1x_i2c0_pdev = {
+ .name = "ls1x-i2c",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(ls1x_i2c0_resource),
+ .resource = ls1x_i2c0_resource,
+};
+
+static struct resource ls1x_i2c1_resource[] = {
+ [0] = {
+ .start = LS1X_I2C1_BASE,
+ .end = LS1X_I2C1_BASE + SZ_16K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+struct platform_device ls1x_i2c1_pdev = {
+ .name = "ls1x-i2c",
+ .id = 1,
+ .num_resources = ARRAY_SIZE(ls1x_i2c1_resource),
+ .resource = ls1x_i2c1_resource,
+};
+
+static struct resource ls1x_i2c2_resource[] = {
+ [0] = {
+ .start = LS1X_I2C2_BASE,
+ .end = LS1X_I2C2_BASE + SZ_16K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+struct platform_device ls1x_i2c2_pdev = {
+ .name = "ls1x-i2c",
+ .id = 2,
+ .num_resources = ARRAY_SIZE(ls1x_i2c2_resource),
+ .resource = ls1x_i2c2_resource,
+};
+
+/* Watchdog */
+static struct resource ls1x_wat_resource[] = {
+ [0] = {
+ .start = LS1X_WDT_BASE,
+ .end = LS1X_WDT_BASE + SZ_8,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+struct platform_device ls1x_wat_pdev = {
+ .name = "ls1x-wdt",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(ls1x_wat_resource),
+ .resource = ls1x_wat_resource,
+};
+
+/* NAND */
+struct ls1x_nand_platform_data {
+ int enable_arbiter;
+ struct mtd_partition *parts;
+ unsigned int nr_parts;
+};
+
+static struct mtd_partition ls1x_nand_partitions[] = {
+ [0] = {
+ .name = "kernel",
+ .offset = 0,
+ .size = 0x01400000,
+ },
+ [1] = {
+ .name = "os",
+ .offset = 0x01400000,
+ .size = 0x0,
+ },
+};
+
+static struct ls1x_nand_platform_data ls1x_nand_parts = {
+ .enable_arbiter = 1,
+ .parts = ls1x_nand_partitions,
+ .nr_parts = ARRAY_SIZE(ls1x_nand_partitions),
+};
+
+static struct resource ls1x_nand_resources[] = {
+ [0] = {
+ .start = 0,
+ .end = 0,
+ .flags = IORESOURCE_DMA,
+ },
+ [1] = {
+ .start = LS1X_NAND_REG_BASE,
+ .end = LS1X_NAND_REG_BASE + SZ_16K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [2] = {
+ .start = LS1X_DMA_ORDER_REG,
+ .end = LS1X_DMA_ORDER_REG,
+ .flags = IORESOURCE_MEM,
+ },
+ [3] = {
+ .start = LS1X_DMA0_IRQ,
+ .end = LS1X_DMA0_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device ls1x_nand_pdev = {
+ .name = "ls1x-nand",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(ls1x_nand_resources),
+ .resource = ls1x_nand_resources,
+ .dev = {
+ .platform_data = &ls1x_nand_parts,
+ },
+};
+
+/* AC97 Audio */
+static struct resource ls1x_audio_resources[] = {
+ [0] = {
+ .start = LS1X_AC97_BASE,
+ .end = LS1X_AC97_BASE + SZ_16K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = LS1X_AC97_IRQ,
+ .end = LS1X_AC97_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device ls1x_audio_pdev = {
+ .name = "ls1x-audio",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(ls1x_audio_resources),
+ .resource = ls1x_audio_resources,
+};
+
+/* SPI */
+static struct resource ls1x_spi0_resources[] = {
+ [1] = {
+ .start = LS1X_SPI0_REG_BASE,
+ .end = LS1X_SPI0_REG_BASE,
+ .flags = IORESOURCE_MEM,
+ },
+ [2] = {
+ .start = LS1X_SPI0_IRQ,
+ .end = LS1X_SPI0_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device ls1x_spi0_pdev = {
+ .name = "ls1x-spi",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(ls1x_spi0_resources),
+ .resource = ls1x_spi0_resources,
+};
+
+static struct resource ls1x_spi1_resources[] = {
+ [1] = {
+ .start = LS1X_SPI1_REG_BASE,
+ .end = LS1X_SPI1_REG_BASE,
+ .flags = IORESOURCE_MEM,
+ },
+ [2] = {
+ .start = LS1X_SPI1_IRQ,
+ .end = LS1X_SPI1_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device ls1x_spi1_pdev = {
+ .name = "ls1x-spi",
+ .id = 1,
+ .num_resources = ARRAY_SIZE(ls1x_spi1_resources),
+ .resource = ls1x_spi1_resources,
};
--
1.9.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v2 3/8] MIPS: Loongson: Add platform devices for Loongson-1A/1B
2015-06-17 10:32 ` [PATCH v2 3/8] MIPS: Loongson: Add platform devices for Loongson-1A/1B Binbin Zhou
@ 2015-08-03 15:21 ` Ralf Baechle
2015-08-04 3:15 ` Huacai Chen
0 siblings, 1 reply; 11+ messages in thread
From: Ralf Baechle @ 2015-08-03 15:21 UTC (permalink / raw)
To: Binbin Zhou
Cc: John Crispin, Steven J. Hill, linux-mips, Fuxin Zhang,
Zhangjin Wu, Kelvin Cheung, Chunbo Cui, Huacai Chen
On Wed, Jun 17, 2015 at 06:32:41PM +0800, Binbin Zhou wrote:
> arch/mips/loongson32/common/platform.c | 290 +++++++++++++++++++++-
Another lengthy platform.c file. Have you considered putting that
information into a DT instead?
Ralf
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 3/8] MIPS: Loongson: Add platform devices for Loongson-1A/1B
2015-08-03 15:21 ` Ralf Baechle
@ 2015-08-04 3:15 ` Huacai Chen
0 siblings, 0 replies; 11+ messages in thread
From: Huacai Chen @ 2015-08-04 3:15 UTC (permalink / raw)
To: Ralf Baechle
Cc: Binbin Zhou, John Crispin, Steven J. Hill,
Linux MIPS Mailing List, Fuxin Zhang, Zhangjin Wu, Kelvin Cheung,
Chunbo Cui
Unforunately, Loongson doesn't support device-tree now.
Huacai
On Mon, Aug 3, 2015 at 11:21 PM, Ralf Baechle <ralf@linux-mips.org> wrote:
> On Wed, Jun 17, 2015 at 06:32:41PM +0800, Binbin Zhou wrote:
>
>> arch/mips/loongson32/common/platform.c | 290 +++++++++++++++++++++-
>
> Another lengthy platform.c file. Have you considered putting that
> information into a DT instead?
>
> Ralf
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2 4/8] MIPS: Loongson: Add loongson-1A board support
2015-06-17 10:32 [PATCH v2 0/8] MIPS: Loongson: Add the Loongson-1A processor support Binbin Zhou
` (2 preceding siblings ...)
2015-06-17 10:32 ` [PATCH v2 3/8] MIPS: Loongson: Add platform devices for Loongson-1A/1B Binbin Zhou
@ 2015-06-17 10:32 ` Binbin Zhou
2015-06-17 10:32 ` [PATCH v2 5/8] MIPS: Loongson-1A: Workaround for pll register can't be read Binbin Zhou
` (3 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Binbin Zhou @ 2015-06-17 10:32 UTC (permalink / raw)
To: Ralf Baechle
Cc: John Crispin, Steven J. Hill, linux-mips, Fuxin Zhang,
Zhangjin Wu, Kelvin Cheung, Binbin Zhou, Chunbo Cui, Huacai Chen
Loongson 1A's platform devices register.
Specially, Loongson 1A use ACPI to control restart/poweroff/halt.
Signed-off-by: Chunbo Cui <cuicb@lemote.com>
Signed-off-by: Binbin Zhou <zhoubb@lemote.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
arch/mips/include/asm/mach-loongson32/loongson1.h | 8 ++
arch/mips/loongson32/Makefile | 6 ++
arch/mips/loongson32/common/reset.c | 6 ++
arch/mips/loongson32/common/setup.c | 38 +++++++-
arch/mips/loongson32/ls1a/Makefile | 5 ++
arch/mips/loongson32/ls1a/board.c | 105 ++++++++++++++++++++++
6 files changed, 167 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/loongson32/ls1a/Makefile
create mode 100644 arch/mips/loongson32/ls1a/board.c
diff --git a/arch/mips/include/asm/mach-loongson32/loongson1.h b/arch/mips/include/asm/mach-loongson32/loongson1.h
index 5c1ba48..3061e64 100644
--- a/arch/mips/include/asm/mach-loongson32/loongson1.h
+++ b/arch/mips/include/asm/mach-loongson32/loongson1.h
@@ -157,6 +157,14 @@
#define LS1X_LPC_CFG2_REG (LS1X_LPC_REG_BASE + 0x8)
#define LS1X_LPC_CFG3_REG (LS1X_LPC_REG_BASE + 0xc)
+/* reg access */
+#define ls1x_readb(addr) (*(volatile u8 *)CKSEG1ADDR(addr))
+#define ls1x_readw(addr) (*(volatile u16 *)CKSEG1ADDR(addr))
+#define ls1x_readl(addr) (*(volatile u32 *)CKSEG1ADDR(addr))
+#define ls1x_writeb(val, addr) (*(volatile u8 *)CKSEG1ADDR(addr) = (val))
+#define ls1x_writew(val, addr) (*(volatile u16 *)CKSEG1ADDR(addr) = (val))
+#define ls1x_writel(val, addr) (*(volatile u32 *)CKSEG1ADDR(addr) = (val))
+
#include <regs-clk.h>
#include <regs-mux.h>
#include <regs-pwm.h>
diff --git a/arch/mips/loongson32/Makefile b/arch/mips/loongson32/Makefile
index 5f4bd6e..c2a6559 100644
--- a/arch/mips/loongson32/Makefile
+++ b/arch/mips/loongson32/Makefile
@@ -5,6 +5,12 @@
obj-$(CONFIG_MACH_LOONGSON32) += common/
#
+# Loongson LS1A board
+#
+
+obj-$(CONFIG_LOONGSON1_LS1A) += ls1a/
+
+#
# Loongson LS1B board
#
diff --git a/arch/mips/loongson32/common/reset.c b/arch/mips/loongson32/common/reset.c
index c41e4ca..71630fd 100644
--- a/arch/mips/loongson32/common/reset.c
+++ b/arch/mips/loongson32/common/reset.c
@@ -18,10 +18,14 @@ static void __iomem *wdt_base;
static void ls1x_halt(void)
{
+#ifdef CONFIG_CPU_LOONGSON1A
+ ls1x_writel(ls1x_readl(LS1X_PM1_CNT_REG) | 0x3d00, LS1X_PM1_CNT_REG);
+#else
while (1) {
if (cpu_wait)
cpu_wait();
}
+#endif
}
static void ls1x_restart(char *command)
@@ -30,7 +34,9 @@ static void ls1x_restart(char *command)
__raw_writel(0x1, wdt_base + WDT_TIMER);
__raw_writel(0x1, wdt_base + WDT_SET);
+#ifndef CONFIG_CPU_LOONGSON1A
ls1x_halt();
+#endif
}
static void ls1x_power_off(void)
diff --git a/arch/mips/loongson32/common/setup.c b/arch/mips/loongson32/common/setup.c
index c3d2036..87d21c9 100644
--- a/arch/mips/loongson32/common/setup.c
+++ b/arch/mips/loongson32/common/setup.c
@@ -8,12 +8,48 @@
*/
#include <asm/bootinfo.h>
-
+#include <linux/ioport.h>
+#include <linux/screen_info.h>
#include <prom.h>
+void (*__wbflush)(void);
+static void wbflush_ls1x(void)
+{
+ asm(".set\tpush\n\t"
+ ".set\tnoreorder\n\t"
+ ".set mips3\n\t"
+ "sync\n\t"
+ "nop\n\t"
+ ".set\tpop\n\t"
+ ".set mips0\n\t");
+}
+
void __init plat_mem_setup(void)
{
add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM);
+
+#ifdef CONFIG_CPU_LOONGSON1A
+ ioport_resource.start = 0;
+ ioport_resource.end = 0xffffffff;
+ iomem_resource.start = 0;
+ iomem_resource.end = 0xffffffff;
+
+ __wbflush = wbflush_ls1x;
+
+ set_io_port_base(0xbc000000);
+
+#if defined(CONFIG_VGA_CONSOLE)
+ screen_info = (struct screen_info) {
+ .orig_x = 0,
+ .orig_y = 25,
+ .orig_video_cols = 80,
+ .orig_video_lines = 25,
+ .orig_video_isVGA = VIDEO_TYPE_VGAC,
+ .orig_video_points = 16,
+ };
+#endif
+ add_memory_region(0x20000000, 0x30000000, BOOT_MEM_RESERVED);
+#endif
}
const char *get_system_type(void)
diff --git a/arch/mips/loongson32/ls1a/Makefile b/arch/mips/loongson32/ls1a/Makefile
new file mode 100644
index 0000000..7f2baf3
--- /dev/null
+++ b/arch/mips/loongson32/ls1a/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for Loongson 1A based machines.
+#
+
+obj-y += board.o
diff --git a/arch/mips/loongson32/ls1a/board.c b/arch/mips/loongson32/ls1a/board.c
new file mode 100644
index 0000000..98fb86c
--- /dev/null
+++ b/arch/mips/loongson32/ls1a/board.c
@@ -0,0 +1,105 @@
+/*
+ * Platform device support for GS232 SoCs.
+ *
+ * Copyright 2009, Su Wen <suwen@ict.ac.cn>
+ *
+ * base on Au1xxx Socs drivers by Matt Porter <mporter@kernel.crashing.org>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+
+#include <irq.h>
+#include <platform.h>
+#include <loongson1.h>
+
+static struct platform_device *ls1a_platform_devices[] __initdata = {
+ &ls1x_nand_pdev,
+ &ls1x_uart_pdev,
+ &ls1x_ahci_pdev,
+ &ls1x_ohci_pdev,
+ &ls1x_ehci_pdev,
+ &ls1x_eth0_pdev,
+ &ls1x_eth1_pdev,
+ &ls1x_wat_pdev,
+ &ls1x_rtc_pdev,
+ &ls1x_audio_pdev,
+ &ls1x_fb_pdev,
+ &ls1x_i2c0_pdev,
+ &ls1x_i2c1_pdev,
+ &ls1x_i2c2_pdev,
+ &ls1x_spi0_pdev,
+ &ls1x_spi1_pdev,
+};
+
+struct i2c_board_info ls1a_pcf8563 __initdata = {
+ I2C_BOARD_INFO("pcf8563", 0x51),
+};
+
+struct flash_platform_data ls1a_spiflash_data = {
+ .name = "m25p80",
+ .parts = NULL,
+ .nr_parts = 0,
+ .type = "m25p80",
+};
+
+struct spi_board_info ls1a_spi_info[] __initdata = {
+ {
+ .modalias = "m25p80",
+ .max_speed_hz = 1000000,
+ .bus_num = 0,
+ .chip_select = 1,
+ .platform_data = &ls1a_spiflash_data,
+ },
+};
+
+void ls1a_route_setting(void)
+{
+ /*set gpio 48-61 as normal pin*/
+ ls1x_writel(ls1x_readl(LS1X_GPIO_CFG1_REG) & 0xc000ffff,
+ LS1X_GPIO_CFG1_REG);
+
+ /*set gpio mux : gmac1 to use uart0, uart1 pins*/
+ ls1x_writel((ls1x_readl(LS1X_MUX_BASE) & 0x00fff5ff) | 0x0a0000c0,
+ LS1X_GPIO_CFG1_REG);
+
+ /*multiplex int0 as gpio0 */
+ ls1x_writel(ls1x_readl(LS1X_GPIO_CFG0_REG) | 0x00000001,
+ LS1X_GPIO_CFG0_REG);
+ ls1x_writel(ls1x_readl(LS1X_GPIO_OE0_REG) | 0x00000001,
+ LS1X_GPIO_OE0_REG);
+ ls1x_writel(ls1x_readl(LS1X_GPIO_IN0_REG) & 0xfffffffe,
+ LS1X_GPIO_IN0_REG);
+
+ /*i2c gpio configuartion gpio64 scl and gpio65 sda*/
+ ls1x_writel(ls1x_readl(LS1X_GPIO_CFG2_REG) & 0xfffffffd,
+ LS1X_GPIO_CFG2_REG);
+
+ mdelay(1);
+
+ /*ls1a usb reset stop*/
+ ls1x_writel(0x40000000, LS1X_LPC_CFG1_REG);
+
+ /* Reset GMAC0/1 to avoid DMA error */
+ ls1x_writel(ls1x_readl(LS1X_GMAC0_DMA_REG) | 1, LS1X_GMAC0_DMA_REG);
+ ls1x_writel(ls1x_readl(LS1X_GMAC1_DMA_REG) | 1, LS1X_GMAC1_DMA_REG);
+}
+
+int __init ls1a_platform_init(void)
+{
+ ls1a_route_setting();
+
+ i2c_register_board_info(1, &ls1a_pcf8563, 1);
+ spi_register_board_info(ls1a_spi_info, ARRAY_SIZE(ls1a_spi_info));
+
+ return platform_add_devices(ls1a_platform_devices,
+ ARRAY_SIZE(ls1a_platform_devices));
+}
+
+arch_initcall(ls1a_platform_init);
--
1.9.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v2 5/8] MIPS: Loongson-1A: Workaround for pll register can't be read
2015-06-17 10:32 [PATCH v2 0/8] MIPS: Loongson: Add the Loongson-1A processor support Binbin Zhou
` (3 preceding siblings ...)
2015-06-17 10:32 ` [PATCH v2 4/8] MIPS: Loongson: Add loongson-1A board support Binbin Zhou
@ 2015-06-17 10:32 ` Binbin Zhou
2015-06-17 10:32 ` [PATCH v2 6/8] MIPS: Loongson-1A: Add IRQ type setting support Binbin Zhou
` (2 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Binbin Zhou @ 2015-06-17 10:32 UTC (permalink / raw)
To: Ralf Baechle
Cc: John Crispin, Steven J. Hill, linux-mips, Fuxin Zhang,
Zhangjin Wu, Kelvin Cheung, Binbin Zhou, Chunbo Cui, Huacai Chen
This is Loongson 1A's bug that the pll register can't be read,
so we set the cpu clk in the inline command line.
The command line format is cpu_clk=osc_clk,cpu_mul,
the osc_clk standby cpu clock and the cpu_mul repect the clock multiplier.
For example, we use the command is cpu_clk=33333333,8
Signed-off-by: Chunbo Cui <cuicb@lemote.com>
Signed-off-by: Binbin Zhou <zhoubb@lemote.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
arch/mips/include/asm/mach-loongson32/loongson1.h | 2 ++
arch/mips/loongson32/common/platform.c | 8 +++++++-
arch/mips/loongson32/common/time.c | 16 ++++++++++++++++
arch/mips/loongson32/ls1a/board.c | 2 ++
drivers/clk/clk-ls1x.c | 19 +++++++++++++++----
5 files changed, 42 insertions(+), 5 deletions(-)
diff --git a/arch/mips/include/asm/mach-loongson32/loongson1.h b/arch/mips/include/asm/mach-loongson32/loongson1.h
index 3061e64..82f951e 100644
--- a/arch/mips/include/asm/mach-loongson32/loongson1.h
+++ b/arch/mips/include/asm/mach-loongson32/loongson1.h
@@ -165,6 +165,8 @@
#define ls1x_writew(val, addr) (*(volatile u16 *)CKSEG1ADDR(addr) = (val))
#define ls1x_writel(val, addr) (*(volatile u32 *)CKSEG1ADDR(addr) = (val))
+extern unsigned int ls1a_osc_clk, ls1a_cpu_mul;
+
#include <regs-clk.h>
#include <regs-mux.h>
#include <regs-pwm.h>
diff --git a/arch/mips/loongson32/common/platform.c b/arch/mips/loongson32/common/platform.c
index 97d8c01..a5bb1eb 100644
--- a/arch/mips/loongson32/common/platform.c
+++ b/arch/mips/loongson32/common/platform.c
@@ -63,9 +63,14 @@ struct platform_device ls1x_uart_pdev = {
void __init ls1x_serial_setup(struct platform_device *pdev)
{
- struct clk *clk;
struct plat_serial8250_port *p;
+#ifdef CONFIG_CPU_LOONGSON1A
+ for (p = pdev->dev.platform_data; p->flags != 0; ++p)
+ p->uartclk = ls1a_osc_clk * 2;
+#else
+ struct clk *clk;
+
clk = clk_get(&pdev->dev, pdev->name);
if (IS_ERR(clk)) {
pr_err("unable to get %s clock, err=%ld",
@@ -76,6 +81,7 @@ void __init ls1x_serial_setup(struct platform_device *pdev)
for (p = pdev->dev.platform_data; p->flags != 0; ++p)
p->uartclk = clk_get_rate(clk);
+#endif
}
/* CPUFreq */
diff --git a/arch/mips/loongson32/common/time.c b/arch/mips/loongson32/common/time.c
index df0f850..01d3950 100644
--- a/arch/mips/loongson32/common/time.c
+++ b/arch/mips/loongson32/common/time.c
@@ -224,3 +224,19 @@ void __init plat_time_init(void)
mips_hpt_frequency = clk_get_rate(clk) / 2;
#endif /* CONFIG_CEVT_CSRC_LS1X */
}
+
+#ifdef CONFIG_CPU_LOONGSON1A
+unsigned int ls1a_osc_clk = 0, ls1a_cpu_mul = 0;
+
+static int __init get_cpu_clk(char *string)
+{
+ int ret;
+
+ ret = sscanf(string, "%u,%u", &ls1a_osc_clk, &ls1a_cpu_mul);
+ if (ret != 1)
+ return -EINVAL;
+
+ return 1;
+}
+__setup("cpu_clk=", get_cpu_clk);
+#endif
diff --git a/arch/mips/loongson32/ls1a/board.c b/arch/mips/loongson32/ls1a/board.c
index 98fb86c..9c53ecc 100644
--- a/arch/mips/loongson32/ls1a/board.c
+++ b/arch/mips/loongson32/ls1a/board.c
@@ -95,6 +95,8 @@ int __init ls1a_platform_init(void)
{
ls1a_route_setting();
+ ls1x_serial_setup(&ls1x_uart_pdev);
+
i2c_register_board_info(1, &ls1a_pcf8563, 1);
spi_register_board_info(ls1a_spi_info, ARRAY_SIZE(ls1a_spi_info));
diff --git a/drivers/clk/clk-ls1x.c b/drivers/clk/clk-ls1x.c
index ca80103..93eda9e 100644
--- a/drivers/clk/clk-ls1x.c
+++ b/drivers/clk/clk-ls1x.c
@@ -32,6 +32,14 @@ static void ls1x_pll_clk_disable(struct clk_hw *hw)
static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
+#ifdef CONFIG_CPU_LOONGSON1A
+ /* workaround, loongson 1A pll register can't be read,
+ * on gateway board, multi is set to 11 */
+ if (ls1a_osc_clk != 0 && ls1a_cpu_mul != 0)
+ return ls1a_osc_clk * ls1a_cpu_mul;
+ else
+ return 33333333 * 8;
+#else
u32 pll, rate;
pll = __raw_readl(LS1X_CLK_PLL_FREQ);
@@ -40,6 +48,7 @@ static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
rate >>= 1;
return rate;
+#endif
}
static const struct clk_ops ls1x_pll_clk_ops = {
@@ -107,7 +116,8 @@ void __init ls1x_clk_init(void)
CLK_GET_RATE_NOCACHE, LS1X_CLK_PLL_DIV,
DIV_CPU_SHIFT, DIV_CPU_WIDTH,
CLK_DIVIDER_ONE_BASED |
- CLK_DIVIDER_ROUND_CLOSEST, &_lock);
+ CLK_DIVIDER_ROUND_CLOSEST |
+ CLK_DIVIDER_ALLOW_ZERO, &_lock);
clk_register_clkdev(clk, "cpu_clk_div", NULL);
clk = clk_register_mux(NULL, "cpu_clk", cpu_parents,
ARRAY_SIZE(cpu_parents),
@@ -123,7 +133,8 @@ void __init ls1x_clk_init(void)
*/
clk = clk_register_divider(NULL, "dc_clk_div", "pll_clk",
0, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
- DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
+ DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED |
+ CLK_DIVIDER_ALLOW_ZERO, &_lock);
clk_register_clkdev(clk, "dc_clk_div", NULL);
clk = clk_register_mux(NULL, "dc_clk", dc_parents,
ARRAY_SIZE(dc_parents),
@@ -139,8 +150,8 @@ void __init ls1x_clk_init(void)
*/
clk = clk_register_divider(NULL, "ahb_clk_div", "pll_clk",
0, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT,
- DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED,
- &_lock);
+ DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED |
+ CLK_DIVIDER_ALLOW_ZERO, &_lock);
clk_register_clkdev(clk, "ahb_clk_div", NULL);
clk = clk_register_mux(NULL, "ahb_clk", ahb_parents,
ARRAY_SIZE(ahb_parents),
--
1.9.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v2 6/8] MIPS: Loongson-1A: Add IRQ type setting support
2015-06-17 10:32 [PATCH v2 0/8] MIPS: Loongson: Add the Loongson-1A processor support Binbin Zhou
` (4 preceding siblings ...)
2015-06-17 10:32 ` [PATCH v2 5/8] MIPS: Loongson-1A: Workaround for pll register can't be read Binbin Zhou
@ 2015-06-17 10:32 ` Binbin Zhou
2015-06-17 10:32 ` [PATCH v2 7/8] MIPS: Loongson-1A: Enable SPARSEMEN and HIGHMEM Binbin Zhou
2015-06-17 10:32 ` [PATCH v2 8/8] MIPS: Loongson: Add a Loongson-1A default config file Binbin Zhou
7 siblings, 0 replies; 11+ messages in thread
From: Binbin Zhou @ 2015-06-17 10:32 UTC (permalink / raw)
To: Ralf Baechle
Cc: John Crispin, Steven J. Hill, linux-mips, Fuxin Zhang,
Zhangjin Wu, Kelvin Cheung, Binbin Zhou, Chunbo Cui, Huacai Chen
Loongson 1A's INT controller support two different interrupt trigger mode:
level trigger and edge trigger.
Whether the INT controller stores the external interrupts is
the difference between them.
The edge trigger should do this, and operate INT_CLR register
to clear the CPU interrupt state.
Signed-off-by: Chunbo Cui <cuicb@lemote.com>
Signed-off-by: Binbin Zhou <zhoubb@lemote.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
arch/mips/loongson32/common/irq.c | 46 +++++++++++++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/arch/mips/loongson32/common/irq.c b/arch/mips/loongson32/common/irq.c
index 455a770..76dd185 100644
--- a/arch/mips/loongson32/common/irq.c
+++ b/arch/mips/loongson32/common/irq.c
@@ -62,12 +62,57 @@ static void ls1x_irq_unmask(struct irq_data *d)
| (1 << bit), LS1X_INTC_INTIEN(n));
}
+static int ls1x_irq_set_type(struct irq_data *d, unsigned int flow_type)
+{
+ unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f;
+ unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5;
+
+ if (flow_type & IRQ_TYPE_EDGE_BOTH) {
+ if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
+ pr_info("ls1x irq don't support both rising and falling\n");
+ return -1;
+ }
+ ls1x_writel(ls1x_readl(LS1X_INTC_INTCLR(n))
+ | (1 << bit), LS1X_INTC_INTCLR(n));
+ if (flow_type & IRQ_TYPE_EDGE_RISING)
+ ls1x_writel(ls1x_readl(LS1X_INTC_INTPOL(n))
+ | (1 << bit), LS1X_INTC_INTPOL(n));
+ else
+ ls1x_writel(ls1x_readl(LS1X_INTC_INTPOL(n))
+ & ~(1 << bit), LS1X_INTC_INTPOL(n));
+
+ ls1x_writel(ls1x_readl(LS1X_INTC_INTEDGE(n))
+ | (1 << bit), LS1X_INTC_INTEDGE(n));
+ ls1x_writel(ls1x_readl(LS1X_INTC_INTIEN(n))
+ | (1 << bit), LS1X_INTC_INTIEN(n));
+ __irq_set_handler_locked(d->irq, handle_edge_irq);
+ } else if (flow_type && IRQ_TYPE_LEVEL_MASK) {
+ ls1x_writel(ls1x_readl(LS1X_INTC_INTCLR(n))
+ | (1 << bit), LS1X_INTC_INTCLR(n));
+ if (flow_type & IRQ_TYPE_LEVEL_HIGH)
+ ls1x_writel(ls1x_readl(LS1X_INTC_INTPOL(n))
+ | (1 << bit), LS1X_INTC_INTPOL(n));
+ else if (flow_type & IRQ_TYPE_LEVEL_LOW)
+ ls1x_writel(ls1x_readl(LS1X_INTC_INTPOL(n))
+ & ~(1 << bit), LS1X_INTC_INTPOL(n));
+
+ ls1x_writel(ls1x_readl(LS1X_INTC_INTEDGE(n))
+ & ~(1 << bit), LS1X_INTC_INTEDGE(n));
+ ls1x_writel(ls1x_readl(LS1X_INTC_INTIEN(n))
+ | (1 << bit), LS1X_INTC_INTIEN(n));
+ __irq_set_handler_locked(d->irq, handle_level_irq);
+ }
+
+ return IRQ_SET_MASK_OK;
+}
+
static struct irq_chip ls1x_irq_chip = {
.name = "LS1X-INTC",
.irq_ack = ls1x_irq_ack,
.irq_mask = ls1x_irq_mask,
.irq_mask_ack = ls1x_irq_mask_ack,
.irq_unmask = ls1x_irq_unmask,
+ .irq_set_type = ls1x_irq_set_type,
};
static void ls1x_irq_dispatch(int n)
@@ -138,6 +183,7 @@ static void __init ls1x_irq_init(int base)
setup_irq(INT1_IRQ, &cascade_irqaction);
setup_irq(INT2_IRQ, &cascade_irqaction);
setup_irq(INT3_IRQ, &cascade_irqaction);
+ setup_irq(INT4_IRQ, &cascade_irqaction);
}
void __init arch_init_irq(void)
--
1.9.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v2 7/8] MIPS: Loongson-1A: Enable SPARSEMEN and HIGHMEM
2015-06-17 10:32 [PATCH v2 0/8] MIPS: Loongson: Add the Loongson-1A processor support Binbin Zhou
` (5 preceding siblings ...)
2015-06-17 10:32 ` [PATCH v2 6/8] MIPS: Loongson-1A: Add IRQ type setting support Binbin Zhou
@ 2015-06-17 10:32 ` Binbin Zhou
2015-06-17 10:32 ` [PATCH v2 8/8] MIPS: Loongson: Add a Loongson-1A default config file Binbin Zhou
7 siblings, 0 replies; 11+ messages in thread
From: Binbin Zhou @ 2015-06-17 10:32 UTC (permalink / raw)
To: Ralf Baechle
Cc: John Crispin, Steven J. Hill, linux-mips, Fuxin Zhang,
Zhangjin Wu, Kelvin Cheung, Binbin Zhou, Chunbo Cui, Huacai Chen
Signed-off-by: Chunbo Cui <cuicb@lemote.com>
Signed-off-by: Binbin Zhou <zhoubb@lemote.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
arch/mips/include/asm/sparsemem.h | 6 +++++-
arch/mips/loongson32/Kconfig | 1 +
arch/mips/loongson32/common/setup.c | 3 ++-
3 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/mips/include/asm/sparsemem.h b/arch/mips/include/asm/sparsemem.h
index b1071c1..f73e671 100644
--- a/arch/mips/include/asm/sparsemem.h
+++ b/arch/mips/include/asm/sparsemem.h
@@ -11,7 +11,11 @@
#else
# define SECTION_SIZE_BITS 28
#endif
-#define MAX_PHYSMEM_BITS 48
+#ifdef CONFIG_64BIT
+# define MAX_PHYSMEM_BITS 48
+#else
+# define MAX_PHYSMEM_BITS 36
+#endif
#endif /* CONFIG_SPARSEMEM */
#endif /* _MIPS_SPARSEMEM_H */
diff --git a/arch/mips/loongson32/Kconfig b/arch/mips/loongson32/Kconfig
index 741867c..5a96672 100644
--- a/arch/mips/loongson32/Kconfig
+++ b/arch/mips/loongson32/Kconfig
@@ -11,6 +11,7 @@ config LOONGSON1_LS1A
bool "Loongson LS1A board"
select CEVT_R4K
select CSRC_R4K
+ select ARCH_SPARSEMEM_ENABLE
select SYS_HAS_CPU_LOONGSON1A
select DMA_NONCOHERENT
select BOOT_ELF32
diff --git a/arch/mips/loongson32/common/setup.c b/arch/mips/loongson32/common/setup.c
index 87d21c9..d764fae 100644
--- a/arch/mips/loongson32/common/setup.c
+++ b/arch/mips/loongson32/common/setup.c
@@ -48,7 +48,8 @@ void __init plat_mem_setup(void)
.orig_video_points = 16,
};
#endif
- add_memory_region(0x20000000, 0x30000000, BOOT_MEM_RESERVED);
+ if (highmemsize > 0)
+ add_memory_region(0x50000000, highmemsize << 20, BOOT_MEM_RAM);
#endif
}
--
1.9.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v2 8/8] MIPS: Loongson: Add a Loongson-1A default config file
2015-06-17 10:32 [PATCH v2 0/8] MIPS: Loongson: Add the Loongson-1A processor support Binbin Zhou
` (6 preceding siblings ...)
2015-06-17 10:32 ` [PATCH v2 7/8] MIPS: Loongson-1A: Enable SPARSEMEN and HIGHMEM Binbin Zhou
@ 2015-06-17 10:32 ` Binbin Zhou
7 siblings, 0 replies; 11+ messages in thread
From: Binbin Zhou @ 2015-06-17 10:32 UTC (permalink / raw)
To: Ralf Baechle
Cc: John Crispin, Steven J. Hill, linux-mips, Fuxin Zhang,
Zhangjin Wu, Kelvin Cheung, Binbin Zhou, Chunbo Cui, Huacai Chen
Signed-off-by: Chunbo Cui <cuicb@lemote.com>
Signed-off-by: Binbin Zhou <zhoubb@lemote.com>
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
arch/mips/configs/ls1a_defconfig | 136 +++++++++++++++++++++++++++++++++++++++
1 file changed, 136 insertions(+)
create mode 100644 arch/mips/configs/ls1a_defconfig
diff --git a/arch/mips/configs/ls1a_defconfig b/arch/mips/configs/ls1a_defconfig
new file mode 100644
index 0000000..116d450
--- /dev/null
+++ b/arch/mips/configs/ls1a_defconfig
@@ -0,0 +1,136 @@
+CONFIG_MACH_LOONGSON32=y
+CONFIG_ZONE_DMA=y
+CONFIG_PAGE_SIZE_16KB=y
+CONFIG_HIGHMEM=y
+CONFIG_HZ_1000=y
+CONFIG_PREEMPT_VOLUNTARY=y
+# CONFIG_SECCOMP is not set
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+# CONFIG_USELIB is not set
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CPUSETS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_BLK_CGROUP=y
+CONFIG_EXPERT=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+# CONFIG_BRIDGE_IGMP_SNOOPING is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_NFTL=y
+CONFIG_NFTL_RW=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=y
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_ATA=y
+# CONFIG_SATA_PMP is not set
+CONFIG_SATA_AHCI_PLATFORM=y
+# CONFIG_ATA_SFF is not set
+CONFIG_NETDEVICES=y
+CONFIG_NETCONSOLE=y
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+CONFIG_STMMAC_ETH=y
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_REALTEK_PHY=y
+# CONFIG_USB_NET_DRIVERS is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_LEGACY_PTY_COUNT=8
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_MON=y
+CONFIG_USB_XHCI_HCD=m
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_STORAGE=m
+CONFIG_USB_GADGET=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_PCF8563=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+# CONFIG_DNOTIFY is not set
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_MISC_FILESYSTEMS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_PRINTK_TIME=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_FTRACE is not set
+CONFIG_XZ_DEC=y
--
1.9.0
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