From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.71) id 1ZMbFj-00040b-Co for mharc-qemu-trivial@gnu.org; Tue, 04 Aug 2015 08:23:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51469) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZMbFg-0003x4-O3 for qemu-trivial@nongnu.org; Tue, 04 Aug 2015 08:23:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZMbFa-0000rg-SL for qemu-trivial@nongnu.org; Tue, 04 Aug 2015 08:23:28 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:40867) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZMbFX-0000nK-QZ; Tue, 04 Aug 2015 08:23:19 -0400 Received: from weber.rr44.fr ([2001:bc8:30d7:120:7e05:7ff:fe0d:f152]) by hall.aurel32.net with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.84) (envelope-from ) id 1ZMbFV-0007f0-3q; Tue, 04 Aug 2015 14:23:17 +0200 Received: from aurel32 by weber.rr44.fr with local (Exim 4.85) (envelope-from ) id 1ZMbFU-0002Ns-D8; Tue, 04 Aug 2015 14:23:16 +0200 Date: Tue, 4 Aug 2015 14:23:16 +0200 From: Aurelien Jarno To: Alex =?iso-8859-15?Q?Benn=E9e?= Message-ID: <20150804122316.GA8918@aurel32.net> References: <1438593291-27109-1-git-send-email-alex.bennee@linaro.org> <1438593291-27109-10-git-send-email-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable In-Reply-To: <1438593291-27109-10-git-send-email-alex.bennee@linaro.org> User-Agent: Mutt/1.5.23 (2014-03-12) X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:bc8:30d7:100::1 Cc: Peter Maydell , qemu-trivial@nongnu.org, qemu-devel@nongnu.org, crosthwaitepeter@gmail.com, pbonzini@redhat.com, rth@twiddle.net Subject: Re: [Qemu-trivial] [PATCH v4 09/11] target-arm: dfilter support for in_asm, op, opt_op X-BeenThere: qemu-trivial@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 04 Aug 2015 12:23:29 -0000 On 2015-08-03 10:14, Alex Benn=E9e wrote: > Each individual architecture needs to use the qemu_log_in_addr_range() > feature for enabling in_asm and marking blocks for op/opt_op output. >=20 > Signed-off-by: Alex Benn=E9e > --- > target-arm/translate-a64.c | 6 ++++-- > target-arm/translate.c | 6 ++++-- > 2 files changed, 8 insertions(+), 4 deletions(-) >=20 > diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c > index 689f2be..0b0f4ae 100644 > --- a/target-arm/translate-a64.c > +++ b/target-arm/translate-a64.c > @@ -11026,7 +11026,8 @@ void gen_intermediate_code_internal_a64(ARMCPU *c= pu, > gen_io_start(); > } > =20 > - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OP= T))) { > + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OP= T) && > + qemu_log_in_addr_range(dc->pc))) { > tcg_gen_debug_insn_start(dc->pc); > } > =20 > @@ -11131,7 +11132,8 @@ done_generating: > gen_tb_end(tb, num_insns); > =20 > #ifdef DEBUG_DISAS > - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { > + if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && > + qemu_log_in_addr_range(pc_start)) { > qemu_log("----------------\n"); > qemu_log("IN: %s\n", lookup_symbol(pc_start)); > log_target_disas(cs, pc_start, dc->pc - pc_start, > diff --git a/target-arm/translate.c b/target-arm/translate.c > index 69ac18c..c914be0 100644 > --- a/target-arm/translate.c > +++ b/target-arm/translate.c > @@ -11316,7 +11316,8 @@ static inline void gen_intermediate_code_internal= (ARMCPU *cpu, > if (num_insns + 1 =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) > gen_io_start(); > =20 > - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OP= T))) { > + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OP= T)) && > + qemu_log_in_addr_range(dc->pc)) { > tcg_gen_debug_insn_start(dc->pc); > } > =20 > @@ -11489,7 +11490,8 @@ done_generating: > gen_tb_end(tb, num_insns); > =20 > #ifdef DEBUG_DISAS > - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { > + if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && > + qemu_log_in_addr_range(pc_start)) { > qemu_log("----------------\n"); > qemu_log("IN: %s\n", lookup_symbol(pc_start)); > log_target_disas(cs, pc_start, dc->pc - pc_start, We probably want to do the same for the other architectures. Reviewed-by: Aurelien Jarno --=20 Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://www.aurel32.net From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51435) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZMbFZ-0003pe-QG for qemu-devel@nongnu.org; Tue, 04 Aug 2015 08:23:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZMbFY-0000nO-0L for qemu-devel@nongnu.org; Tue, 04 Aug 2015 08:23:21 -0400 Date: Tue, 4 Aug 2015 14:23:16 +0200 From: Aurelien Jarno Message-ID: <20150804122316.GA8918@aurel32.net> References: <1438593291-27109-1-git-send-email-alex.bennee@linaro.org> <1438593291-27109-10-git-send-email-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable In-Reply-To: <1438593291-27109-10-git-send-email-alex.bennee@linaro.org> Subject: Re: [Qemu-devel] [PATCH v4 09/11] target-arm: dfilter support for in_asm, op, opt_op List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alex =?iso-8859-15?Q?Benn=E9e?= Cc: Peter Maydell , qemu-trivial@nongnu.org, qemu-devel@nongnu.org, crosthwaitepeter@gmail.com, pbonzini@redhat.com, rth@twiddle.net On 2015-08-03 10:14, Alex Benn=E9e wrote: > Each individual architecture needs to use the qemu_log_in_addr_range() > feature for enabling in_asm and marking blocks for op/opt_op output. >=20 > Signed-off-by: Alex Benn=E9e > --- > target-arm/translate-a64.c | 6 ++++-- > target-arm/translate.c | 6 ++++-- > 2 files changed, 8 insertions(+), 4 deletions(-) >=20 > diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c > index 689f2be..0b0f4ae 100644 > --- a/target-arm/translate-a64.c > +++ b/target-arm/translate-a64.c > @@ -11026,7 +11026,8 @@ void gen_intermediate_code_internal_a64(ARMCPU *c= pu, > gen_io_start(); > } > =20 > - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OP= T))) { > + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OP= T) && > + qemu_log_in_addr_range(dc->pc))) { > tcg_gen_debug_insn_start(dc->pc); > } > =20 > @@ -11131,7 +11132,8 @@ done_generating: > gen_tb_end(tb, num_insns); > =20 > #ifdef DEBUG_DISAS > - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { > + if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && > + qemu_log_in_addr_range(pc_start)) { > qemu_log("----------------\n"); > qemu_log("IN: %s\n", lookup_symbol(pc_start)); > log_target_disas(cs, pc_start, dc->pc - pc_start, > diff --git a/target-arm/translate.c b/target-arm/translate.c > index 69ac18c..c914be0 100644 > --- a/target-arm/translate.c > +++ b/target-arm/translate.c > @@ -11316,7 +11316,8 @@ static inline void gen_intermediate_code_internal= (ARMCPU *cpu, > if (num_insns + 1 =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) > gen_io_start(); > =20 > - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OP= T))) { > + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OP= T)) && > + qemu_log_in_addr_range(dc->pc)) { > tcg_gen_debug_insn_start(dc->pc); > } > =20 > @@ -11489,7 +11490,8 @@ done_generating: > gen_tb_end(tb, num_insns); > =20 > #ifdef DEBUG_DISAS > - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { > + if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && > + qemu_log_in_addr_range(pc_start)) { > qemu_log("----------------\n"); > qemu_log("IN: %s\n", lookup_symbol(pc_start)); > log_target_disas(cs, pc_start, dc->pc - pc_start, We probably want to do the same for the other architectures. Reviewed-by: Aurelien Jarno --=20 Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://www.aurel32.net