Re: [PATCH] drm/i915: Check idle to active before processing CSQ

[Daniel Vetter <daniel@ffwll.ch>]

On Thu, Aug 06, 2015 at 05:09:17PM +0300, Mika Kuoppala wrote:
> If idle to active bit is set, the rest of the fields
> in CSQ are not valid.
> 
> Bail out early if this is the case in order to prevent
> rest of the loop inspecting stale values.
> 
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>

Same questions here too, what's the impact. E.g. if you only found this by
bspec/code inspection then it's for -next, but if it's to fix some known
breakage then it's for -fixes + cc: stable.

Thanks, Daniel

> ---
>  drivers/gpu/drm/i915/intel_lrc.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 99bba8e..96218bf 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -497,6 +497,9 @@ void intel_lrc_irq_handler(struct intel_engine_cs *ring)
>  		status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) +
>  				(read_pointer % 6) * 8 + 4);
>  
> +		if (status & GEN8_CTX_STATUS_IDLE_ACTIVE)
> +			continue;
> +
>  		if (status & GEN8_CTX_STATUS_PREEMPTED) {
>  			if (status & GEN8_CTX_STATUS_LITE_RESTORE) {
>  				if (execlists_check_remove_request(ring, status_id))
> -- 
> 2.1.4
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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