From: Aurelien Jarno <aurelien@aurel32.net>
To: Alvise Rigo <a.rigo@virtualopensystems.com>
Cc: mttcg@listserver.greensocs.com, claudio.fontana@huawei.com,
qemu-devel@nongnu.org, pbonzini@redhat.com,
jani.kokkonen@huawei.com, tech@virtualopensystems.com,
alex.bennee@linaro.org
Subject: Re: [Qemu-devel] [RFC v4 5/9] configure: Enable/disable new qemu_{ld, st} excl insns
Date: Sat, 8 Aug 2015 14:44:01 +0200 [thread overview]
Message-ID: <20150808124401.GA18166@aurel32.net> (raw)
In-Reply-To: <1438966995-5913-6-git-send-email-a.rigo@virtualopensystems.com>
On 2015-08-07 19:03, Alvise Rigo wrote:
> Introduce the new --enable-tcg-ldst-excl configure option to enable the
> LL/SC operations only for those backends that support them.
>
> Suggested-by: Jani Kokkonen <jani.kokkonen@huawei.com>
> Suggested-by: Claudio Fontana <claudio.fontana@huawei.com>
> Signed-off-by: Alvise Rigo <a.rigo@virtualopensystems.com>
> ---
> configure | 21 +++++++++++++++++++++
> 1 file changed, 21 insertions(+)
We have seen that for this kind of patch, it's better to add support in
all backends, otherwise it takes ages to get all the backends converted.
I think you should involve the backend maintainers. I can try to provide
the corresponding patches for mips and ia64.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurelien@aurel32.net http://www.aurel32.net
next prev parent reply other threads:[~2015-08-08 12:46 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-08-07 17:03 [Qemu-devel] [RFC v4 0/9] Slow-path for atomic instruction translation Alvise Rigo
2015-08-07 17:03 ` [Qemu-devel] [RFC v4 1/9] exec.c: Add new exclusive bitmap to ram_list Alvise Rigo
2015-08-11 13:52 ` Paolo Bonzini
2015-08-11 14:24 ` Peter Maydell
2015-08-11 14:34 ` alvise rigo
2015-08-11 15:54 ` alvise rigo
2015-08-11 15:55 ` Paolo Bonzini
2015-08-11 16:11 ` alvise rigo
2015-08-11 16:32 ` Paolo Bonzini
2015-08-12 7:31 ` alvise rigo
2015-08-12 12:36 ` Paolo Bonzini
2015-08-12 13:02 ` Peter Maydell
2015-08-12 14:04 ` alvise rigo
2015-08-12 14:10 ` Paolo Bonzini
2015-08-12 14:32 ` alvise rigo
2015-09-10 13:04 ` alvise rigo
2015-09-10 16:19 ` Alex Bennée
2015-09-10 17:36 ` alvise rigo
2015-09-10 16:25 ` Paolo Bonzini
2015-08-07 17:03 ` [Qemu-devel] [RFC v4 2/9] softmmu: Add new TLB_EXCL flag Alvise Rigo
2015-08-07 17:03 ` [Qemu-devel] [RFC v4 3/9] softmmu: Add helpers for a new slowpath Alvise Rigo
2015-08-11 13:32 ` alvise rigo
2015-08-11 13:52 ` Paolo Bonzini
2015-08-11 15:55 ` alvise rigo
2015-08-12 12:43 ` Paolo Bonzini
2015-08-12 13:09 ` alvise rigo
2015-08-12 13:14 ` Paolo Bonzini
2015-08-07 17:03 ` [Qemu-devel] [RFC v4 4/9] tcg-op: create new TCG qemu_{ld, st} excl variants Alvise Rigo
2015-08-07 17:03 ` [Qemu-devel] [RFC v4 5/9] configure: Enable/disable new qemu_{ld, st} excl insns Alvise Rigo
2015-08-08 12:44 ` Aurelien Jarno [this message]
2015-08-08 13:57 ` Peter Maydell
2015-08-09 8:11 ` Alex Bennée
2015-08-09 8:40 ` Aurelien Jarno
2015-08-09 9:51 ` Alex Bennée
2015-08-09 10:13 ` Aurelien Jarno
2015-08-09 16:27 ` Alex Bennée
2015-08-07 17:03 ` [Qemu-devel] [RFC v4 6/9] tcg-i386: Implement excl variants of qemu_{ld, st} Alvise Rigo
2015-08-08 13:00 ` Aurelien Jarno
2015-08-10 7:50 ` alvise rigo
2015-08-07 17:03 ` [Qemu-devel] [RFC v4 7/9] tcg-arm: " Alvise Rigo
2015-08-07 17:03 ` [Qemu-devel] [RFC v4 8/9] tcg-aarch64: " Alvise Rigo
2015-08-07 17:03 ` [Qemu-devel] [RFC v4 9/9] target-arm: translate: Use ld/st excl for atomic insns Alvise Rigo
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