diff for duplicates of <20150811213433.31346.58424@quantum>

diff --git a/a/1.txt b/N1/1.txt
index 00dae98..35389f0 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -1,21 +1,17 @@
-Quoting Heiko St=C3=BCbner (2015-07-28 03:08:54)
+Quoting Heiko Stübner (2015-07-28 03:08:54)
 > Am Dienstag, 28. Juli 2015, 11:52:42 schrieb Sjoerd Simons:
 > > Neither spdif_src nor spdif_pll exists, judging by the vendor kernel in
 > > both cases spdif_pre was meant. This brings the naming in line and
 > > hierachy in line with that of sclk_i2s0.
-> > =
-
+> > 
 > > Also allow sclk_spdif and spdif_frac to change their parents rate as
 > > that the upstream dividers are purely there to feed sclk_spdif
-> > =
-
+> > 
 > > Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
-> =
-
+> 
 > I guess there was one rename to many back in the time :-) .
 > Verified this with the CRU documentation, so
-> =
-
+> 
 > Reviewed-by: Heiko Stuebner <heiko@sntech.de>
 
 Applied to clk-next.
@@ -23,35 +19,26 @@ Applied to clk-next.
 Regards,
 Mike
 
-> =
-
+> 
 > > ---
 > >  drivers/clk/rockchip/clk-rk3188.c | 6 +++---
 > >  1 file changed, 3 insertions(+), 3 deletions(-)
-> > =
-
+> > 
 > > diff --git a/drivers/clk/rockchip/clk-rk3188.c
 > > b/drivers/clk/rockchip/clk-rk3188.c index 0abf22d..ed02bbc 100644
 > > --- a/drivers/clk/rockchip/clk-rk3188.c
 > > +++ b/drivers/clk/rockchip/clk-rk3188.c
-> > @@ -202,7 +202,7 @@ PNAME(mux_pll_src_cpll_gpll_p)    =3D { "cpll", "gp=
-ll" };
-> >  PNAME(mux_aclk_cpu_p)                =3D { "apll", "gpll" };
-> >  PNAME(mux_sclk_cif0_p)               =3D { "cif0_pre", "xin24m" };
-> >  PNAME(mux_sclk_i2s0_p)               =3D { "i2s0_pre", "i2s0_frac", "x=
-in12m" };
-> > -PNAME(mux_sclk_spdif_p)              =3D { "spdif_src", "spdif_frac", =
-"xin12m" };
-> > +PNAME(mux_sclk_spdif_p)              =3D { "spdif_pre", "spdif_frac", =
-"xin12m" };
-> >  PNAME(mux_sclk_uart0_p)              =3D { "uart0_pre", "uart0_frac", =
-"xin24m" };
-> >  PNAME(mux_sclk_uart1_p)              =3D { "uart1_pre", "uart1_frac", =
-"xin24m" };
-> >  PNAME(mux_sclk_uart2_p)              =3D { "uart2_pre", "uart2_frac", =
-"xin24m" };
+> > @@ -202,7 +202,7 @@ PNAME(mux_pll_src_cpll_gpll_p)    = { "cpll", "gpll" };
+> >  PNAME(mux_aclk_cpu_p)                = { "apll", "gpll" };
+> >  PNAME(mux_sclk_cif0_p)               = { "cif0_pre", "xin24m" };
+> >  PNAME(mux_sclk_i2s0_p)               = { "i2s0_pre", "i2s0_frac", "xin12m" };
+> > -PNAME(mux_sclk_spdif_p)              = { "spdif_src", "spdif_frac", "xin12m" };
+> > +PNAME(mux_sclk_spdif_p)              = { "spdif_pre", "spdif_frac", "xin12m" };
+> >  PNAME(mux_sclk_uart0_p)              = { "uart0_pre", "uart0_frac", "xin24m" };
+> >  PNAME(mux_sclk_uart1_p)              = { "uart1_pre", "uart1_frac", "xin24m" };
+> >  PNAME(mux_sclk_uart2_p)              = { "uart2_pre", "uart2_frac", "xin24m" };
 > > @@ -350,10 +350,10 @@ static struct rockchip_clk_branch
-> > common_clk_branches[] __initdata =3D { COMPOSITE_NOMUX(0, "spdif_pre",
+> > common_clk_branches[] __initdata = { COMPOSITE_NOMUX(0, "spdif_pre",
 > > "i2s_src", 0,
 > >                       RK2928_CLKSEL_CON(5), 0, 7, DFLAGS,
 > >                       RK2928_CLKGATE_CON(0), 13, GFLAGS),
@@ -60,17 +47,18 @@ in12m" };
 > >                       RK2928_CLKSEL_CON(9), 0,
 > >                       RK2928_CLKGATE_CON(0), 14, GFLAGS),
 > > -     MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0,
-> > +     MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARE=
-NT,
+> > +     MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT,
 > >                       RK2928_CLKSEL_CON(5), 8, 2, MFLAGS),
-> > =
-
+> > 
 > >       /*
-> =
-
-> =
-
+> 
+> 
 > _______________________________________________
 > linux-arm-kernel mailing list
 > linux-arm-kernel@lists.infradead.org
 > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
+
+_______________________________________________
+Linux-rockchip mailing list
+Linux-rockchip@lists.infradead.org
+http://lists.infradead.org/mailman/listinfo/linux-rockchip
diff --git a/a/content_digest b/N1/content_digest
index 79a5d5d..3797a27 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -1,34 +1,30 @@
  "ref\01438077162-27623-1-git-send-email-sjoerd.simons@collabora.co.uk\0"
  "ref\02030894.j0VJujBTor@diego\0"
- "From\0Michael Turquette <mturquette@baylibre.com>\0"
+ "From\0Michael Turquette <mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>\0"
  "Subject\0Re: [PATCH] clk: rockchip: Fix SPIF special clock definition\0"
  "Date\0Tue, 11 Aug 2015 14:34:33 -0700\0"
- "To\0Heiko St\303\274bner <heiko@sntech.de>"
- " Sjoerd Simons <sjoerd.simons@collabora.co.uk>\0"
- "Cc\0linux-rockchip@lists.infradead.org"
-  Stephen Boyd <sboyd@codeaurora.org>
-  linux-clk@vger.kernel.org
- " linux-arm-kernel@lists.infradead.org\0"
+ "To\0Heiko St\303\274bner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>"
+ " Sjoerd Simons <sjoerd.simons-ZGY8ohtN/8pPYcu2f3hruQ@public.gmane.org>\0"
+ "Cc\0linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org"
+  Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
+  linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
+ " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0"
  "\00:1\0"
  "b\0"
- "Quoting Heiko St=C3=BCbner (2015-07-28 03:08:54)\n"
+ "Quoting Heiko St\303\274bner (2015-07-28 03:08:54)\n"
  "> Am Dienstag, 28. Juli 2015, 11:52:42 schrieb Sjoerd Simons:\n"
  "> > Neither spdif_src nor spdif_pll exists, judging by the vendor kernel in\n"
  "> > both cases spdif_pre was meant. This brings the naming in line and\n"
  "> > hierachy in line with that of sclk_i2s0.\n"
- "> > =\n"
- "\n"
+ "> > \n"
  "> > Also allow sclk_spdif and spdif_frac to change their parents rate as\n"
  "> > that the upstream dividers are purely there to feed sclk_spdif\n"
- "> > =\n"
- "\n"
+ "> > \n"
  "> > Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>\n"
- "> =\n"
- "\n"
+ "> \n"
  "> I guess there was one rename to many back in the time :-) .\n"
  "> Verified this with the CRU documentation, so\n"
- "> =\n"
- "\n"
+ "> \n"
  "> Reviewed-by: Heiko Stuebner <heiko@sntech.de>\n"
  "\n"
  "Applied to clk-next.\n"
@@ -36,35 +32,26 @@
  "Regards,\n"
  "Mike\n"
  "\n"
- "> =\n"
- "\n"
+ "> \n"
  "> > ---\n"
  "> >  drivers/clk/rockchip/clk-rk3188.c | 6 +++---\n"
  "> >  1 file changed, 3 insertions(+), 3 deletions(-)\n"
- "> > =\n"
- "\n"
+ "> > \n"
  "> > diff --git a/drivers/clk/rockchip/clk-rk3188.c\n"
  "> > b/drivers/clk/rockchip/clk-rk3188.c index 0abf22d..ed02bbc 100644\n"
  "> > --- a/drivers/clk/rockchip/clk-rk3188.c\n"
  "> > +++ b/drivers/clk/rockchip/clk-rk3188.c\n"
- "> > @@ -202,7 +202,7 @@ PNAME(mux_pll_src_cpll_gpll_p)    =3D { \"cpll\", \"gp=\n"
- "ll\" };\n"
- "> >  PNAME(mux_aclk_cpu_p)                =3D { \"apll\", \"gpll\" };\n"
- "> >  PNAME(mux_sclk_cif0_p)               =3D { \"cif0_pre\", \"xin24m\" };\n"
- "> >  PNAME(mux_sclk_i2s0_p)               =3D { \"i2s0_pre\", \"i2s0_frac\", \"x=\n"
- "in12m\" };\n"
- "> > -PNAME(mux_sclk_spdif_p)              =3D { \"spdif_src\", \"spdif_frac\", =\n"
- "\"xin12m\" };\n"
- "> > +PNAME(mux_sclk_spdif_p)              =3D { \"spdif_pre\", \"spdif_frac\", =\n"
- "\"xin12m\" };\n"
- "> >  PNAME(mux_sclk_uart0_p)              =3D { \"uart0_pre\", \"uart0_frac\", =\n"
- "\"xin24m\" };\n"
- "> >  PNAME(mux_sclk_uart1_p)              =3D { \"uart1_pre\", \"uart1_frac\", =\n"
- "\"xin24m\" };\n"
- "> >  PNAME(mux_sclk_uart2_p)              =3D { \"uart2_pre\", \"uart2_frac\", =\n"
- "\"xin24m\" };\n"
+ "> > @@ -202,7 +202,7 @@ PNAME(mux_pll_src_cpll_gpll_p)    = { \"cpll\", \"gpll\" };\n"
+ "> >  PNAME(mux_aclk_cpu_p)                = { \"apll\", \"gpll\" };\n"
+ "> >  PNAME(mux_sclk_cif0_p)               = { \"cif0_pre\", \"xin24m\" };\n"
+ "> >  PNAME(mux_sclk_i2s0_p)               = { \"i2s0_pre\", \"i2s0_frac\", \"xin12m\" };\n"
+ "> > -PNAME(mux_sclk_spdif_p)              = { \"spdif_src\", \"spdif_frac\", \"xin12m\" };\n"
+ "> > +PNAME(mux_sclk_spdif_p)              = { \"spdif_pre\", \"spdif_frac\", \"xin12m\" };\n"
+ "> >  PNAME(mux_sclk_uart0_p)              = { \"uart0_pre\", \"uart0_frac\", \"xin24m\" };\n"
+ "> >  PNAME(mux_sclk_uart1_p)              = { \"uart1_pre\", \"uart1_frac\", \"xin24m\" };\n"
+ "> >  PNAME(mux_sclk_uart2_p)              = { \"uart2_pre\", \"uart2_frac\", \"xin24m\" };\n"
  "> > @@ -350,10 +350,10 @@ static struct rockchip_clk_branch\n"
- "> > common_clk_branches[] __initdata =3D { COMPOSITE_NOMUX(0, \"spdif_pre\",\n"
+ "> > common_clk_branches[] __initdata = { COMPOSITE_NOMUX(0, \"spdif_pre\",\n"
  "> > \"i2s_src\", 0,\n"
  "> >                       RK2928_CLKSEL_CON(5), 0, 7, DFLAGS,\n"
  "> >                       RK2928_CLKGATE_CON(0), 13, GFLAGS),\n"
@@ -73,19 +60,20 @@
  "> >                       RK2928_CLKSEL_CON(9), 0,\n"
  "> >                       RK2928_CLKGATE_CON(0), 14, GFLAGS),\n"
  "> > -     MUX(SCLK_SPDIF, \"sclk_spdif\", mux_sclk_spdif_p, 0,\n"
- "> > +     MUX(SCLK_SPDIF, \"sclk_spdif\", mux_sclk_spdif_p, CLK_SET_RATE_PARE=\n"
- "NT,\n"
+ "> > +     MUX(SCLK_SPDIF, \"sclk_spdif\", mux_sclk_spdif_p, CLK_SET_RATE_PARENT,\n"
  "> >                       RK2928_CLKSEL_CON(5), 8, 2, MFLAGS),\n"
- "> > =\n"
- "\n"
+ "> > \n"
  "> >       /*\n"
- "> =\n"
- "\n"
- "> =\n"
- "\n"
+ "> \n"
+ "> \n"
  "> _______________________________________________\n"
  "> linux-arm-kernel mailing list\n"
  "> linux-arm-kernel@lists.infradead.org\n"
- > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
+ "> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel\n"
+ "\n"
+ "_______________________________________________\n"
+ "Linux-rockchip mailing list\n"
+ "Linux-rockchip@lists.infradead.org\n"
+ http://lists.infradead.org/mailman/listinfo/linux-rockchip
 
-3bb88a5b84b561840a4b813b61ecbdf77f736c2a666c6f544db2a2adec671574
+6d675269aca62f4e04a670d23396527ce5a9dae0b1479ac9bcb54b86e8792a1d
