Re: [PATCH] ASoC: fsl-asoc-card: add wm8960 support

[Zidan Wang <zidan.wang@freescale.com>]

On Thu, Aug 13, 2015 at 08:58:06PM -0700, Nicolin Chen wrote:
> On Fri, Aug 14, 2015 at 10:21:18AM +0800, Zidan Wang wrote:
> 
> > > And there is a crucial problem I can imagine:
> > >   Is it okay to set this bit while setting SD1_CLK PAD as one
> > >   of other functions rather than SAI MCLK? -- Customers might
> > >   keep your code as they also use SAI2 while using SD1_CLK PAD
> > >   as a GPIO input.
> 
> > I just add a gpr node in device tree, if customer want to use SD1_CLK
> > PAD as a GPIO input, remove the gpr node.
> 
> My question was whether setting this bit would cause a hardware
> damage -- Customers might not notice your gpr node in the Device
> Tree at all, not to mention the possibility of an accidental wrong
> configurations.
> 
> And another reason I asked that is to find out if we can set these
> bits anyway in the SoC level driver of imx6ul when this bit would
> not cause anything dangerous and when there's no extra clock MUX
> for the SAI MCLK between internal CCM and external clock source.
> 
This bit will not cause any hardware damage. 

ccm ----->1------------------>2<------------>3
	  |                   |
    	  |                   |		
	  4 SAIx MCLK1        5 SAIx MCLK2

If this bit is set, the clock route is ccm->1->2->3, 2 to 5 is disconnect.
If this bit is clear, the clock route is 3->2->5, 1 to 2 is disconnect.

Best Regards,
Zidan Wang

> Nicolin