diff for duplicates of <20150818124448.GA13507@arm.com> diff --git a/a/1.txt b/N1/1.txt index ab0fb22..7d00ef6 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,7 +1,7 @@ Hi Tirumalesh, -On Tue, Aug 18, 2015 at 12:13:55AM +0100, tchalamarla-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org wrote: -> From: Tirumalesh Chalamarla <tchalamarla-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org> +On Tue, Aug 18, 2015 at 12:13:55AM +0100, tchalamarla at caviumnetworks.com wrote: +> From: Tirumalesh Chalamarla <tchalamarla@caviumnetworks.com> > > The SMMU architecture defines two different behaviors when 64-bit > registers are written with 32-bit writes. The first behavior causes @@ -11,7 +11,7 @@ On Tue, Aug 18, 2015 at 12:13:55AM +0100, tchalamarla-M3mlKVOIwJVv6pq1l3V1OdBPR1 > On some buggy implementations, registers incorrectly zero extended > when they should instead behave as normal 32-bit register pairs. > -> Signed-off-by: Tirumalesh Chalamarla <tchalamarla-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org> +> Signed-off-by: Tirumalesh Chalamarla <tchalamarla@caviumnetworks.com> > > Changes from V2: > - removed unused definitions diff --git a/a/content_digest b/N1/content_digest index 743b442..034112d 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,20 +1,14 @@ "ref\01439853235-12162-1-git-send-email-tchalamarla@caviumnetworks.com\0" - "ref\01439853235-12162-1-git-send-email-tchalamarla-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org\0" - "From\0Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>\0" - "Subject\0Re: [PATCH V3] iommu/arm-smmu-v2: ThunderX mis-extends 64bit registers\0" + "From\0will.deacon@arm.com (Will Deacon)\0" + "Subject\0[PATCH V3] iommu/arm-smmu-v2: ThunderX mis-extends 64bit registers\0" "Date\0Tue, 18 Aug 2015 13:44:48 +0100\0" - "To\0tchalamarla-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org <tchalamarla-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>\0" - "Cc\0linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>" - ddaney-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org <ddaney-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org> - iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org <iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org> - robert.richter-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org <robert.richter-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org> - " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Hi Tirumalesh,\n" "\n" - "On Tue, Aug 18, 2015 at 12:13:55AM +0100, tchalamarla-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org wrote:\n" - "> From: Tirumalesh Chalamarla <tchalamarla-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>\n" + "On Tue, Aug 18, 2015 at 12:13:55AM +0100, tchalamarla at caviumnetworks.com wrote:\n" + "> From: Tirumalesh Chalamarla <tchalamarla@caviumnetworks.com>\n" "> \n" "> The SMMU architecture defines two different behaviors when 64-bit\n" "> registers are written with 32-bit writes. The first behavior causes\n" @@ -24,7 +18,7 @@ "> On some buggy implementations, registers incorrectly zero extended\n" "> when they should instead behave as normal 32-bit register pairs.\n" "> \n" - "> Signed-off-by: Tirumalesh Chalamarla <tchalamarla-M3mlKVOIwJVv6pq1l3V1OdBPR1lH4CV8@public.gmane.org>\n" + "> Signed-off-by: Tirumalesh Chalamarla <tchalamarla@caviumnetworks.com>\n" "> \n" "> Changes from V2:\n" "> \t- removed unused definitions\n" @@ -43,4 +37,4 @@ "\n" Will -a64e6e91efcfa08b99ebbdf4fe8851eb10bcc4dea76cea969d488349c509c842 +853ebf988158496cb3b0bbf0f10b0cc5faef69b87fc26facb9544f96d291bbde
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