From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Date: Tue, 25 Aug 2015 08:55:56 +0100 From: Lee Jones To: Vaibhav Hiremath Cc: linux-arm-kernel@lists.infradead.org, robh+dt@kernel.org, mturquette@baylibre.com, k.kozlowski@samsung.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: Re: [PATCH-v2 2/5] mfd: 88pm800: Update the header file with 32K clk related macros Message-ID: <20150825075556.GG19409@x1> References: <1440442594-3102-1-git-send-email-vaibhav.hiremath@linaro.org> <1440442594-3102-4-git-send-email-vaibhav.hiremath@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 In-Reply-To: <1440442594-3102-4-git-send-email-vaibhav.hiremath@linaro.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: On Tue, 25 Aug 2015, Vaibhav Hiremath wrote: > Update header file with required macros for 32KHz buffered clock > output of 88PM800 family of device. > These macros will be used in clk provider driver. > > Signed-off-by: Vaibhav Hiremath > --- > include/linux/mfd/88pm80x.h | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/include/linux/mfd/88pm80x.h b/include/linux/mfd/88pm80x.h > index 122cfd2..0215d5f 100644 > --- a/include/linux/mfd/88pm80x.h > +++ b/include/linux/mfd/88pm80x.h > @@ -91,6 +91,7 @@ enum { > /* Referance and low power registers */ > #define PM800_LOW_POWER1 (0x20) > #define PM800_LOW_POWER2 (0x21) > +#define PM800_LOW_POWER2_XO_LJ_EN BIT(5) Some people add an extra space for register bits, which I quite like. So: #define SOME_REGISTER_ADDRESS 0x123 #define SOME_BIT_VALUE BIT(4) Feel free to use it, or not. > #define PM800_LOW_POWER_CONFIG3 (0x22) > #define PM800_LDOBK_FREEZE BIT(7) > @@ -138,6 +139,13 @@ enum { > #define PM800_ALARM BIT(5) > #define PM800_RTC1_USE_XO BIT(7) > > +#define PM800_32K_OUTX_SEL_MASK 0x3 > +/* 32KHz clk output sel mode */ > +#define PM800_32K_OUTX_SEL_ZERO 0x0 > +#define PM800_32K_OUTX_SEL_INT_32KHZ 0x1 > +#define PM800_32K_OUTX_SEL_XO_32KHZ 0x2 > +#define PM800_32K_OUTX_SEL_HIZ 0x3 > + > /* Regulator Control Registers: BUCK1,BUCK5,LDO1 have DVC */ > > /* buck registers */ > @@ -208,6 +216,10 @@ enum { > #define PM800_PMOD_MEAS1 0x52 > #define PM800_PMOD_MEAS2 0x53 > > +/* Oscillator control */ > +#define PM800_OSC_CNTRL1 0x50 > +#define PM800_OSC_CNTRL1_OSC_FREERUN_EN BIT(1) 0x50 goes before 0x52 (and 0x51 if it's there). > #define PM800_GPADC0_MEAS1 0x54 > #define PM800_GPADC0_MEAS2 0x55 > #define PM800_GPADC1_MEAS1 0x56 -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog From mboxrd@z Thu Jan 1 00:00:00 1970 From: lee.jones@linaro.org (Lee Jones) Date: Tue, 25 Aug 2015 08:55:56 +0100 Subject: [PATCH-v2 2/5] mfd: 88pm800: Update the header file with 32K clk related macros In-Reply-To: <1440442594-3102-4-git-send-email-vaibhav.hiremath@linaro.org> References: <1440442594-3102-1-git-send-email-vaibhav.hiremath@linaro.org> <1440442594-3102-4-git-send-email-vaibhav.hiremath@linaro.org> Message-ID: <20150825075556.GG19409@x1> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Tue, 25 Aug 2015, Vaibhav Hiremath wrote: > Update header file with required macros for 32KHz buffered clock > output of 88PM800 family of device. > These macros will be used in clk provider driver. > > Signed-off-by: Vaibhav Hiremath > --- > include/linux/mfd/88pm80x.h | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/include/linux/mfd/88pm80x.h b/include/linux/mfd/88pm80x.h > index 122cfd2..0215d5f 100644 > --- a/include/linux/mfd/88pm80x.h > +++ b/include/linux/mfd/88pm80x.h > @@ -91,6 +91,7 @@ enum { > /* Referance and low power registers */ > #define PM800_LOW_POWER1 (0x20) > #define PM800_LOW_POWER2 (0x21) > +#define PM800_LOW_POWER2_XO_LJ_EN BIT(5) Some people add an extra space for register bits, which I quite like. So: #define SOME_REGISTER_ADDRESS 0x123 #define SOME_BIT_VALUE BIT(4) Feel free to use it, or not. > #define PM800_LOW_POWER_CONFIG3 (0x22) > #define PM800_LDOBK_FREEZE BIT(7) > @@ -138,6 +139,13 @@ enum { > #define PM800_ALARM BIT(5) > #define PM800_RTC1_USE_XO BIT(7) > > +#define PM800_32K_OUTX_SEL_MASK 0x3 > +/* 32KHz clk output sel mode */ > +#define PM800_32K_OUTX_SEL_ZERO 0x0 > +#define PM800_32K_OUTX_SEL_INT_32KHZ 0x1 > +#define PM800_32K_OUTX_SEL_XO_32KHZ 0x2 > +#define PM800_32K_OUTX_SEL_HIZ 0x3 > + > /* Regulator Control Registers: BUCK1,BUCK5,LDO1 have DVC */ > > /* buck registers */ > @@ -208,6 +216,10 @@ enum { > #define PM800_PMOD_MEAS1 0x52 > #define PM800_PMOD_MEAS2 0x53 > > +/* Oscillator control */ > +#define PM800_OSC_CNTRL1 0x50 > +#define PM800_OSC_CNTRL1_OSC_FREERUN_EN BIT(1) 0x50 goes before 0x52 (and 0x51 if it's there). > #define PM800_GPADC0_MEAS1 0x54 > #define PM800_GPADC0_MEAS2 0x55 > #define PM800_GPADC1_MEAS1 0x56 -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org ? Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog From mboxrd@z Thu Jan 1 00:00:00 1970 From: Lee Jones Subject: Re: [PATCH-v2 2/5] mfd: 88pm800: Update the header file with 32K clk related macros Date: Tue, 25 Aug 2015 08:55:56 +0100 Message-ID: <20150825075556.GG19409@x1> References: <1440442594-3102-1-git-send-email-vaibhav.hiremath@linaro.org> <1440442594-3102-4-git-send-email-vaibhav.hiremath@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: <1440442594-3102-4-git-send-email-vaibhav.hiremath@linaro.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Vaibhav Hiremath Cc: devicetree@vger.kernel.org, k.kozlowski@samsung.com, mturquette@baylibre.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org T24gVHVlLCAyNSBBdWcgMjAxNSwgVmFpYmhhdiBIaXJlbWF0aCB3cm90ZToKCj4gVXBkYXRlIGhl YWRlciBmaWxlIHdpdGggcmVxdWlyZWQgbWFjcm9zIGZvciAzMktIeiBidWZmZXJlZCBjbG9jawo+ IG91dHB1dCBvZiA4OFBNODAwIGZhbWlseSBvZiBkZXZpY2UuCj4gVGhlc2UgbWFjcm9zIHdpbGwg YmUgdXNlZCBpbiBjbGsgcHJvdmlkZXIgZHJpdmVyLgo+IAo+IFNpZ25lZC1vZmYtYnk6IFZhaWJo YXYgSGlyZW1hdGggPHZhaWJoYXYuaGlyZW1hdGhAbGluYXJvLm9yZz4KPiAtLS0KPiAgaW5jbHVk ZS9saW51eC9tZmQvODhwbTgweC5oIHwgMTIgKysrKysrKysrKysrCj4gIDEgZmlsZSBjaGFuZ2Vk LCAxMiBpbnNlcnRpb25zKCspCj4gCj4gZGlmZiAtLWdpdCBhL2luY2x1ZGUvbGludXgvbWZkLzg4 cG04MHguaCBiL2luY2x1ZGUvbGludXgvbWZkLzg4cG04MHguaAo+IGluZGV4IDEyMmNmZDIuLjAy MTVkNWYgMTAwNjQ0Cj4gLS0tIGEvaW5jbHVkZS9saW51eC9tZmQvODhwbTgweC5oCj4gKysrIGIv aW5jbHVkZS9saW51eC9tZmQvODhwbTgweC5oCj4gQEAgLTkxLDYgKzkxLDcgQEAgZW51bSB7Cj4g IC8qIFJlZmVyYW5jZSBhbmQgbG93IHBvd2VyIHJlZ2lzdGVycyAqLwo+ICAjZGVmaW5lIFBNODAw X0xPV19QT1dFUjEJCSgweDIwKQo+ICAjZGVmaW5lIFBNODAwX0xPV19QT1dFUjIJCSgweDIxKQo+ ICsjZGVmaW5lIFBNODAwX0xPV19QT1dFUjJfWE9fTEpfRU4JQklUKDUpCgpTb21lIHBlb3BsZSBh ZGQgYW4gZXh0cmEgc3BhY2UgZm9yIHJlZ2lzdGVyIGJpdHMsIHdoaWNoIEkgcXVpdGUgbGlrZS4K ClNvOgoKI2RlZmluZSBTT01FX1JFR0lTVEVSX0FERFJFU1MJMHgxMjMKI2RlZmluZSAgU09NRV9C SVRfVkFMVUUJCUJJVCg0KQoKRmVlbCBmcmVlIHRvIHVzZSBpdCwgb3Igbm90LgoKPiAgI2RlZmlu ZSBQTTgwMF9MT1dfUE9XRVJfQ09ORklHMwkJKDB4MjIpCj4gICNkZWZpbmUgUE04MDBfTERPQktf RlJFRVpFCQlCSVQoNykKPiBAQCAtMTM4LDYgKzEzOSwxMyBAQCBlbnVtIHsKPiAgI2RlZmluZSBQ TTgwMF9BTEFSTQkJCUJJVCg1KQo+ICAjZGVmaW5lIFBNODAwX1JUQzFfVVNFX1hPCQlCSVQoNykK PiAgCj4gKyNkZWZpbmUgUE04MDBfMzJLX09VVFhfU0VMX01BU0sJCTB4Mwo+ICsvKiAzMktIeiBj bGsgb3V0cHV0IHNlbCBtb2RlICovCj4gKyNkZWZpbmUgUE04MDBfMzJLX09VVFhfU0VMX1pFUk8J CTB4MAo+ICsjZGVmaW5lIFBNODAwXzMyS19PVVRYX1NFTF9JTlRfMzJLSFoJMHgxCj4gKyNkZWZp bmUgUE04MDBfMzJLX09VVFhfU0VMX1hPXzMyS0haCTB4Mgo+ICsjZGVmaW5lIFBNODAwXzMyS19P VVRYX1NFTF9ISVoJCTB4Mwo+ICsKPiAgLyogUmVndWxhdG9yIENvbnRyb2wgUmVnaXN0ZXJzOiBC VUNLMSxCVUNLNSxMRE8xIGhhdmUgRFZDICovCj4gIAo+ICAvKiBidWNrIHJlZ2lzdGVycyAqLwo+ IEBAIC0yMDgsNiArMjE2LDEwIEBAIGVudW0gewo+ICAjZGVmaW5lIFBNODAwX1BNT0RfTUVBUzEJ CTB4NTIKPiAgI2RlZmluZSBQTTgwMF9QTU9EX01FQVMyCQkweDUzCj4gIAo+ICsvKiBPc2NpbGxh dG9yIGNvbnRyb2wgKi8KPiArI2RlZmluZSBQTTgwMF9PU0NfQ05UUkwxCQkweDUwCj4gKyNkZWZp bmUgUE04MDBfT1NDX0NOVFJMMV9PU0NfRlJFRVJVTl9FTglCSVQoMSkKCjB4NTAgZ29lcyBiZWZv cmUgMHg1MiAoYW5kIDB4NTEgaWYgaXQncyB0aGVyZSkuCgo+ICAjZGVmaW5lIFBNODAwX0dQQURD MF9NRUFTMQkJMHg1NAo+ICAjZGVmaW5lIFBNODAwX0dQQURDMF9NRUFTMgkJMHg1NQo+ICAjZGVm aW5lIFBNODAwX0dQQURDMV9NRUFTMQkJMHg1NgoKLS0gCkxlZSBKb25lcwpMaW5hcm8gU1RNaWNy b2VsZWN0cm9uaWNzIExhbmRpbmcgVGVhbSBMZWFkCkxpbmFyby5vcmcg4pSCIE9wZW4gc291cmNl IHNvZnR3YXJlIGZvciBBUk0gU29DcwpGb2xsb3cgTGluYXJvOiBGYWNlYm9vayB8IFR3aXR0ZXIg fCBCbG9nCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwps aW51eC1hcm0ta2VybmVsIG1haWxpbmcgbGlzdApsaW51eC1hcm0ta2VybmVsQGxpc3RzLmluZnJh ZGVhZC5vcmcKaHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51 eC1hcm0ta2VybmVsCg==