diff for duplicates of <20150825184013.31346.67214@quantum> diff --git a/a/1.txt b/N1/1.txt index 9d81d8f..f4cb94c 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -2,11 +2,9 @@ Quoting Bartlomiej Zolnierkiewicz (2015-08-06 06:41:50) > With the addition of the new Samsung specific cpu-clock type, the > arm clock can be represented as a cpu-clock type. Add the CPU clock > configuration data and instantiate the CPU clock type for Exynos4x12. -> = - +> > Based on the earlier work by Thomas Abraham. -> = - +> > Cc: Tomasz Figa <tomasz.figa@gmail.com> > Cc: Michael Turquette <mturquette@baylibre.com> > Cc: Thomas Abraham <thomas.ab@samsung.com> @@ -19,127 +17,80 @@ Quoting Bartlomiej Zolnierkiewicz (2015-08-06 06:41:50) Acked-by: Michael Turquette <mturquette@baylibre.com> > --- -> drivers/clk/samsung/clk-exynos4.c | 50 +++++++++++++++++++++++++++++++++= -++++++ +> drivers/clk/samsung/clk-exynos4.c | 50 +++++++++++++++++++++++++++++++++++++++ > 1 file changed, 50 insertions(+) -> = - -> diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-= -exynos4.c +> +> diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c > index 251f48d..7f370d3 100644 > --- a/drivers/clk/samsung/clk-exynos4.c > +++ b/drivers/clk/samsung/clk-exynos4.c -> @@ -1398,6 +1398,45 @@ static const struct exynos_cpuclk_cfg_data e4210_a= -rmclk_d[] __initconst =3D { +> @@ -1398,6 +1398,45 @@ static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = { > { 0 }, > }; -> = - -> +static const struct exynos_cpuclk_cfg_data e4212_armclk_d[] __initconst = -=3D { -> + { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6)= -, }, -> + { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6)= -, }, -> + { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5)= -, }, -> + { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5)= -, }, -> + { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4210_CPU_DIV1(2, 4)= -, }, -> + { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4210_CPU_DIV1(2, 4)= -, }, -> + { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3)= -, }, -> + { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3)= -, }, -> + { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3)= -, }, -> + { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3)= -, }, -> + { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3)= -, }, -> + { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3)= -, }, -> + { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4210_CPU_DIV1(2, 3)= -, }, -> + { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4210_CPU_DIV1(2, 3)= -, }, +> +> +static const struct exynos_cpuclk_cfg_data e4212_armclk_d[] __initconst = { +> + { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), }, +> + { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), }, +> + { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), }, +> + { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), }, +> + { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4210_CPU_DIV1(2, 4), }, +> + { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4210_CPU_DIV1(2, 4), }, +> + { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), }, +> + { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), }, +> + { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), }, +> + { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), }, +> + { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), }, +> + { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), }, +> + { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4210_CPU_DIV1(2, 3), }, +> + { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4210_CPU_DIV1(2, 3), }, > + { 0 }, > +}; > + > +#define E4412_CPU_DIV1(cores, hpm, copy) \ > + (((cores) << 8) | ((hpm) << 4) | ((copy) << 0)) > + -> +static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = -=3D { -> + { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0,= - 6), }, -> + { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(6, 0,= - 6), }, -> + { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(6, 0,= - 5), }, -> + { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(5, 0,= - 5), }, -> + { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4412_CPU_DIV1(5, 0,= - 4), }, -> + { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4412_CPU_DIV1(4, 0,= - 4), }, -> + { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(4, 0,= - 3), }, -> + { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(3, 0,= - 3), }, -> + { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(3, 0,= - 3), }, -> + { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0,= - 3), }, -> + { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0,= - 3), }, -> + { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(1, 0,= - 3), }, -> + { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4412_CPU_DIV1(1, 0,= - 3), }, -> + { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4412_CPU_DIV1(0, 0,= - 3), }, +> +static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = { +> + { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), }, +> + { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(6, 0, 6), }, +> + { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(6, 0, 5), }, +> + { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(5, 0, 5), }, +> + { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4412_CPU_DIV1(5, 0, 4), }, +> + { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4412_CPU_DIV1(4, 0, 4), }, +> + { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(4, 0, 3), }, +> + { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(3, 0, 3), }, +> + { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(3, 0, 3), }, +> + { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), }, +> + { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), }, +> + { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), }, +> + { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), }, +> + { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4412_CPU_DIV1(0, 0, 3), }, > + { 0 }, > +}; > + > /* register exynos4 clocks */ > static void __init exynos4_clk_init(struct device_node *np, > enum exynos4_soc soc) -> @@ -1491,6 +1530,17 @@ static void __init exynos4_clk_init(struct device_= -node *np, +> @@ -1491,6 +1530,17 @@ static void __init exynos4_clk_init(struct device_node *np, > samsung_clk_register_fixed_factor(ctx, > exynos4x12_fixed_factor_clks, > ARRAY_SIZE(exynos4x12_fixed_factor_clks)); > + if (of_machine_is_compatible("samsung,exynos4412")) { -> + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armc= -lk", -> + mout_core_p4x12[0], mout_core_p4x12[1], 0= -x14200, -> + e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d= -), -> + CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS= -_DIV1); +> + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", +> + mout_core_p4x12[0], mout_core_p4x12[1], 0x14200, +> + e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d), +> + CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1); > + } else { -> + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armc= -lk", -> + mout_core_p4x12[0], mout_core_p4x12[1], 0= -x14200, -> + e4212_armclk_d, ARRAY_SIZE(e4212_armclk_d= -), -> + CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS= -_DIV1); +> + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", +> + mout_core_p4x12[0], mout_core_p4x12[1], 0x14200, +> + e4212_armclk_d, ARRAY_SIZE(e4212_armclk_d), +> + CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1); > + } > } -> = - +> > samsung_clk_register_alias(ctx, exynos4_aliases, -> -- = - +> -- > 1.9.1 -> = - +> > -- > To unsubscribe from this list: send the line "unsubscribe linux-kernel" in > the body of a message to majordomo@vger.kernel.org diff --git a/a/content_digest b/N1/content_digest index 4e4869f..51c7984 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -3,8 +3,7 @@ "From\0Michael Turquette <mturquette@baylibre.com>\0" "Subject\0Re: [PATCH v4 2/6] clk: samsung: exynos4x12: add cpu clock configuration data and instantiate cpu clock\0" "Date\0Tue, 25 Aug 2015 11:40:13 -0700\0" - "To\0Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>" - Thomas Abraham <thomas.ab@samsung.com> + "To\0Thomas Abraham <thomas.ab@samsung.com>" Sylwester Nawrocki <s.nawrocki@samsung.com> Kukjin Kim <kgene.kim@samsung.com> Kukjin Kim <kgene@kernel.org> @@ -30,11 +29,9 @@ "> With the addition of the new Samsung specific cpu-clock type, the\n" "> arm clock can be represented as a cpu-clock type. Add the CPU clock\n" "> configuration data and instantiate the CPU clock type for Exynos4x12.\n" - "> =\n" - "\n" + "> \n" "> Based on the earlier work by Thomas Abraham.\n" - "> =\n" - "\n" + "> \n" "> Cc: Tomasz Figa <tomasz.figa@gmail.com>\n" "> Cc: Michael Turquette <mturquette@baylibre.com>\n" "> Cc: Thomas Abraham <thomas.ab@samsung.com>\n" @@ -47,131 +44,84 @@ "Acked-by: Michael Turquette <mturquette@baylibre.com>\n" "\n" "> ---\n" - "> drivers/clk/samsung/clk-exynos4.c | 50 +++++++++++++++++++++++++++++++++=\n" - "++++++\n" + "> drivers/clk/samsung/clk-exynos4.c | 50 +++++++++++++++++++++++++++++++++++++++\n" "> 1 file changed, 50 insertions(+)\n" - "> =\n" - "\n" - "> diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-=\n" - "exynos4.c\n" + "> \n" + "> diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c\n" "> index 251f48d..7f370d3 100644\n" "> --- a/drivers/clk/samsung/clk-exynos4.c\n" "> +++ b/drivers/clk/samsung/clk-exynos4.c\n" - "> @@ -1398,6 +1398,45 @@ static const struct exynos_cpuclk_cfg_data e4210_a=\n" - "rmclk_d[] __initconst =3D {\n" + "> @@ -1398,6 +1398,45 @@ static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = {\n" "> { 0 },\n" "> };\n" - "> =\n" - "\n" - "> +static const struct exynos_cpuclk_cfg_data e4212_armclk_d[] __initconst =\n" - "=3D {\n" - "> + { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6)=\n" - ", },\n" - "> + { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6)=\n" - ", },\n" - "> + { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5)=\n" - ", },\n" - "> + { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5)=\n" - ", },\n" - "> + { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4210_CPU_DIV1(2, 4)=\n" - ", },\n" - "> + { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4210_CPU_DIV1(2, 4)=\n" - ", },\n" - "> + { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3)=\n" - ", },\n" - "> + { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3)=\n" - ", },\n" - "> + { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3)=\n" - ", },\n" - "> + { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3)=\n" - ", },\n" - "> + { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3)=\n" - ", },\n" - "> + { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3)=\n" - ", },\n" - "> + { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4210_CPU_DIV1(2, 3)=\n" - ", },\n" - "> + { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4210_CPU_DIV1(2, 3)=\n" - ", },\n" + "> \n" + "> +static const struct exynos_cpuclk_cfg_data e4212_armclk_d[] __initconst = {\n" + "> + { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },\n" + "> + { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },\n" + "> + { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },\n" + "> + { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },\n" + "> + { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4210_CPU_DIV1(2, 4), },\n" + "> + { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4210_CPU_DIV1(2, 4), },\n" + "> + { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },\n" + "> + { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },\n" + "> + { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },\n" + "> + { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },\n" + "> + { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },\n" + "> + { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },\n" + "> + { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4210_CPU_DIV1(2, 3), },\n" + "> + { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4210_CPU_DIV1(2, 3), },\n" "> + { 0 },\n" "> +};\n" "> +\n" "> +#define E4412_CPU_DIV1(cores, hpm, copy) \\\n" "> + (((cores) << 8) | ((hpm) << 4) | ((copy) << 0))\n" "> +\n" - "> +static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst =\n" - "=3D {\n" - "> + { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0,=\n" - " 6), },\n" - "> + { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(6, 0,=\n" - " 6), },\n" - "> + { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(6, 0,=\n" - " 5), },\n" - "> + { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(5, 0,=\n" - " 5), },\n" - "> + { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4412_CPU_DIV1(5, 0,=\n" - " 4), },\n" - "> + { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4412_CPU_DIV1(4, 0,=\n" - " 4), },\n" - "> + { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(4, 0,=\n" - " 3), },\n" - "> + { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(3, 0,=\n" - " 3), },\n" - "> + { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(3, 0,=\n" - " 3), },\n" - "> + { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0,=\n" - " 3), },\n" - "> + { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0,=\n" - " 3), },\n" - "> + { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(1, 0,=\n" - " 3), },\n" - "> + { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4412_CPU_DIV1(1, 0,=\n" - " 3), },\n" - "> + { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4412_CPU_DIV1(0, 0,=\n" - " 3), },\n" + "> +static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = {\n" + "> + { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), },\n" + "> + { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(6, 0, 6), },\n" + "> + { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(6, 0, 5), },\n" + "> + { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(5, 0, 5), },\n" + "> + { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4412_CPU_DIV1(5, 0, 4), },\n" + "> + { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4412_CPU_DIV1(4, 0, 4), },\n" + "> + { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(4, 0, 3), },\n" + "> + { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(3, 0, 3), },\n" + "> + { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(3, 0, 3), },\n" + "> + { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), },\n" + "> + { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), },\n" + "> + { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), },\n" + "> + { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), },\n" + "> + { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4412_CPU_DIV1(0, 0, 3), },\n" "> + { 0 },\n" "> +};\n" "> +\n" "> /* register exynos4 clocks */\n" "> static void __init exynos4_clk_init(struct device_node *np,\n" "> enum exynos4_soc soc)\n" - "> @@ -1491,6 +1530,17 @@ static void __init exynos4_clk_init(struct device_=\n" - "node *np,\n" + "> @@ -1491,6 +1530,17 @@ static void __init exynos4_clk_init(struct device_node *np,\n" "> samsung_clk_register_fixed_factor(ctx,\n" "> exynos4x12_fixed_factor_clks,\n" "> ARRAY_SIZE(exynos4x12_fixed_factor_clks));\n" "> + if (of_machine_is_compatible(\"samsung,exynos4412\")) {\n" - "> + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, \"armc=\n" - "lk\",\n" - "> + mout_core_p4x12[0], mout_core_p4x12[1], 0=\n" - "x14200,\n" - "> + e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d=\n" - "),\n" - "> + CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS=\n" - "_DIV1);\n" + "> + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, \"armclk\",\n" + "> + mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,\n" + "> + e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d),\n" + "> + CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);\n" "> + } else {\n" - "> + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, \"armc=\n" - "lk\",\n" - "> + mout_core_p4x12[0], mout_core_p4x12[1], 0=\n" - "x14200,\n" - "> + e4212_armclk_d, ARRAY_SIZE(e4212_armclk_d=\n" - "),\n" - "> + CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS=\n" - "_DIV1);\n" + "> + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, \"armclk\",\n" + "> + mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,\n" + "> + e4212_armclk_d, ARRAY_SIZE(e4212_armclk_d),\n" + "> + CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);\n" "> + }\n" "> }\n" - "> =\n" - "\n" + "> \n" "> samsung_clk_register_alias(ctx, exynos4_aliases,\n" - "> -- =\n" - "\n" + "> -- \n" "> 1.9.1\n" - "> =\n" - "\n" + "> \n" "> --\n" "> To unsubscribe from this list: send the line \"unsubscribe linux-kernel\" in\n" "> the body of a message to majordomo@vger.kernel.org\n" "> More majordomo info at http://vger.kernel.org/majordomo-info.html\n" > Please read the FAQ at http://www.tux.org/lkml/ -0e905af657cff5b9705abce80fb7a09d0990045e29649abb455a9a7d2a6e5a77 +9aa16478bd37a7b2d16f93b419bab4ddd53655194a0e2871972f0dd021d9ead9
diff --git a/a/1.txt b/N2/1.txt index 9d81d8f..cab15d8 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -2,11 +2,9 @@ Quoting Bartlomiej Zolnierkiewicz (2015-08-06 06:41:50) > With the addition of the new Samsung specific cpu-clock type, the > arm clock can be represented as a cpu-clock type. Add the CPU clock > configuration data and instantiate the CPU clock type for Exynos4x12. -> = - +> > Based on the earlier work by Thomas Abraham. -> = - +> > Cc: Tomasz Figa <tomasz.figa@gmail.com> > Cc: Michael Turquette <mturquette@baylibre.com> > Cc: Thomas Abraham <thomas.ab@samsung.com> @@ -19,129 +17,82 @@ Quoting Bartlomiej Zolnierkiewicz (2015-08-06 06:41:50) Acked-by: Michael Turquette <mturquette@baylibre.com> > --- -> drivers/clk/samsung/clk-exynos4.c | 50 +++++++++++++++++++++++++++++++++= -++++++ +> drivers/clk/samsung/clk-exynos4.c | 50 +++++++++++++++++++++++++++++++++++++++ > 1 file changed, 50 insertions(+) -> = - -> diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-= -exynos4.c +> +> diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c > index 251f48d..7f370d3 100644 > --- a/drivers/clk/samsung/clk-exynos4.c > +++ b/drivers/clk/samsung/clk-exynos4.c -> @@ -1398,6 +1398,45 @@ static const struct exynos_cpuclk_cfg_data e4210_a= -rmclk_d[] __initconst =3D { +> @@ -1398,6 +1398,45 @@ static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = { > { 0 }, > }; -> = - -> +static const struct exynos_cpuclk_cfg_data e4212_armclk_d[] __initconst = -=3D { -> + { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6)= -, }, -> + { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6)= -, }, -> + { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5)= -, }, -> + { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5)= -, }, -> + { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4210_CPU_DIV1(2, 4)= -, }, -> + { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4210_CPU_DIV1(2, 4)= -, }, -> + { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3)= -, }, -> + { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3)= -, }, -> + { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3)= -, }, -> + { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3)= -, }, -> + { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3)= -, }, -> + { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3)= -, }, -> + { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4210_CPU_DIV1(2, 3)= -, }, -> + { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4210_CPU_DIV1(2, 3)= -, }, +> +> +static const struct exynos_cpuclk_cfg_data e4212_armclk_d[] __initconst = { +> + { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), }, +> + { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), }, +> + { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), }, +> + { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), }, +> + { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4210_CPU_DIV1(2, 4), }, +> + { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4210_CPU_DIV1(2, 4), }, +> + { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), }, +> + { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), }, +> + { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), }, +> + { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), }, +> + { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), }, +> + { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), }, +> + { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4210_CPU_DIV1(2, 3), }, +> + { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4210_CPU_DIV1(2, 3), }, > + { 0 }, > +}; > + > +#define E4412_CPU_DIV1(cores, hpm, copy) \ > + (((cores) << 8) | ((hpm) << 4) | ((copy) << 0)) > + -> +static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = -=3D { -> + { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0,= - 6), }, -> + { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(6, 0,= - 6), }, -> + { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(6, 0,= - 5), }, -> + { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(5, 0,= - 5), }, -> + { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4412_CPU_DIV1(5, 0,= - 4), }, -> + { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4412_CPU_DIV1(4, 0,= - 4), }, -> + { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(4, 0,= - 3), }, -> + { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(3, 0,= - 3), }, -> + { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(3, 0,= - 3), }, -> + { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0,= - 3), }, -> + { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0,= - 3), }, -> + { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(1, 0,= - 3), }, -> + { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4412_CPU_DIV1(1, 0,= - 3), }, -> + { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4412_CPU_DIV1(0, 0,= - 3), }, +> +static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = { +> + { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), }, +> + { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(6, 0, 6), }, +> + { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(6, 0, 5), }, +> + { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(5, 0, 5), }, +> + { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4412_CPU_DIV1(5, 0, 4), }, +> + { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4412_CPU_DIV1(4, 0, 4), }, +> + { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(4, 0, 3), }, +> + { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(3, 0, 3), }, +> + { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(3, 0, 3), }, +> + { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), }, +> + { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), }, +> + { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), }, +> + { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), }, +> + { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4412_CPU_DIV1(0, 0, 3), }, > + { 0 }, > +}; > + > /* register exynos4 clocks */ > static void __init exynos4_clk_init(struct device_node *np, > enum exynos4_soc soc) -> @@ -1491,6 +1530,17 @@ static void __init exynos4_clk_init(struct device_= -node *np, +> @@ -1491,6 +1530,17 @@ static void __init exynos4_clk_init(struct device_node *np, > samsung_clk_register_fixed_factor(ctx, > exynos4x12_fixed_factor_clks, > ARRAY_SIZE(exynos4x12_fixed_factor_clks)); > + if (of_machine_is_compatible("samsung,exynos4412")) { -> + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armc= -lk", -> + mout_core_p4x12[0], mout_core_p4x12[1], 0= -x14200, -> + e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d= -), -> + CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS= -_DIV1); +> + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", +> + mout_core_p4x12[0], mout_core_p4x12[1], 0x14200, +> + e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d), +> + CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1); > + } else { -> + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armc= -lk", -> + mout_core_p4x12[0], mout_core_p4x12[1], 0= -x14200, -> + e4212_armclk_d, ARRAY_SIZE(e4212_armclk_d= -), -> + CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS= -_DIV1); +> + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", +> + mout_core_p4x12[0], mout_core_p4x12[1], 0x14200, +> + e4212_armclk_d, ARRAY_SIZE(e4212_armclk_d), +> + CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1); > + } > } -> = - +> > samsung_clk_register_alias(ctx, exynos4_aliases, -> -- = - +> -- > 1.9.1 -> = - +> > -- > To unsubscribe from this list: send the line "unsubscribe linux-kernel" in -> the body of a message to majordomo@vger.kernel.org +> the body of a message to majordomo at vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > Please read the FAQ at http://www.tux.org/lkml/ diff --git a/a/content_digest b/N2/content_digest index 4e4869f..ae6f757 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,40 +1,18 @@ "ref\01438868514-8814-1-git-send-email-b.zolnierkie@samsung.com\0" "ref\01438868514-8814-3-git-send-email-b.zolnierkie@samsung.com\0" - "From\0Michael Turquette <mturquette@baylibre.com>\0" - "Subject\0Re: [PATCH v4 2/6] clk: samsung: exynos4x12: add cpu clock configuration data and instantiate cpu clock\0" + "From\0mturquette@baylibre.com (Michael Turquette)\0" + "Subject\0[PATCH v4 2/6] clk: samsung: exynos4x12: add cpu clock configuration data and instantiate cpu clock\0" "Date\0Tue, 25 Aug 2015 11:40:13 -0700\0" - "To\0Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>" - Thomas Abraham <thomas.ab@samsung.com> - Sylwester Nawrocki <s.nawrocki@samsung.com> - Kukjin Kim <kgene.kim@samsung.com> - Kukjin Kim <kgene@kernel.org> - Viresh Kumar <viresh.kumar@linaro.org> - " Krzysztof Kozlowski <k.kozlowski@samsung.com>\0" - "Cc\0Tomasz Figa <tomasz.figa@gmail.com>" - Lukasz Majewski <l.majewski@samsung.com> - Heiko Stuebner <heiko@sntech.de> - Chanwoo Choi <cw00.choi@samsung.com> - Kevin Hilman <khilman@linaro.org> - Javier Martinez Canillas <javier@dowhile0.org> - Tobias Jakobi <tjakobi@math.uni-bielefeld.de> - Anand Moon <linux.amoon@gmail.com> - linux-samsung-soc@vger.kernel.org - linux-clk@vger.kernel.org - linux-pm@vger.kernel.org - linux-arm-kernel@lists.infradead.org - linux-kernel@vger.kernel.org - " b.zolnierkie@samsung.com\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Quoting Bartlomiej Zolnierkiewicz (2015-08-06 06:41:50)\n" "> With the addition of the new Samsung specific cpu-clock type, the\n" "> arm clock can be represented as a cpu-clock type. Add the CPU clock\n" "> configuration data and instantiate the CPU clock type for Exynos4x12.\n" - "> =\n" - "\n" + "> \n" "> Based on the earlier work by Thomas Abraham.\n" - "> =\n" - "\n" + "> \n" "> Cc: Tomasz Figa <tomasz.figa@gmail.com>\n" "> Cc: Michael Turquette <mturquette@baylibre.com>\n" "> Cc: Thomas Abraham <thomas.ab@samsung.com>\n" @@ -47,131 +25,84 @@ "Acked-by: Michael Turquette <mturquette@baylibre.com>\n" "\n" "> ---\n" - "> drivers/clk/samsung/clk-exynos4.c | 50 +++++++++++++++++++++++++++++++++=\n" - "++++++\n" + "> drivers/clk/samsung/clk-exynos4.c | 50 +++++++++++++++++++++++++++++++++++++++\n" "> 1 file changed, 50 insertions(+)\n" - "> =\n" - "\n" - "> diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-=\n" - "exynos4.c\n" + "> \n" + "> diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c\n" "> index 251f48d..7f370d3 100644\n" "> --- a/drivers/clk/samsung/clk-exynos4.c\n" "> +++ b/drivers/clk/samsung/clk-exynos4.c\n" - "> @@ -1398,6 +1398,45 @@ static const struct exynos_cpuclk_cfg_data e4210_a=\n" - "rmclk_d[] __initconst =3D {\n" + "> @@ -1398,6 +1398,45 @@ static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = {\n" "> { 0 },\n" "> };\n" - "> =\n" - "\n" - "> +static const struct exynos_cpuclk_cfg_data e4212_armclk_d[] __initconst =\n" - "=3D {\n" - "> + { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6)=\n" - ", },\n" - "> + { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6)=\n" - ", },\n" - "> + { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5)=\n" - ", },\n" - "> + { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5)=\n" - ", },\n" - "> + { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4210_CPU_DIV1(2, 4)=\n" - ", },\n" - "> + { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4210_CPU_DIV1(2, 4)=\n" - ", },\n" - "> + { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3)=\n" - ", },\n" - "> + { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3)=\n" - ", },\n" - "> + { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3)=\n" - ", },\n" - "> + { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3)=\n" - ", },\n" - "> + { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3)=\n" - ", },\n" - "> + { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3)=\n" - ", },\n" - "> + { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4210_CPU_DIV1(2, 3)=\n" - ", },\n" - "> + { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4210_CPU_DIV1(2, 3)=\n" - ", },\n" + "> \n" + "> +static const struct exynos_cpuclk_cfg_data e4212_armclk_d[] __initconst = {\n" + "> + { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },\n" + "> + { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },\n" + "> + { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },\n" + "> + { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },\n" + "> + { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4210_CPU_DIV1(2, 4), },\n" + "> + { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4210_CPU_DIV1(2, 4), },\n" + "> + { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },\n" + "> + { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },\n" + "> + { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },\n" + "> + { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },\n" + "> + { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },\n" + "> + { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },\n" + "> + { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4210_CPU_DIV1(2, 3), },\n" + "> + { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4210_CPU_DIV1(2, 3), },\n" "> + { 0 },\n" "> +};\n" "> +\n" "> +#define E4412_CPU_DIV1(cores, hpm, copy) \\\n" "> + (((cores) << 8) | ((hpm) << 4) | ((copy) << 0))\n" "> +\n" - "> +static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst =\n" - "=3D {\n" - "> + { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0,=\n" - " 6), },\n" - "> + { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(6, 0,=\n" - " 6), },\n" - "> + { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(6, 0,=\n" - " 5), },\n" - "> + { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(5, 0,=\n" - " 5), },\n" - "> + { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4412_CPU_DIV1(5, 0,=\n" - " 4), },\n" - "> + { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4412_CPU_DIV1(4, 0,=\n" - " 4), },\n" - "> + { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(4, 0,=\n" - " 3), },\n" - "> + { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(3, 0,=\n" - " 3), },\n" - "> + { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(3, 0,=\n" - " 3), },\n" - "> + { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0,=\n" - " 3), },\n" - "> + { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0,=\n" - " 3), },\n" - "> + { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(1, 0,=\n" - " 3), },\n" - "> + { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4412_CPU_DIV1(1, 0,=\n" - " 3), },\n" - "> + { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4412_CPU_DIV1(0, 0,=\n" - " 3), },\n" + "> +static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = {\n" + "> + { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), },\n" + "> + { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(6, 0, 6), },\n" + "> + { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(6, 0, 5), },\n" + "> + { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(5, 0, 5), },\n" + "> + { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4412_CPU_DIV1(5, 0, 4), },\n" + "> + { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4412_CPU_DIV1(4, 0, 4), },\n" + "> + { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(4, 0, 3), },\n" + "> + { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(3, 0, 3), },\n" + "> + { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(3, 0, 3), },\n" + "> + { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), },\n" + "> + { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), },\n" + "> + { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), },\n" + "> + { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), },\n" + "> + { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4412_CPU_DIV1(0, 0, 3), },\n" "> + { 0 },\n" "> +};\n" "> +\n" "> /* register exynos4 clocks */\n" "> static void __init exynos4_clk_init(struct device_node *np,\n" "> enum exynos4_soc soc)\n" - "> @@ -1491,6 +1530,17 @@ static void __init exynos4_clk_init(struct device_=\n" - "node *np,\n" + "> @@ -1491,6 +1530,17 @@ static void __init exynos4_clk_init(struct device_node *np,\n" "> samsung_clk_register_fixed_factor(ctx,\n" "> exynos4x12_fixed_factor_clks,\n" "> ARRAY_SIZE(exynos4x12_fixed_factor_clks));\n" "> + if (of_machine_is_compatible(\"samsung,exynos4412\")) {\n" - "> + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, \"armc=\n" - "lk\",\n" - "> + mout_core_p4x12[0], mout_core_p4x12[1], 0=\n" - "x14200,\n" - "> + e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d=\n" - "),\n" - "> + CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS=\n" - "_DIV1);\n" + "> + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, \"armclk\",\n" + "> + mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,\n" + "> + e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d),\n" + "> + CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);\n" "> + } else {\n" - "> + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, \"armc=\n" - "lk\",\n" - "> + mout_core_p4x12[0], mout_core_p4x12[1], 0=\n" - "x14200,\n" - "> + e4212_armclk_d, ARRAY_SIZE(e4212_armclk_d=\n" - "),\n" - "> + CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS=\n" - "_DIV1);\n" + "> + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, \"armclk\",\n" + "> + mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,\n" + "> + e4212_armclk_d, ARRAY_SIZE(e4212_armclk_d),\n" + "> + CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);\n" "> + }\n" "> }\n" - "> =\n" - "\n" + "> \n" "> samsung_clk_register_alias(ctx, exynos4_aliases,\n" - "> -- =\n" - "\n" + "> -- \n" "> 1.9.1\n" - "> =\n" - "\n" + "> \n" "> --\n" "> To unsubscribe from this list: send the line \"unsubscribe linux-kernel\" in\n" - "> the body of a message to majordomo@vger.kernel.org\n" + "> the body of a message to majordomo at vger.kernel.org\n" "> More majordomo info at http://vger.kernel.org/majordomo-info.html\n" > Please read the FAQ at http://www.tux.org/lkml/ -0e905af657cff5b9705abce80fb7a09d0990045e29649abb455a9a7d2a6e5a77 +587b8ea6ea57f7f07d0b641a0297e9cc518e0a4de3c8baae7170cbef9375229c
diff --git a/a/1.txt b/N3/1.txt index 9d81d8f..f4cb94c 100644 --- a/a/1.txt +++ b/N3/1.txt @@ -2,11 +2,9 @@ Quoting Bartlomiej Zolnierkiewicz (2015-08-06 06:41:50) > With the addition of the new Samsung specific cpu-clock type, the > arm clock can be represented as a cpu-clock type. Add the CPU clock > configuration data and instantiate the CPU clock type for Exynos4x12. -> = - +> > Based on the earlier work by Thomas Abraham. -> = - +> > Cc: Tomasz Figa <tomasz.figa@gmail.com> > Cc: Michael Turquette <mturquette@baylibre.com> > Cc: Thomas Abraham <thomas.ab@samsung.com> @@ -19,127 +17,80 @@ Quoting Bartlomiej Zolnierkiewicz (2015-08-06 06:41:50) Acked-by: Michael Turquette <mturquette@baylibre.com> > --- -> drivers/clk/samsung/clk-exynos4.c | 50 +++++++++++++++++++++++++++++++++= -++++++ +> drivers/clk/samsung/clk-exynos4.c | 50 +++++++++++++++++++++++++++++++++++++++ > 1 file changed, 50 insertions(+) -> = - -> diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-= -exynos4.c +> +> diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c > index 251f48d..7f370d3 100644 > --- a/drivers/clk/samsung/clk-exynos4.c > +++ b/drivers/clk/samsung/clk-exynos4.c -> @@ -1398,6 +1398,45 @@ static const struct exynos_cpuclk_cfg_data e4210_a= -rmclk_d[] __initconst =3D { +> @@ -1398,6 +1398,45 @@ static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = { > { 0 }, > }; -> = - -> +static const struct exynos_cpuclk_cfg_data e4212_armclk_d[] __initconst = -=3D { -> + { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6)= -, }, -> + { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6)= -, }, -> + { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5)= -, }, -> + { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5)= -, }, -> + { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4210_CPU_DIV1(2, 4)= -, }, -> + { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4210_CPU_DIV1(2, 4)= -, }, -> + { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3)= -, }, -> + { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3)= -, }, -> + { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3)= -, }, -> + { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3)= -, }, -> + { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3)= -, }, -> + { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3)= -, }, -> + { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4210_CPU_DIV1(2, 3)= -, }, -> + { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4210_CPU_DIV1(2, 3)= -, }, +> +> +static const struct exynos_cpuclk_cfg_data e4212_armclk_d[] __initconst = { +> + { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), }, +> + { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), }, +> + { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), }, +> + { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), }, +> + { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4210_CPU_DIV1(2, 4), }, +> + { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4210_CPU_DIV1(2, 4), }, +> + { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), }, +> + { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), }, +> + { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), }, +> + { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), }, +> + { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), }, +> + { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), }, +> + { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4210_CPU_DIV1(2, 3), }, +> + { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4210_CPU_DIV1(2, 3), }, > + { 0 }, > +}; > + > +#define E4412_CPU_DIV1(cores, hpm, copy) \ > + (((cores) << 8) | ((hpm) << 4) | ((copy) << 0)) > + -> +static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = -=3D { -> + { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0,= - 6), }, -> + { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(6, 0,= - 6), }, -> + { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(6, 0,= - 5), }, -> + { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(5, 0,= - 5), }, -> + { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4412_CPU_DIV1(5, 0,= - 4), }, -> + { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4412_CPU_DIV1(4, 0,= - 4), }, -> + { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(4, 0,= - 3), }, -> + { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(3, 0,= - 3), }, -> + { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(3, 0,= - 3), }, -> + { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0,= - 3), }, -> + { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0,= - 3), }, -> + { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(1, 0,= - 3), }, -> + { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4412_CPU_DIV1(1, 0,= - 3), }, -> + { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4412_CPU_DIV1(0, 0,= - 3), }, +> +static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = { +> + { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), }, +> + { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(6, 0, 6), }, +> + { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(6, 0, 5), }, +> + { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(5, 0, 5), }, +> + { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4412_CPU_DIV1(5, 0, 4), }, +> + { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4412_CPU_DIV1(4, 0, 4), }, +> + { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(4, 0, 3), }, +> + { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(3, 0, 3), }, +> + { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(3, 0, 3), }, +> + { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), }, +> + { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), }, +> + { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), }, +> + { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), }, +> + { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4412_CPU_DIV1(0, 0, 3), }, > + { 0 }, > +}; > + > /* register exynos4 clocks */ > static void __init exynos4_clk_init(struct device_node *np, > enum exynos4_soc soc) -> @@ -1491,6 +1530,17 @@ static void __init exynos4_clk_init(struct device_= -node *np, +> @@ -1491,6 +1530,17 @@ static void __init exynos4_clk_init(struct device_node *np, > samsung_clk_register_fixed_factor(ctx, > exynos4x12_fixed_factor_clks, > ARRAY_SIZE(exynos4x12_fixed_factor_clks)); > + if (of_machine_is_compatible("samsung,exynos4412")) { -> + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armc= -lk", -> + mout_core_p4x12[0], mout_core_p4x12[1], 0= -x14200, -> + e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d= -), -> + CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS= -_DIV1); +> + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", +> + mout_core_p4x12[0], mout_core_p4x12[1], 0x14200, +> + e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d), +> + CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1); > + } else { -> + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armc= -lk", -> + mout_core_p4x12[0], mout_core_p4x12[1], 0= -x14200, -> + e4212_armclk_d, ARRAY_SIZE(e4212_armclk_d= -), -> + CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS= -_DIV1); +> + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", +> + mout_core_p4x12[0], mout_core_p4x12[1], 0x14200, +> + e4212_armclk_d, ARRAY_SIZE(e4212_armclk_d), +> + CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1); > + } > } -> = - +> > samsung_clk_register_alias(ctx, exynos4_aliases, -> -- = - +> -- > 1.9.1 -> = - +> > -- > To unsubscribe from this list: send the line "unsubscribe linux-kernel" in > the body of a message to majordomo@vger.kernel.org diff --git a/a/content_digest b/N3/content_digest index 4e4869f..3a9ef94 100644 --- a/a/content_digest +++ b/N3/content_digest @@ -30,11 +30,9 @@ "> With the addition of the new Samsung specific cpu-clock type, the\n" "> arm clock can be represented as a cpu-clock type. Add the CPU clock\n" "> configuration data and instantiate the CPU clock type for Exynos4x12.\n" - "> =\n" - "\n" + "> \n" "> Based on the earlier work by Thomas Abraham.\n" - "> =\n" - "\n" + "> \n" "> Cc: Tomasz Figa <tomasz.figa@gmail.com>\n" "> Cc: Michael Turquette <mturquette@baylibre.com>\n" "> Cc: Thomas Abraham <thomas.ab@samsung.com>\n" @@ -47,131 +45,84 @@ "Acked-by: Michael Turquette <mturquette@baylibre.com>\n" "\n" "> ---\n" - "> drivers/clk/samsung/clk-exynos4.c | 50 +++++++++++++++++++++++++++++++++=\n" - "++++++\n" + "> drivers/clk/samsung/clk-exynos4.c | 50 +++++++++++++++++++++++++++++++++++++++\n" "> 1 file changed, 50 insertions(+)\n" - "> =\n" - "\n" - "> diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-=\n" - "exynos4.c\n" + "> \n" + "> diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c\n" "> index 251f48d..7f370d3 100644\n" "> --- a/drivers/clk/samsung/clk-exynos4.c\n" "> +++ b/drivers/clk/samsung/clk-exynos4.c\n" - "> @@ -1398,6 +1398,45 @@ static const struct exynos_cpuclk_cfg_data e4210_a=\n" - "rmclk_d[] __initconst =3D {\n" + "> @@ -1398,6 +1398,45 @@ static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = {\n" "> { 0 },\n" "> };\n" - "> =\n" - "\n" - "> +static const struct exynos_cpuclk_cfg_data e4212_armclk_d[] __initconst =\n" - "=3D {\n" - "> + { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6)=\n" - ", },\n" - "> + { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6)=\n" - ", },\n" - "> + { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5)=\n" - ", },\n" - "> + { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5)=\n" - ", },\n" - "> + { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4210_CPU_DIV1(2, 4)=\n" - ", },\n" - "> + { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4210_CPU_DIV1(2, 4)=\n" - ", },\n" - "> + { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3)=\n" - ", },\n" - "> + { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3)=\n" - ", },\n" - "> + { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3)=\n" - ", },\n" - "> + { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3)=\n" - ", },\n" - "> + { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3)=\n" - ", },\n" - "> + { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3)=\n" - ", },\n" - "> + { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4210_CPU_DIV1(2, 3)=\n" - ", },\n" - "> + { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4210_CPU_DIV1(2, 3)=\n" - ", },\n" + "> \n" + "> +static const struct exynos_cpuclk_cfg_data e4212_armclk_d[] __initconst = {\n" + "> + { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },\n" + "> + { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },\n" + "> + { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },\n" + "> + { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },\n" + "> + { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4210_CPU_DIV1(2, 4), },\n" + "> + { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4210_CPU_DIV1(2, 4), },\n" + "> + { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },\n" + "> + { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },\n" + "> + { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },\n" + "> + { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },\n" + "> + { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },\n" + "> + { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },\n" + "> + { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4210_CPU_DIV1(2, 3), },\n" + "> + { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4210_CPU_DIV1(2, 3), },\n" "> + { 0 },\n" "> +};\n" "> +\n" "> +#define E4412_CPU_DIV1(cores, hpm, copy) \\\n" "> + (((cores) << 8) | ((hpm) << 4) | ((copy) << 0))\n" "> +\n" - "> +static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst =\n" - "=3D {\n" - "> + { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0,=\n" - " 6), },\n" - "> + { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(6, 0,=\n" - " 6), },\n" - "> + { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(6, 0,=\n" - " 5), },\n" - "> + { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(5, 0,=\n" - " 5), },\n" - "> + { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4412_CPU_DIV1(5, 0,=\n" - " 4), },\n" - "> + { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4412_CPU_DIV1(4, 0,=\n" - " 4), },\n" - "> + { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(4, 0,=\n" - " 3), },\n" - "> + { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(3, 0,=\n" - " 3), },\n" - "> + { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(3, 0,=\n" - " 3), },\n" - "> + { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0,=\n" - " 3), },\n" - "> + { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0,=\n" - " 3), },\n" - "> + { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(1, 0,=\n" - " 3), },\n" - "> + { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4412_CPU_DIV1(1, 0,=\n" - " 3), },\n" - "> + { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4412_CPU_DIV1(0, 0,=\n" - " 3), },\n" + "> +static const struct exynos_cpuclk_cfg_data e4412_armclk_d[] __initconst = {\n" + "> + { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(7, 0, 6), },\n" + "> + { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4412_CPU_DIV1(6, 0, 6), },\n" + "> + { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(6, 0, 5), },\n" + "> + { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4412_CPU_DIV1(5, 0, 5), },\n" + "> + { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4412_CPU_DIV1(5, 0, 4), },\n" + "> + { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4412_CPU_DIV1(4, 0, 4), },\n" + "> + { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(4, 0, 3), },\n" + "> + { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4412_CPU_DIV1(3, 0, 3), },\n" + "> + { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(3, 0, 3), },\n" + "> + { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), },\n" + "> + { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(2, 0, 3), },\n" + "> + { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), },\n" + "> + { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4412_CPU_DIV1(1, 0, 3), },\n" + "> + { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4412_CPU_DIV1(0, 0, 3), },\n" "> + { 0 },\n" "> +};\n" "> +\n" "> /* register exynos4 clocks */\n" "> static void __init exynos4_clk_init(struct device_node *np,\n" "> enum exynos4_soc soc)\n" - "> @@ -1491,6 +1530,17 @@ static void __init exynos4_clk_init(struct device_=\n" - "node *np,\n" + "> @@ -1491,6 +1530,17 @@ static void __init exynos4_clk_init(struct device_node *np,\n" "> samsung_clk_register_fixed_factor(ctx,\n" "> exynos4x12_fixed_factor_clks,\n" "> ARRAY_SIZE(exynos4x12_fixed_factor_clks));\n" "> + if (of_machine_is_compatible(\"samsung,exynos4412\")) {\n" - "> + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, \"armc=\n" - "lk\",\n" - "> + mout_core_p4x12[0], mout_core_p4x12[1], 0=\n" - "x14200,\n" - "> + e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d=\n" - "),\n" - "> + CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS=\n" - "_DIV1);\n" + "> + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, \"armclk\",\n" + "> + mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,\n" + "> + e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d),\n" + "> + CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);\n" "> + } else {\n" - "> + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, \"armc=\n" - "lk\",\n" - "> + mout_core_p4x12[0], mout_core_p4x12[1], 0=\n" - "x14200,\n" - "> + e4212_armclk_d, ARRAY_SIZE(e4212_armclk_d=\n" - "),\n" - "> + CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS=\n" - "_DIV1);\n" + "> + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, \"armclk\",\n" + "> + mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,\n" + "> + e4212_armclk_d, ARRAY_SIZE(e4212_armclk_d),\n" + "> + CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);\n" "> + }\n" "> }\n" - "> =\n" - "\n" + "> \n" "> samsung_clk_register_alias(ctx, exynos4_aliases,\n" - "> -- =\n" - "\n" + "> -- \n" "> 1.9.1\n" - "> =\n" - "\n" + "> \n" "> --\n" "> To unsubscribe from this list: send the line \"unsubscribe linux-kernel\" in\n" "> the body of a message to majordomo@vger.kernel.org\n" "> More majordomo info at http://vger.kernel.org/majordomo-info.html\n" > Please read the FAQ at http://www.tux.org/lkml/ -0e905af657cff5b9705abce80fb7a09d0990045e29649abb455a9a7d2a6e5a77 +5fac7ccb0eb8184e28aa0d231039b7c0b36a7f5ea49d90cf5872737556815a26
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