All of lore.kernel.org
 help / color / mirror / Atom feed
diff for duplicates of <20150826184009.GA4171@broadcom.com>

diff --git a/a/1.txt b/N1/1.txt
index 836ca0f..64e6a5c 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -11,7 +11,7 @@ mailing list would be enough of a catch all.  My apologies.  I'll CC
 everyone listed as a maintainer on all of the patches in the future.
 
 > 
-> On Thu, Aug 20, 2015 at 10:46 AM, Jon Mason <jonmason@broadcom.com> wrote:
+> On Thu, Aug 20, 2015 at 10:46 AM, Jon Mason <jonmason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> wrote:
 > > Add a very minimalistic set of Northstar Plus Device Tree files which
 > > describes the SoC and the BCM958625 implementation.  The perpherials
 > > described are:
@@ -22,10 +22,10 @@ everyone listed as a maintainer on all of the patches in the future.
 > > PL310 L2 Cache
 > > ARM A9 Global timer
 > >
-> > Signed-off-by: Jon Mason <jonmason@broadcom.com>
-> > Signed-off-by: Kapil Hali <kapilh@broadcom.com>
-> > Reviewed-by: Ray Jui <rjui@broadcom.com>
-> > Reviewed-by: Scott Branden <sbranden@broadcom.com>
+> > Signed-off-by: Jon Mason <jonmason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
+> > Signed-off-by: Kapil Hali <kapilh-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
+> > Reviewed-by: Ray Jui <rjui-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
+> > Reviewed-by: Scott Branden <sbranden-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
 > 
 > Seeing reviewed-by already attached to a v1 of a patchset has limited
 > value for someone on the outside.
@@ -102,7 +102,7 @@ If this is preferred to be GPL v2, then I will happily comply.
 > > +               #address-cells = <1>;
 > > +               #size-cells = <0>;
 > > +
-> > +               cpu at 0 {
+> > +               cpu@0 {
 > > +                       device_type = "cpu";
 > > +                       compatible = "arm,cortex-a9";
 > > +                       next-level-cache = <&L2>;
@@ -122,7 +122,7 @@ If this is preferred to be GPL v2, then I will happily comply.
 > > +               };
 > > +       };
 > > +
-> > +       uart0: serial at 18000300 {
+> > +       uart0: serial@18000300 {
 > > +               compatible = "ns16550a";
 > > +               reg = <0x18000300 0x100>;
 > > +               interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
@@ -130,7 +130,7 @@ If this is preferred to be GPL v2, then I will happily comply.
 > > +               status = "disabled";
 > > +       };
 > > +
-> > +       uart1: serial at 18000400 {
+> > +       uart1: serial@18000400 {
 > > +               compatible = "ns16550a";
 > > +               reg = <0x18000400 0x100>;
 > > +               interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
@@ -138,7 +138,7 @@ If this is preferred to be GPL v2, then I will happily comply.
 > > +               status = "disabled";
 > > +       };
 > > +
-> > +       gic: interrupt-controller at 19021000 {
+> > +       gic: interrupt-controller@19021000 {
 > > +               compatible = "arm,cortex-a9-gic";
 > > +               #interrupt-cells = <3>;
 > > +               #address-cells = <0>;
@@ -154,7 +154,7 @@ If this is preferred to be GPL v2, then I will happily comply.
 > > +               cache-level = <2>;
 > > +       };
 > > +
-> > +       timer at 19020200 {
+> > +       timer@19020200 {
 > > +               compatible = "arm,cortex-a9-global-timer";
 > > +               reg = <0x19020200 0x100>;
 > > +               interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
@@ -225,11 +225,11 @@ shell without issue.
 
 > 
 > > +
-> > +       uart0: serial at 18000300 {
+> > +       uart0: serial@18000300 {
 > > +               status = "okay";
 > > +       };
 > > +
-> > +       uart1: serial at 18000400 {
+> > +       uart1: serial@18000400 {
 > > +               status = "okay";
 > > +       };
 > 
@@ -251,3 +251,7 @@ Jon
 > 
 > 
 > -Olof
+--
+To unsubscribe from this list: send the line "unsubscribe devicetree" in
+the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
+More majordomo info at  http://vger.kernel.org/majordomo-info.html
diff --git a/a/content_digest b/N1/content_digest
index a4a7812..4db68ce 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -1,9 +1,20 @@
  "ref\01440092804-25726-1-git-send-email-jonmason@broadcom.com\0"
  "ref\0CAOesGMhE40_mfZCD2PqcTObE_Gz_6rKFwhf3-6kZY4n9Yxn2rQ@mail.gmail.com\0"
- "From\0jonmason@broadcom.com (Jon Mason)\0"
- "Subject\0[PATCH 2/5] ARM: NSP: add minimal Northstar Plus device tree\0"
+ "ref\0CAOesGMhE40_mfZCD2PqcTObE_Gz_6rKFwhf3-6kZY4n9Yxn2rQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org\0"
+ "From\0Jon Mason <jonmason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>\0"
+ "Subject\0Re: [PATCH 2/5] ARM: NSP: add minimal Northstar Plus device tree\0"
  "Date\0Wed, 26 Aug 2015 14:40:10 -0400\0"
- "To\0linux-arm-kernel@lists.infradead.org\0"
+ "To\0Olof Johansson <olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org>\0"
+ "Cc\0Florian Fainelli <f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>"
+  Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
+  Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
+  Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
+  Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>
+  Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
+  devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
+  linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>
+  Broadcom Kernel Feedback List <bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
+ " Kapil Hali <kapilh-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>\0"
  "\00:1\0"
  "b\0"
  "On Tue, Aug 25, 2015 at 04:36:45PM -0700, Olof Johansson wrote:\n"
@@ -19,7 +30,7 @@
  "everyone listed as a maintainer on all of the patches in the future.\n"
  "\n"
  "> \n"
- "> On Thu, Aug 20, 2015 at 10:46 AM, Jon Mason <jonmason@broadcom.com> wrote:\n"
+ "> On Thu, Aug 20, 2015 at 10:46 AM, Jon Mason <jonmason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org> wrote:\n"
  "> > Add a very minimalistic set of Northstar Plus Device Tree files which\n"
  "> > describes the SoC and the BCM958625 implementation.  The perpherials\n"
  "> > described are:\n"
@@ -30,10 +41,10 @@
  "> > PL310 L2 Cache\n"
  "> > ARM A9 Global timer\n"
  "> >\n"
- "> > Signed-off-by: Jon Mason <jonmason@broadcom.com>\n"
- "> > Signed-off-by: Kapil Hali <kapilh@broadcom.com>\n"
- "> > Reviewed-by: Ray Jui <rjui@broadcom.com>\n"
- "> > Reviewed-by: Scott Branden <sbranden@broadcom.com>\n"
+ "> > Signed-off-by: Jon Mason <jonmason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>\n"
+ "> > Signed-off-by: Kapil Hali <kapilh-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>\n"
+ "> > Reviewed-by: Ray Jui <rjui-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>\n"
+ "> > Reviewed-by: Scott Branden <sbranden-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>\n"
  "> \n"
  "> Seeing reviewed-by already attached to a v1 of a patchset has limited\n"
  "> value for someone on the outside.\n"
@@ -110,7 +121,7 @@
  "> > +               #address-cells = <1>;\n"
  "> > +               #size-cells = <0>;\n"
  "> > +\n"
- "> > +               cpu at 0 {\n"
+ "> > +               cpu@0 {\n"
  "> > +                       device_type = \"cpu\";\n"
  "> > +                       compatible = \"arm,cortex-a9\";\n"
  "> > +                       next-level-cache = <&L2>;\n"
@@ -130,7 +141,7 @@
  "> > +               };\n"
  "> > +       };\n"
  "> > +\n"
- "> > +       uart0: serial at 18000300 {\n"
+ "> > +       uart0: serial@18000300 {\n"
  "> > +               compatible = \"ns16550a\";\n"
  "> > +               reg = <0x18000300 0x100>;\n"
  "> > +               interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -138,7 +149,7 @@
  "> > +               status = \"disabled\";\n"
  "> > +       };\n"
  "> > +\n"
- "> > +       uart1: serial at 18000400 {\n"
+ "> > +       uart1: serial@18000400 {\n"
  "> > +               compatible = \"ns16550a\";\n"
  "> > +               reg = <0x18000400 0x100>;\n"
  "> > +               interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -146,7 +157,7 @@
  "> > +               status = \"disabled\";\n"
  "> > +       };\n"
  "> > +\n"
- "> > +       gic: interrupt-controller at 19021000 {\n"
+ "> > +       gic: interrupt-controller@19021000 {\n"
  "> > +               compatible = \"arm,cortex-a9-gic\";\n"
  "> > +               #interrupt-cells = <3>;\n"
  "> > +               #address-cells = <0>;\n"
@@ -162,7 +173,7 @@
  "> > +               cache-level = <2>;\n"
  "> > +       };\n"
  "> > +\n"
- "> > +       timer at 19020200 {\n"
+ "> > +       timer@19020200 {\n"
  "> > +               compatible = \"arm,cortex-a9-global-timer\";\n"
  "> > +               reg = <0x19020200 0x100>;\n"
  "> > +               interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -233,11 +244,11 @@
  "\n"
  "> \n"
  "> > +\n"
- "> > +       uart0: serial at 18000300 {\n"
+ "> > +       uart0: serial@18000300 {\n"
  "> > +               status = \"okay\";\n"
  "> > +       };\n"
  "> > +\n"
- "> > +       uart1: serial at 18000400 {\n"
+ "> > +       uart1: serial@18000400 {\n"
  "> > +               status = \"okay\";\n"
  "> > +       };\n"
  "> \n"
@@ -258,6 +269,10 @@
  "> \n"
  "> \n"
  "> \n"
- > -Olof
+ "> -Olof\n"
+ "--\n"
+ "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n"
+ "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n"
+ More majordomo info at  http://vger.kernel.org/majordomo-info.html
 
-24a97c9d6b54910b70147494ff43e7ce801390345a28f817d8192ad3ff1eb9f6
+e4937c7e580d0b250a6c5320cdf9ef434c4e1ae5c9ba9f4655cbc288dac7a633

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.