From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH v2] drm/i915: Limit the number of loops for reading a split 64bit register Date: Tue, 8 Sep 2015 21:00:59 +0200 Message-ID: <20150908190059.GG2767@phenom.ffwll.local> References: <8737ypnl4f.fsf@intel.com> <1441718233-29112-1-git-send-email-chris@chris-wilson.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mail-wi0-f170.google.com (mail-wi0-f170.google.com [209.85.212.170]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0603E6E412 for ; Tue, 8 Sep 2015 11:58:19 -0700 (PDT) Received: by wicfx3 with SMTP id fx3so125790682wic.0 for ; Tue, 08 Sep 2015 11:58:17 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1441718233-29112-1-git-send-email-chris@chris-wilson.co.uk> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Chris Wilson Cc: Daniel Vetter , intel-gfx@lists.freedesktop.org, stable@vger.kernel.org List-Id: intel-gfx@lists.freedesktop.org T24gVHVlLCBTZXAgMDgsIDIwMTUgYXQgMDI6MTc6MTNQTSArMDEwMCwgQ2hyaXMgV2lsc29uIHdy b3RlOgo+IEluIEk5MTVfUkVBRDY0XzJ4MzIgd2UgYXR0ZW1wdCB0byByZWFkIGEgNjRiaXQgcmVn aXN0ZXIgdXNpbmcgMiAzMmJpdAo+IHJlYWRzLiBEdWUgdG8gdGhlIG5hdHVyZSBvZiB0aGUgcmVn aXN0ZXJzIHdlIHRyeSB0byByZWFkIGluIHRoaXMgbWFubmVyLAo+IHRoZXkgbWF5IGluY3JlbWVu dCBiZXR3ZWVuIHRoZSB0d28gaW5zdHJ1Y3Rpb24gKGUuZy4gYSB0aW1lc3RhbXAKPiBjb3VudGVy KS4gVG8ga2VlcCB0aGUgcmVzdWx0IGFjY3VyYXRlLCB3ZSByZXBlYXQgdGhlIHJlYWQgaWYgd2Ug ZGV0ZWN0Cj4gYW4gb3ZlcmZsb3cgKGkuZS4gdGhlIHVwcGVyIHZhbHVlIHZhcmllcykuIEhvd2V2 ZXIsIHNvbWUgaGFyd2FyZSBpcyBqdXN0Cj4gcGxhaW4gZmxha3kgYW5kIG1heSBlbmRsZXNzIGxv b3AgYXMgdGhlIHRoZSB1cHBlciAzMmJpdHMgYXJlIG5vdCBzdGFibGUuCj4gSnVzdCBnaXZlIHVw IGFmdGVyIGEgY291cGxlIG9mIHRyaWVzIGFuZCByZXBvcnQgd2hhdGV2ZXIgd2UgcmVhZCBsYXN0 Lgo+IAo+IHYyOiBVc2UgdGhlIG1vc3QgcmVjZW50IHZhbHVlcyB3aGVuIGVycmluZyBvdXQgb24g YW4gdW5zdGFibGUgcmVnaXN0ZXIuCj4gCj4gUmVwb3J0ZWQtYnk6IHJ1c3NpYW5uZXVyb21hbmNl ckB5YS5ydQo+IEJ1Z3ppbGxhOiBodHRwczovL2J1Z3MuZnJlZWRlc2t0b3Aub3JnL3Nob3dfYnVn LmNnaT9pZD05MTkwNgo+IFNpZ25lZC1vZmYtYnk6IENocmlzIFdpbHNvbiA8Y2hyaXNAY2hyaXMt d2lsc29uLmNvLnVrPgo+IENjOiBNaWNoYcWCIFdpbmlhcnNraSA8bWljaGFsLndpbmlhcnNraUBp bnRlbC5jb20+Cj4gQ2M6IERhbmllbCBWZXR0ZXIgPGRhbmllbC52ZXR0ZXJAZmZ3bGwuY2g+Cj4g Q2M6IEphbmkgTmlrdWxhIDxqYW5pLm5pa3VsYUBsaW51eC5pbnRlbC5jb20+Cj4gQ2M6IHN0YWJs ZUB2Z2VyLmtlcm5lbC5vcmcKClN0aWxsIFJldmlld2VkLWJ5OiBEYW5pZWwgVmV0dGVyIDxkYW5p ZWwudmV0dGVyQGZmd2xsLmNoPgoKPiAtLS0KPiAgZHJpdmVycy9ncHUvZHJtL2k5MTUvaTkxNV9k cnYuaCB8IDEwICsrKysrLS0tLS0KPiAgMSBmaWxlIGNoYW5nZWQsIDUgaW5zZXJ0aW9ucygrKSwg NSBkZWxldGlvbnMoLSkKPiAKPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvaTkx NV9kcnYuaCBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2k5MTVfZHJ2LmgKPiBpbmRleCAxMjg3MDA3 M2Q1OGYuLjUxYTg4ZTcwYTZmNyAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9p OTE1X2Rydi5oCj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvaTkxNV9kcnYuaAo+IEBAIC0z NDAyLDEzICszNDAyLDEzIEBAIGludCBpbnRlbF9mcmVxX29wY29kZShzdHJ1Y3QgZHJtX2k5MTVf cHJpdmF0ZSAqZGV2X3ByaXYsIGludCB2YWwpOwo+ICAjZGVmaW5lIEk5MTVfUkVBRDY0KHJlZykJ ZGV2X3ByaXYtPnVuY29yZS5mdW5jcy5tbWlvX3JlYWRxKGRldl9wcml2LCAocmVnKSwgdHJ1ZSkK PiAgCj4gICNkZWZpbmUgSTkxNV9SRUFENjRfMngzMihsb3dlcl9yZWcsIHVwcGVyX3JlZykgKHsJ CQlcCj4gLQl1MzIgdXBwZXIsIGxvd2VyLCB0bXA7CQkJCQkJXAo+IC0JdG1wID0gSTkxNV9SRUFE KHVwcGVyX3JlZyk7CQkJCQlcCj4gKwl1MzIgdXBwZXIsIGxvd2VyLCBvbGRfdXBwZXIsIGxvb3Ag PSAwOwkJCQlcCj4gKwl1cHBlciA9IEk5MTVfUkVBRCh1cHBlcl9yZWcpOwkJCQkJXAo+ICAJZG8g ewkJCQkJCQkJXAo+IC0JCXVwcGVyID0gdG1wOwkJCQkJCVwKPiArCQlvbGRfdXBwZXIgPSB1cHBl cjsJCQkJCVwKPiAgCQlsb3dlciA9IEk5MTVfUkVBRChsb3dlcl9yZWcpOwkJCQlcCj4gLQkJdG1w ID0gSTkxNV9SRUFEKHVwcGVyX3JlZyk7CQkJCVwKPiAtCX0gd2hpbGUgKHVwcGVyICE9IHRtcCk7 CQkJCQkJXAo+ICsJCXVwcGVyID0gSTkxNV9SRUFEKHVwcGVyX3JlZyk7CQkJCVwKPiArCX0gd2hp bGUgKHVwcGVyICE9IG9sZF91cHBlciAmJiBsb29wKysgPCAyKTsJCQlcCj4gIAkodTY0KXVwcGVy IDw8IDMyIHwgbG93ZXI7IH0pCj4gIAo+ICAjZGVmaW5lIFBPU1RJTkdfUkVBRChyZWcpCSh2b2lk KUk5MTVfUkVBRF9OT1RSQUNFKHJlZykKPiAtLSAKPiAyLjUuMQo+IAoKLS0gCkRhbmllbCBWZXR0 ZXIKU29mdHdhcmUgRW5naW5lZXIsIEludGVsIENvcnBvcmF0aW9uCmh0dHA6Ly9ibG9nLmZmd2xs LmNoCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCkludGVs LWdmeCBtYWlsaW5nIGxpc3QKSW50ZWwtZ2Z4QGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwOi8v bGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4Cg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wi0-f180.google.com ([209.85.212.180]:33657 "EHLO mail-wi0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751136AbbIHS6T (ORCPT ); Tue, 8 Sep 2015 14:58:19 -0400 Received: by wiclk2 with SMTP id lk2so131372431wic.0 for ; Tue, 08 Sep 2015 11:58:17 -0700 (PDT) Date: Tue, 8 Sep 2015 21:00:59 +0200 From: Daniel Vetter To: Chris Wilson Cc: intel-gfx@lists.freedesktop.org, =?utf-8?Q?Micha=C5=82?= Winiarski , Daniel Vetter , Jani Nikula , stable@vger.kernel.org Subject: Re: [PATCH v2] drm/i915: Limit the number of loops for reading a split 64bit register Message-ID: <20150908190059.GG2767@phenom.ffwll.local> References: <8737ypnl4f.fsf@intel.com> <1441718233-29112-1-git-send-email-chris@chris-wilson.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1441718233-29112-1-git-send-email-chris@chris-wilson.co.uk> Sender: stable-owner@vger.kernel.org List-ID: On Tue, Sep 08, 2015 at 02:17:13PM +0100, Chris Wilson wrote: > In I915_READ64_2x32 we attempt to read a 64bit register using 2 32bit > reads. Due to the nature of the registers we try to read in this manner, > they may increment between the two instruction (e.g. a timestamp > counter). To keep the result accurate, we repeat the read if we detect > an overflow (i.e. the upper value varies). However, some harware is just > plain flaky and may endless loop as the the upper 32bits are not stable. > Just give up after a couple of tries and report whatever we read last. > > v2: Use the most recent values when erring out on an unstable register. > > Reported-by: russianneuromancer@ya.ru > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91906 > Signed-off-by: Chris Wilson > Cc: Michał Winiarski > Cc: Daniel Vetter > Cc: Jani Nikula > Cc: stable@vger.kernel.org Still Reviewed-by: Daniel Vetter > --- > drivers/gpu/drm/i915/i915_drv.h | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 12870073d58f..51a88e70a6f7 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -3402,13 +3402,13 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); > #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) > > #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ > - u32 upper, lower, tmp; \ > - tmp = I915_READ(upper_reg); \ > + u32 upper, lower, old_upper, loop = 0; \ > + upper = I915_READ(upper_reg); \ > do { \ > - upper = tmp; \ > + old_upper = upper; \ > lower = I915_READ(lower_reg); \ > - tmp = I915_READ(upper_reg); \ > - } while (upper != tmp); \ > + upper = I915_READ(upper_reg); \ > + } while (upper != old_upper && loop++ < 2); \ > (u64)upper << 32 | lower; }) > > #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) > -- > 2.5.1 > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch