From: Thierry Reding <thierry.reding@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 1/2] ARM: tegra124: Clear IDDQ when enabling PLLC
Date: Thu, 10 Sep 2015 14:01:21 +0200 [thread overview]
Message-ID: <20150910120119.GA21542@ulmo.nvidia.com> (raw)
In-Reply-To: <55F0FAFE.1080005@wwwdotorg.org>
On Wed, Sep 09, 2015 at 08:37:34PM -0700, Stephen Warren wrote:
> On 09/08/2015 02:38 AM, Thierry Reding wrote:
> > From: Thierry Reding <treding@nvidia.com>
> >
> > Enabling a PLL while IDDQ is high. The Linux kernel checks for this
>
> Is there some word missing in/at-the-end-of that first sentence? It
> doesn't seem complete.
Erm... yeah. This should read:
"Enabling a PLL while IDDQ is high is not allowed."
or "not supported" or similar. Interestingly doing this does seem to
work. Unless we don't actually use PLLC yet.
Thierry
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prev parent reply other threads:[~2015-09-10 12:01 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-08 9:38 [U-Boot] [PATCH 1/2] ARM: tegra124: Clear IDDQ when enabling PLLC Thierry Reding
2015-09-08 9:38 ` [U-Boot] [PATCH 2/2] ARM: tegra114: " Thierry Reding
2015-09-08 15:58 ` Tom Warren
2015-09-10 12:09 ` Thierry Reding
2015-09-09 20:40 ` [U-Boot] [PATCH 1/2] ARM: tegra124: " Nicolas Chauvet
2015-09-10 3:37 ` Stephen Warren
2015-09-10 12:01 ` Thierry Reding [this message]
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