From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755667AbbILXTU (ORCPT ); Sat, 12 Sep 2015 19:19:20 -0400 Received: from wtarreau.pck.nerim.net ([62.212.114.60]:9294 "EHLO 1wt.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755436AbbILXMj (ORCPT ); Sat, 12 Sep 2015 19:12:39 -0400 Message-Id: <20150912225608.071797495@1wt.eu> User-Agent: quilt/0.63-1 Date: Sun, 13 Sep 2015 00:56:41 +0200 From: Willy Tarreau To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Ralf Baechle , Ben Hutchings , Willy Tarreau Subject: [PATCH 2.6.32 35/62] MIPS: Fix cpu_has_mips_r2_exec_hazard. MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15 In-Reply-To: <08d3b586eb2e764308c3de9ee398a17c@local> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 2.6.32-longterm review patch. If anyone has any objections, please let me know. ------------------ From: Ralf Baechle commit 9cdf30bd3bac697fc533988f44a117434a858f69 upstream. Returns a non-zero value if the current processor implementation requires an IHB instruction to deal with an instruction hazard as per MIPS R2 architecture specification, zero otherwise. For a discussion, see http://patchwork.linux-mips.org/patch/9539/. Signed-off-by: Ralf Baechle [bwh: Backported to 3.2: trim the CPU type list] Signed-off-by: Ben Hutchings (cherry picked from commit 8feb2a714b3478b2cde5c576fd9f47ef44b60e8d) Signed-off-by: Willy Tarreau --- arch/mips/include/asm/cpu-features.h | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 1f4df64..a3dbb59 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -150,8 +150,32 @@ #define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ cpu_has_mips64r1 | cpu_has_mips64r2) +/* + * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor + * + * Returns non-zero value if the current processor implementation requires + * an IHB instruction to deal with an instruction hazard as per MIPS R2 + * architecture specification, zero otherwise. + */ #ifndef cpu_has_mips_r2_exec_hazard -#define cpu_has_mips_r2_exec_hazard cpu_has_mips_r2 +#define cpu_has_mips_r2_exec_hazard \ +({ \ + int __res; \ + \ + switch (current_cpu_type()) { \ + case CPU_74K: \ + case CPU_CAVIUM_OCTEON: \ + case CPU_CAVIUM_OCTEON_PLUS: \ + case CPU_CAVIUM_OCTEON2: \ + __res = 0; \ + break; \ + \ + default: \ + __res = 1; \ + } \ + \ + __res; \ +}) #endif /* -- 1.7.12.2.21.g234cd45.dirty