From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43950) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zc4cO-0004v8-Ht for qemu-devel@nongnu.org; Wed, 16 Sep 2015 00:46:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zc4cK-0008Ek-H2 for qemu-devel@nongnu.org; Wed, 16 Sep 2015 00:46:52 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:44644) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zc4cK-0008EI-Ad for qemu-devel@nongnu.org; Wed, 16 Sep 2015 00:46:48 -0400 Date: Wed, 16 Sep 2015 06:46:17 +0200 From: Aurelien Jarno Message-ID: <20150916044617.GA12445@aurel32.net> References: <1442234754-15692-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1442234754-15692-1-git-send-email-leon.alrae@imgtec.com> Subject: Re: [Qemu-devel] [PATCH 0/2] target-mips: minor clean up in mtc0 and mfc0 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Leon Alrae Cc: qemu-devel@nongnu.org On 2015-09-14 13:45, Leon Alrae wrote: > This patchset removes the gen_mtc0_store64() which is actually incorrect > as MTC0 instruction in MIPS64 is supposed to move entire content (if > dst CP0 register is 64-bit) without sign extending. It also removes the > gen_mfc0_load64() and replaces the pair of tcg_gen_ld_tl() + > tcg_gen_ext32s_tl() with single tcg_gen_ld32s_tl(). > > Leon Alrae (2): > target-mips: correct MTC0 instruction on MIPS64 > target-mips: remove gen_mfc0_load64() and use tcg_gen_ld32s_tl() The existence of tcg_gen_ld32s_tl is relatively recent, that's why we had it opened coded up to now. Reviewed-by: Aurelien Jarno -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://www.aurel32.net