From mboxrd@z Thu Jan 1 00:00:00 1970 From: will.deacon@arm.com (Will Deacon) Date: Wed, 16 Sep 2015 18:05:05 +0100 Subject: [PATCH] arm64: Add support for PTE contiguous bit. In-Reply-To: <1442340117-3964-1-git-send-email-dwoods@ezchip.com> References: <1442340117-3964-1-git-send-email-dwoods@ezchip.com> Message-ID: <20150916170505.GR28771@arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi David, On Tue, Sep 15, 2015 at 07:01:57PM +0100, David Woods wrote: > The arm64 MMU supports a Contiguous bit which is a hint that the TTE > is one of a set of contiguous entries which can be cached in a single > TLB entry. Supporting this bit adds new intermediate huge page sizes. > > The set of huge page sizes available depends on the base page size. > Without using contiguous pages the huge page sizes are as follows. > > 4KB: 2MB 1GB > 64KB: 512MB 4TB > > With 4KB pages, the contiguous bit groups together sets of 16 pages > and with 64KB pages it groups sets of 32 pages. This enables two new > huge page sizes in each case, so that the full set of available sizes > is as follows. > > 4KB: 64KB 2MB 32MB 1GB > 64KB: 2MB 512MB 16GB 4TB > > If the base page size is set to 64KB then 2MB pages are enabled by > default. It is possible in the future to make 2MB the default huge > page size for both 4KB and 64KB pages. > > Signed-off-by: David Woods > Reviewed-by: Chris Metcalf > --- > arch/arm64/Kconfig | 3 - > arch/arm64/include/asm/hugetlb.h | 4 + > arch/arm64/include/asm/pgtable-hwdef.h | 15 +++ > arch/arm64/include/asm/pgtable.h | 30 +++++- > arch/arm64/mm/hugetlbpage.c | 165 ++++++++++++++++++++++++++++++++- > 5 files changed, 210 insertions(+), 7 deletions(-) I glanced briefly at this, and I think you'll need to do some extra work for the CONFIG_HW_AFDBM=y case, where the CPU can set access/dirty bits in any (i.e. not necessarily all) of the page table entries in a contiguous mapping. In this case, things like huge_pte_dirty might need overriding. Will From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-io0-f180.google.com (mail-io0-f180.google.com [209.85.223.180]) by kanga.kvack.org (Postfix) with ESMTP id D47916B0038 for ; Wed, 16 Sep 2015 13:05:04 -0400 (EDT) Received: by iofb144 with SMTP id b144so237392064iof.1 for ; Wed, 16 Sep 2015 10:05:04 -0700 (PDT) Received: from foss.arm.com (foss.arm.com. [217.140.101.70]) by mx.google.com with ESMTP id c9si3915854igg.40.2015.09.16.10.05.03 for ; Wed, 16 Sep 2015 10:05:03 -0700 (PDT) Date: Wed, 16 Sep 2015 18:05:05 +0100 From: Will Deacon Subject: Re: [PATCH] arm64: Add support for PTE contiguous bit. Message-ID: <20150916170505.GR28771@arm.com> References: <1442340117-3964-1-git-send-email-dwoods@ezchip.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1442340117-3964-1-git-send-email-dwoods@ezchip.com> Sender: owner-linux-mm@kvack.org List-ID: To: David Woods Cc: Chris Metcalf , Catalin Marinas , Steve Capper , Marc Zyngier , Hugh Dickins , Mike Kravetz , Naoya Horiguchi , Andrew Morton , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-mm@kvack.org" Hi David, On Tue, Sep 15, 2015 at 07:01:57PM +0100, David Woods wrote: > The arm64 MMU supports a Contiguous bit which is a hint that the TTE > is one of a set of contiguous entries which can be cached in a single > TLB entry. Supporting this bit adds new intermediate huge page sizes. > > The set of huge page sizes available depends on the base page size. > Without using contiguous pages the huge page sizes are as follows. > > 4KB: 2MB 1GB > 64KB: 512MB 4TB > > With 4KB pages, the contiguous bit groups together sets of 16 pages > and with 64KB pages it groups sets of 32 pages. This enables two new > huge page sizes in each case, so that the full set of available sizes > is as follows. > > 4KB: 64KB 2MB 32MB 1GB > 64KB: 2MB 512MB 16GB 4TB > > If the base page size is set to 64KB then 2MB pages are enabled by > default. It is possible in the future to make 2MB the default huge > page size for both 4KB and 64KB pages. > > Signed-off-by: David Woods > Reviewed-by: Chris Metcalf > --- > arch/arm64/Kconfig | 3 - > arch/arm64/include/asm/hugetlb.h | 4 + > arch/arm64/include/asm/pgtable-hwdef.h | 15 +++ > arch/arm64/include/asm/pgtable.h | 30 +++++- > arch/arm64/mm/hugetlbpage.c | 165 ++++++++++++++++++++++++++++++++- > 5 files changed, 210 insertions(+), 7 deletions(-) I glanced briefly at this, and I think you'll need to do some extra work for the CONFIG_HW_AFDBM=y case, where the CPU can set access/dirty bits in any (i.e. not necessarily all) of the page table entries in a contiguous mapping. In this case, things like huge_pte_dirty might need overriding. Will -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752902AbbIPRFF (ORCPT ); Wed, 16 Sep 2015 13:05:05 -0400 Received: from foss.arm.com ([217.140.101.70]:37615 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751689AbbIPRFD (ORCPT ); Wed, 16 Sep 2015 13:05:03 -0400 Date: Wed, 16 Sep 2015 18:05:05 +0100 From: Will Deacon To: David Woods Cc: Chris Metcalf , Catalin Marinas , Steve Capper , Marc Zyngier , Hugh Dickins , Mike Kravetz , Naoya Horiguchi , Andrew Morton , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-mm@kvack.org" Subject: Re: [PATCH] arm64: Add support for PTE contiguous bit. Message-ID: <20150916170505.GR28771@arm.com> References: <1442340117-3964-1-git-send-email-dwoods@ezchip.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1442340117-3964-1-git-send-email-dwoods@ezchip.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi David, On Tue, Sep 15, 2015 at 07:01:57PM +0100, David Woods wrote: > The arm64 MMU supports a Contiguous bit which is a hint that the TTE > is one of a set of contiguous entries which can be cached in a single > TLB entry. Supporting this bit adds new intermediate huge page sizes. > > The set of huge page sizes available depends on the base page size. > Without using contiguous pages the huge page sizes are as follows. > > 4KB: 2MB 1GB > 64KB: 512MB 4TB > > With 4KB pages, the contiguous bit groups together sets of 16 pages > and with 64KB pages it groups sets of 32 pages. This enables two new > huge page sizes in each case, so that the full set of available sizes > is as follows. > > 4KB: 64KB 2MB 32MB 1GB > 64KB: 2MB 512MB 16GB 4TB > > If the base page size is set to 64KB then 2MB pages are enabled by > default. It is possible in the future to make 2MB the default huge > page size for both 4KB and 64KB pages. > > Signed-off-by: David Woods > Reviewed-by: Chris Metcalf > --- > arch/arm64/Kconfig | 3 - > arch/arm64/include/asm/hugetlb.h | 4 + > arch/arm64/include/asm/pgtable-hwdef.h | 15 +++ > arch/arm64/include/asm/pgtable.h | 30 +++++- > arch/arm64/mm/hugetlbpage.c | 165 ++++++++++++++++++++++++++++++++- > 5 files changed, 210 insertions(+), 7 deletions(-) I glanced briefly at this, and I think you'll need to do some extra work for the CONFIG_HW_AFDBM=y case, where the CPU can set access/dirty bits in any (i.e. not necessarily all) of the page table entries in a contiguous mapping. In this case, things like huge_pte_dirty might need overriding. Will