diff for duplicates of <20150922155450.GL4684@lukather> diff --git a/a/1.txt b/N1/1.txt index 5be1817..7c8c8ee 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -3,7 +3,7 @@ On Tue, Sep 22, 2015 at 11:38:56PM +0800, Vishnu Patekar wrote: > This adds the basic dtsi, the clocks differs from > earlier sun8i SOCs. > -> Signed-off-by: Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> +> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> > --- > arch/arm/boot/dts/sun8i-a83t.dtsi | 243 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 243 insertions(+) @@ -18,7 +18,7 @@ On Tue, Sep 22, 2015 at 11:38:56PM +0800, Vishnu Patekar wrote: > +/* > + * Copyright 2015 Vishnu Patekar > + * -> + * Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> +> + * Vishnu Patekar <vishnupatekar0510@gmail.com> > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual @@ -79,47 +79,47 @@ On Tue, Sep 22, 2015 at 11:38:56PM +0800, Vishnu Patekar wrote: > + #address-cells = <1>; > + #size-cells = <0>; > + -> + cpu@0 { +> + cpu at 0 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <0>; > + }; > + -> + cpu@1 { +> + cpu at 1 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <1>; > + }; > + -> + cpu@2 { +> + cpu at 2 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <2>; > + }; > + -> + cpu@3 { +> + cpu at 3 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <3>; > + }; -> + cpu@4 { +> + cpu at 4 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <4>; > + }; > + -> + cpu@5 { +> + cpu at 5 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <5>; > + }; -> + cpu@6 { +> + cpu at 6 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <6>; > + }; > + -> + cpu@7 { +> + cpu at 7 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <7>; @@ -160,13 +160,13 @@ On Tue, Sep 22, 2015 at 11:38:56PM +0800, Vishnu Patekar wrote: > + }; > + }; > + -> + soc@01c00000 { +> + soc at 01c00000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + -> + pio: pinctrl@01c20800 { +> + pio: pinctrl at 01c20800 { > + compatible = "allwinner,sun8i-a83t-pinctrl"; > + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, @@ -186,14 +186,14 @@ Ditto > + #interrupt-cells = <3>; > + #gpio-cells = <3>; > + -> + uart0_pins_a: uart0@0 { +> + uart0_pins_a: uart0 at 0 { > + allwinner,pins = "PF2", "PF4"; > + allwinner,function = "uart0"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + mmc0_pins_a: mmc0@0 { +> + mmc0_pins_a: mmc0 at 0 { > + allwinner,pins = "PF0", "PF1", "PF2", > + "PF3", "PF4", "PF5"; > + allwinner,function = "mmc0"; @@ -201,7 +201,7 @@ Ditto > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + mmc1_pins_a: mmc1@0 { +> + mmc1_pins_a: mmc1 at 0 { > + allwinner,pins = "PG0", "PG1", "PG2", > + "PG3", "PG4", "PG5"; > + allwinner,function = "mmc1"; @@ -219,21 +219,21 @@ Ditto > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + i2c0_pins_a: i2c0@0 { +> + i2c0_pins_a: i2c0 at 0 { > + allwinner,pins = "PH0", "PH1"; > + allwinner,function = "i2c0"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + i2c1_pins_a: i2c1@0 { +> + i2c1_pins_a: i2c1 at 0 { > + allwinner,pins = "PH2", "PH3"; > + allwinner,function = "i2c1"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; > + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; > + }; > + -> + i2c2_pins_a: i2c2@0 { +> + i2c2_pins_a: i2c2 at 0 { > + allwinner,pins = "PH4", "PH5"; > + allwinner,function = "i2c2"; > + allwinner,drive = <SUN4I_PINCTRL_10_MA>; @@ -244,7 +244,7 @@ Please order those by alphabetical order. > + }; > + -> + uart0: serial@01c28000 { +> + uart0: serial at 01c28000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28000 0x400>; > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; @@ -254,7 +254,7 @@ Please order those by alphabetical order. > + status = "disabled"; > + }; > + -> + gic: interrupt-controller@01c81000 { +> + gic: interrupt-controller at 01c81000 { > + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; > + reg = <0x01c81000 0x1000>, > + <0x01c82000 0x1000>, @@ -278,3 +278,10 @@ Maxime Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com +-------------- next part -------------- +A non-text attachment was scrubbed... +Name: signature.asc +Type: application/pgp-signature +Size: 819 bytes +Desc: Digital signature +URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20150922/c9207b63/attachment-0001.sig> diff --git a/a/content_digest b/N1/content_digest index 550793b..1a2e29b 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,34 +1,17 @@ "ref\01442936337-3104-1-git-send-email-vishnupatekar0510@gmail.com\0" "ref\01442936337-3104-4-git-send-email-vishnupatekar0510@gmail.com\0" - "ref\01442936337-3104-4-git-send-email-vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org\0" - "From\0Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>\0" - "Subject\0Re: [PATCH 3/4] ARM: dts: sun8i: Add Allwinner A83T dtsi\0" + "From\0maxime.ripard@free-electrons.com (Maxime Ripard)\0" + "Subject\0[PATCH 3/4] ARM: dts: sun8i: Add Allwinner A83T dtsi\0" "Date\0Tue, 22 Sep 2015 17:54:50 +0200\0" - "To\0Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0" - "Cc\0robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org" - pawel.moll-5wv7dgnIgG8@public.gmane.org - mark.rutland-5wv7dgnIgG8@public.gmane.org - ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org - galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org - linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org - emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org - linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org - jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org - hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org - wens-jdAy2FN1RRM@public.gmane.org - devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org - linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org - " linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" - "\01:1\0" + "To\0linux-arm-kernel@lists.infradead.org\0" + "\00:1\0" "b\0" "On Tue, Sep 22, 2015 at 11:38:56PM +0800, Vishnu Patekar wrote:\n" "> Allwinner A83T is new octa-core cortex-a7 SOC.\n" "> This adds the basic dtsi, the clocks differs from\n" "> earlier sun8i SOCs.\n" "> \n" - "> Signed-off-by: Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\n" + "> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>\n" "> ---\n" "> arch/arm/boot/dts/sun8i-a83t.dtsi | 243 ++++++++++++++++++++++++++++++++++++++\n" "> 1 file changed, 243 insertions(+)\n" @@ -43,7 +26,7 @@ "> +/*\n" "> + * Copyright 2015 Vishnu Patekar\n" "> + *\n" - "> + * Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\n" + "> + * Vishnu Patekar <vishnupatekar0510@gmail.com>\n" "> + *\n" "> + * This file is dual-licensed: you can use it either under the terms\n" "> + * of the GPL or the X11 license, at your option. Note that this dual\n" @@ -104,47 +87,47 @@ "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\tcpu@0 {\n" + "> +\t\tcpu at 0 {\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu@1 {\n" + "> +\t\tcpu at 1 {\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu@2 {\n" + "> +\t\tcpu at 2 {\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu@3 {\n" + "> +\t\tcpu at 3 {\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <3>;\n" "> +\t\t};\n" - "> +\t\tcpu@4 {\n" + "> +\t\tcpu at 4 {\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <4>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu@5 {\n" + "> +\t\tcpu at 5 {\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <5>;\n" "> +\t\t};\n" - "> +\t\tcpu@6 {\n" + "> +\t\tcpu at 6 {\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <6>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu@7 {\n" + "> +\t\tcpu at 7 {\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <7>;\n" @@ -185,13 +168,13 @@ "> +\t\t};\n" "> +\t};\n" "> +\n" - "> +\tsoc@01c00000 {\n" + "> +\tsoc at 01c00000 {\n" "> +\t\tcompatible = \"simple-bus\";\n" "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <1>;\n" "> +\t\tranges;\n" "> +\n" - "> +\t\tpio: pinctrl@01c20800 {\n" + "> +\t\tpio: pinctrl at 01c20800 {\n" "> +\t\t\tcompatible = \"allwinner,sun8i-a83t-pinctrl\";\n" "> +\t\t\tinterrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,\n" "> +\t\t\t<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -211,14 +194,14 @@ "> +\t\t\t#interrupt-cells = <3>;\n" "> +\t\t\t#gpio-cells = <3>;\n" "> +\n" - "> +\t\t\tuart0_pins_a: uart0@0 {\n" + "> +\t\t\tuart0_pins_a: uart0 at 0 {\n" "> +\t\t\t\tallwinner,pins = \"PF2\", \"PF4\";\n" "> +\t\t\t\tallwinner,function = \"uart0\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tmmc0_pins_a: mmc0@0 {\n" + "> +\t\t\tmmc0_pins_a: mmc0 at 0 {\n" "> +\t\t\t\tallwinner,pins = \"PF0\", \"PF1\", \"PF2\",\n" "> +\t\t\t\t\t\t \"PF3\", \"PF4\", \"PF5\";\n" "> +\t\t\t\tallwinner,function = \"mmc0\";\n" @@ -226,7 +209,7 @@ "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tmmc1_pins_a: mmc1@0 {\n" + "> +\t\t\tmmc1_pins_a: mmc1 at 0 {\n" "> +\t\t\t\tallwinner,pins = \"PG0\", \"PG1\", \"PG2\",\n" "> +\t\t\t\t\t\t \"PG3\", \"PG4\", \"PG5\";\n" "> +\t\t\t\tallwinner,function = \"mmc1\";\n" @@ -244,21 +227,21 @@ "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\ti2c0_pins_a: i2c0@0 {\n" + "> +\t\t\ti2c0_pins_a: i2c0 at 0 {\n" "> +\t\t\t\tallwinner,pins = \"PH0\", \"PH1\";\n" "> +\t\t\t\tallwinner,function = \"i2c0\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\ti2c1_pins_a: i2c1@0 {\n" + "> +\t\t\ti2c1_pins_a: i2c1 at 0 {\n" "> +\t\t\t\tallwinner,pins = \"PH2\", \"PH3\";\n" "> +\t\t\t\tallwinner,function = \"i2c1\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" "> +\t\t\t\tallwinner,pull = <SUN4I_PINCTRL_NO_PULL>;\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\ti2c2_pins_a: i2c2@0 {\n" + "> +\t\t\ti2c2_pins_a: i2c2 at 0 {\n" "> +\t\t\t\tallwinner,pins = \"PH4\", \"PH5\";\n" "> +\t\t\t\tallwinner,function = \"i2c2\";\n" "> +\t\t\t\tallwinner,drive = <SUN4I_PINCTRL_10_MA>;\n" @@ -269,7 +252,7 @@ "\n" "> +\t\t};\n" "> +\n" - "> +\t\tuart0: serial@01c28000 {\n" + "> +\t\tuart0: serial at 01c28000 {\n" "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\treg = <0x01c28000 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -279,7 +262,7 @@ "> +\t\t\tstatus = \"disabled\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tgic: interrupt-controller@01c81000 {\n" + "> +\t\tgic: interrupt-controller at 01c81000 {\n" "> +\t\t\tcompatible = \"arm,cortex-a7-gic\", \"arm,cortex-a15-gic\";\n" "> +\t\t\treg = <0x01c81000 0x1000>,\n" "> +\t\t\t <0x01c82000 0x1000>,\n" @@ -302,6 +285,13 @@ "-- \n" "Maxime Ripard, Free Electrons\n" "Embedded Linux, Kernel and Android engineering\n" - http://free-electrons.com + "http://free-electrons.com\n" + "-------------- next part --------------\n" + "A non-text attachment was scrubbed...\n" + "Name: signature.asc\n" + "Type: application/pgp-signature\n" + "Size: 819 bytes\n" + "Desc: Digital signature\n" + URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20150922/c9207b63/attachment-0001.sig> -cf74f7a4e7886aa5dcd78aaf7212e8213ea84847ca2d68628cbeb2fe0f30a3b8 +990dd16034cc70498f42207097f2dff624021f292777988a0ec720950b34fbdb
diff --git a/a/1.txt b/N2/1.txt index 5be1817..67a015f 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -3,7 +3,7 @@ On Tue, Sep 22, 2015 at 11:38:56PM +0800, Vishnu Patekar wrote: > This adds the basic dtsi, the clocks differs from > earlier sun8i SOCs. > -> Signed-off-by: Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> +> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> > --- > arch/arm/boot/dts/sun8i-a83t.dtsi | 243 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 243 insertions(+) @@ -18,7 +18,7 @@ On Tue, Sep 22, 2015 at 11:38:56PM +0800, Vishnu Patekar wrote: > +/* > + * Copyright 2015 Vishnu Patekar > + * -> + * Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> +> + * Vishnu Patekar <vishnupatekar0510@gmail.com> > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual diff --git a/N2/2.bin b/N2/2.bin new file mode 100644 index 0000000..ded21e1 --- /dev/null +++ b/N2/2.bin @@ -0,0 +1,17 @@ +-----BEGIN PGP SIGNATURE----- +Version: GnuPG v1 + +iQIcBAEBAgAGBQJWAXnKAAoJEBx+YmzsjxAg6KIP/R9xQcNloEhsrUl+uIx3BnHX +yHMYpbgygDAJHlPcvmxcVI7qCQVelOKU/3BnQuyzJOl4SQQRe5nDmiDiQrivp4g+ +dD7p7A4Fk8sTjLwpwHA5mzCjl1WP/M6VtnfYyLDMGDACkXjwcmWqKR0Yrn0c+9UH +Ibbrx0V5NvtmavMUsHHkbrXVrlVjIP7Dxk3B5bAmiX1WRgSVZqkAyd0R0oEFSJd1 +8mrL9EOFMv5MbqUyX3LmZbOLbZGn2Kg3yJVoHn8lsPlzqC7jthmkAN9YE6heX/Dn +0bFUvR8KZfT2ExiKdWrYxYJULQOKPTp0Z7fPXA6gYg78sEczs6I3fAWmBXaH66N1 +ycvmB0j1M0lDk3bKvpZOYQn05iANBLSudZ7xKYfWpFB+nYA8p4ovYmE65NahRoSV +jj/5ZrYFD2td/oECbTGyVxxS8Pn3Qxbauz0b3X8U67NJ/s4FRJ6M4/F+iJVee8Br +o+jdLxiai+8ux5KV4zyqH4a92fh0s8FK3I85zuOLbo9cP3A28AunqTgEKzMgWXl4 +I4MBuORVgWXsHQmXCjzTRMnFCcQrE8nS5WcB4OmiCEOeoqGQEG25Csxj/JEe6W6m +zUThA3gDZzp3r1/ZSbkoIB7JKt+4zqKa2XPHIakMkNW7HOGI8Y9Y8UyxMhLndBcl +HWmdt54DXEKZn8sUH7Lj +=fYij +-----END PGP SIGNATURE----- diff --git a/N2/2.hdr b/N2/2.hdr new file mode 100644 index 0000000..3237378 --- /dev/null +++ b/N2/2.hdr @@ -0,0 +1,2 @@ +Content-Type: application/pgp-signature; name="signature.asc" +Content-Description: Digital signature diff --git a/a/content_digest b/N2/content_digest index 550793b..1a72549 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,26 +1,25 @@ "ref\01442936337-3104-1-git-send-email-vishnupatekar0510@gmail.com\0" "ref\01442936337-3104-4-git-send-email-vishnupatekar0510@gmail.com\0" - "ref\01442936337-3104-4-git-send-email-vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org\0" - "From\0Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>\0" + "From\0Maxime Ripard <maxime.ripard@free-electrons.com>\0" "Subject\0Re: [PATCH 3/4] ARM: dts: sun8i: Add Allwinner A83T dtsi\0" "Date\0Tue, 22 Sep 2015 17:54:50 +0200\0" - "To\0Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0" - "Cc\0robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org" - pawel.moll-5wv7dgnIgG8@public.gmane.org - mark.rutland-5wv7dgnIgG8@public.gmane.org - ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org - galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org - linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org - emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org - linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org - jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org - hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org - wens-jdAy2FN1RRM@public.gmane.org - devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org - linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org - " linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" + "To\0Vishnu Patekar <vishnupatekar0510@gmail.com>\0" + "Cc\0robh+dt@kernel.org" + pawel.moll@arm.com + mark.rutland@arm.com + ijc+devicetree@hellion.org.uk + galak@codeaurora.org + linux@arm.linux.org.uk + emilio@elopez.com.ar + linus.walleij@linaro.org + jenskuske@gmail.com + hdegoede@redhat.com + wens@csie.org + devicetree@vger.kernel.org + linux-arm-kernel@lists.infradead.org + linux-kernel@vger.kernel.org + linux-sunxi@googlegroups.com + " linux-gpio@vger.kernel.org\0" "\01:1\0" "b\0" "On Tue, Sep 22, 2015 at 11:38:56PM +0800, Vishnu Patekar wrote:\n" @@ -28,7 +27,7 @@ "> This adds the basic dtsi, the clocks differs from\n" "> earlier sun8i SOCs.\n" "> \n" - "> Signed-off-by: Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\n" + "> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>\n" "> ---\n" "> arch/arm/boot/dts/sun8i-a83t.dtsi | 243 ++++++++++++++++++++++++++++++++++++++\n" "> 1 file changed, 243 insertions(+)\n" @@ -43,7 +42,7 @@ "> +/*\n" "> + * Copyright 2015 Vishnu Patekar\n" "> + *\n" - "> + * Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\n" + "> + * Vishnu Patekar <vishnupatekar0510@gmail.com>\n" "> + *\n" "> + * This file is dual-licensed: you can use it either under the terms\n" "> + * of the GPL or the X11 license, at your option. Note that this dual\n" @@ -303,5 +302,26 @@ "Maxime Ripard, Free Electrons\n" "Embedded Linux, Kernel and Android engineering\n" http://free-electrons.com + "\01:2\0" + "fn\0signature.asc\0" + "d\0Digital signature\0" + "b\0" + "-----BEGIN PGP SIGNATURE-----\n" + "Version: GnuPG v1\n" + "\n" + "iQIcBAEBAgAGBQJWAXnKAAoJEBx+YmzsjxAg6KIP/R9xQcNloEhsrUl+uIx3BnHX\n" + "yHMYpbgygDAJHlPcvmxcVI7qCQVelOKU/3BnQuyzJOl4SQQRe5nDmiDiQrivp4g+\n" + "dD7p7A4Fk8sTjLwpwHA5mzCjl1WP/M6VtnfYyLDMGDACkXjwcmWqKR0Yrn0c+9UH\n" + "Ibbrx0V5NvtmavMUsHHkbrXVrlVjIP7Dxk3B5bAmiX1WRgSVZqkAyd0R0oEFSJd1\n" + "8mrL9EOFMv5MbqUyX3LmZbOLbZGn2Kg3yJVoHn8lsPlzqC7jthmkAN9YE6heX/Dn\n" + "0bFUvR8KZfT2ExiKdWrYxYJULQOKPTp0Z7fPXA6gYg78sEczs6I3fAWmBXaH66N1\n" + "ycvmB0j1M0lDk3bKvpZOYQn05iANBLSudZ7xKYfWpFB+nYA8p4ovYmE65NahRoSV\n" + "jj/5ZrYFD2td/oECbTGyVxxS8Pn3Qxbauz0b3X8U67NJ/s4FRJ6M4/F+iJVee8Br\n" + "o+jdLxiai+8ux5KV4zyqH4a92fh0s8FK3I85zuOLbo9cP3A28AunqTgEKzMgWXl4\n" + "I4MBuORVgWXsHQmXCjzTRMnFCcQrE8nS5WcB4OmiCEOeoqGQEG25Csxj/JEe6W6m\n" + "zUThA3gDZzp3r1/ZSbkoIB7JKt+4zqKa2XPHIakMkNW7HOGI8Y9Y8UyxMhLndBcl\n" + "HWmdt54DXEKZn8sUH7Lj\n" + "=fYij\n" + "-----END PGP SIGNATURE-----\n" -cf74f7a4e7886aa5dcd78aaf7212e8213ea84847ca2d68628cbeb2fe0f30a3b8 +b5200db11c1452519f1c0e7727e1f73558cb69f4d397054af67e67669aff01c8
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