From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: Re: [PATCH 3/4] ARM: dts: sun8i: Add Allwinner A83T dtsi Date: Tue, 22 Sep 2015 17:54:50 +0200 Message-ID: <20150922155450.GL4684@lukather> References: <1442936337-3104-1-git-send-email-vishnupatekar0510@gmail.com> <1442936337-3104-4-git-send-email-vishnupatekar0510@gmail.com> Reply-To: maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="tuMntWBhi9NC2Hav" Return-path: Content-Disposition: inline In-Reply-To: <1442936337-3104-4-git-send-email-vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Vishnu Patekar Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, pawel.moll-5wv7dgnIgG8@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org, galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org, emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org, linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, wens-jdAy2FN1RRM@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: linux-gpio@vger.kernel.org --tuMntWBhi9NC2Hav Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline On Tue, Sep 22, 2015 at 11:38:56PM +0800, Vishnu Patekar wrote: > Allwinner A83T is new octa-core cortex-a7 SOC. > This adds the basic dtsi, the clocks differs from > earlier sun8i SOCs. > > Signed-off-by: Vishnu Patekar > --- > arch/arm/boot/dts/sun8i-a83t.dtsi | 243 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 243 insertions(+) > create mode 100644 arch/arm/boot/dts/sun8i-a83t.dtsi > > diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi > new file mode 100644 > index 0000000..f6ddd9c > --- /dev/null > +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi > @@ -0,0 +1,243 @@ > +/* > + * Copyright 2015 Vishnu Patekar > + * > + * Vishnu Patekar > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual > + * licensing only applies to this file, and not this project as a > + * whole. > + * > + * a) This file is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of the > + * License, or (at your option) any later version. > + * > + * This file is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * Or, alternatively, > + * > + * b) Permission is hereby granted, free of charge, to any person > + * obtaining a copy of this software and associated documentation > + * files (the "Software"), to deal in the Software without > + * restriction, including without limitation the rights to use, > + * copy, modify, merge, publish, distribute, sublicense, and/or > + * sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following > + * conditions: > + * > + * The above copyright notice and this permission notice shall be > + * included in all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + > + */ > + > +#include "skeleton.dtsi" > + > +#include > + > +#include > + > +/ { > + interrupt-parent = <&gic>; > + > + chosen { > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu@0 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <0>; > + }; > + > + cpu@1 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <1>; > + }; > + > + cpu@2 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <2>; > + }; > + > + cpu@3 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <3>; > + }; > + cpu@4 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <4>; > + }; > + > + cpu@5 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <5>; > + }; > + cpu@6 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <6>; > + }; > + > + cpu@7 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <7>; > + }; > + }; > + > + memory { > + reg = <0x40000000 0x80000000>; > + }; > + > + timer { > + compatible = "arm,armv7-timer"; > + interrupts = , > + , > + , > + ; > + clock-frequency = <24000000>; > + arm,cpu-registers-not-fw-configured; > + }; > + > + clocks { > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + osc24M: osc24M_clk { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <24000000>; > + clock-output-names = "osc24M"; > + }; > + > + osc32k: osc32k_clk { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <32768>; > + clock-output-names = "osc32k"; > + }; > + }; > + > + soc@01c00000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + pio: pinctrl@01c20800 { > + compatible = "allwinner,sun8i-a83t-pinctrl"; > + interrupts = , > + , > + ; > + /* compatible gets set in SoC specific dtsi file */ Which DTSI? > + reg = <0x01c20800 0x400>; > + /* interrupts get set in SoC specific dtsi file */ Ditto > + clocks = <&osc24M>; > + gpio-controller; > + interrupt-controller; > + #interrupt-cells = <3>; > + #gpio-cells = <3>; > + > + uart0_pins_a: uart0@0 { > + allwinner,pins = "PF2", "PF4"; > + allwinner,function = "uart0"; > + allwinner,drive = ; > + allwinner,pull = ; > + }; > + > + mmc0_pins_a: mmc0@0 { > + allwinner,pins = "PF0", "PF1", "PF2", > + "PF3", "PF4", "PF5"; > + allwinner,function = "mmc0"; > + allwinner,drive = ; > + allwinner,pull = ; > + }; > + > + mmc1_pins_a: mmc1@0 { > + allwinner,pins = "PG0", "PG1", "PG2", > + "PG3", "PG4", "PG5"; > + allwinner,function = "mmc1"; > + allwinner,drive = ; > + allwinner,pull = ; > + }; > + > + mmc2_8bit_pins: mmc2_8bit { > + allwinner,pins = "PC5", "PC6", "PC8", > + "PC9", "PC10", "PC11", > + "PC12", "PC13", "PC14", > + "PC15"; > + allwinner,function = "mmc2"; > + allwinner,drive = ; > + allwinner,pull = ; > + }; > + > + i2c0_pins_a: i2c0@0 { > + allwinner,pins = "PH0", "PH1"; > + allwinner,function = "i2c0"; > + allwinner,drive = ; > + allwinner,pull = ; > + }; > + > + i2c1_pins_a: i2c1@0 { > + allwinner,pins = "PH2", "PH3"; > + allwinner,function = "i2c1"; > + allwinner,drive = ; > + allwinner,pull = ; > + }; > + > + i2c2_pins_a: i2c2@0 { > + allwinner,pins = "PH4", "PH5"; > + allwinner,function = "i2c2"; > + allwinner,drive = ; > + allwinner,pull = ; > + }; Please order those by alphabetical order. > + }; > + > + uart0: serial@01c28000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28000 0x400>; > + interrupts = ; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&osc24M>; > + status = "disabled"; > + }; > + > + gic: interrupt-controller@01c81000 { > + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; > + reg = <0x01c81000 0x1000>, > + <0x01c82000 0x1000>, > + <0x01c84000 0x2000>, > + <0x01c86000 0x2000>; > + interrupt-controller; > + #interrupt-cells = <3>; > + interrupts = ; > + }; > + > + }; > +}; > -- > 1.9.1 > Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --tuMntWBhi9NC2Hav-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: maxime.ripard@free-electrons.com (Maxime Ripard) Date: Tue, 22 Sep 2015 17:54:50 +0200 Subject: [PATCH 3/4] ARM: dts: sun8i: Add Allwinner A83T dtsi In-Reply-To: <1442936337-3104-4-git-send-email-vishnupatekar0510@gmail.com> References: <1442936337-3104-1-git-send-email-vishnupatekar0510@gmail.com> <1442936337-3104-4-git-send-email-vishnupatekar0510@gmail.com> Message-ID: <20150922155450.GL4684@lukather> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Tue, Sep 22, 2015 at 11:38:56PM +0800, Vishnu Patekar wrote: > Allwinner A83T is new octa-core cortex-a7 SOC. > This adds the basic dtsi, the clocks differs from > earlier sun8i SOCs. > > Signed-off-by: Vishnu Patekar > --- > arch/arm/boot/dts/sun8i-a83t.dtsi | 243 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 243 insertions(+) > create mode 100644 arch/arm/boot/dts/sun8i-a83t.dtsi > > diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi > new file mode 100644 > index 0000000..f6ddd9c > --- /dev/null > +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi > @@ -0,0 +1,243 @@ > +/* > + * Copyright 2015 Vishnu Patekar > + * > + * Vishnu Patekar > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual > + * licensing only applies to this file, and not this project as a > + * whole. > + * > + * a) This file is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of the > + * License, or (at your option) any later version. > + * > + * This file is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * Or, alternatively, > + * > + * b) Permission is hereby granted, free of charge, to any person > + * obtaining a copy of this software and associated documentation > + * files (the "Software"), to deal in the Software without > + * restriction, including without limitation the rights to use, > + * copy, modify, merge, publish, distribute, sublicense, and/or > + * sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following > + * conditions: > + * > + * The above copyright notice and this permission notice shall be > + * included in all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + > + */ > + > +#include "skeleton.dtsi" > + > +#include > + > +#include > + > +/ { > + interrupt-parent = <&gic>; > + > + chosen { > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu at 0 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <0>; > + }; > + > + cpu at 1 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <1>; > + }; > + > + cpu at 2 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <2>; > + }; > + > + cpu at 3 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <3>; > + }; > + cpu at 4 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <4>; > + }; > + > + cpu at 5 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <5>; > + }; > + cpu at 6 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <6>; > + }; > + > + cpu at 7 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <7>; > + }; > + }; > + > + memory { > + reg = <0x40000000 0x80000000>; > + }; > + > + timer { > + compatible = "arm,armv7-timer"; > + interrupts = , > + , > + , > + ; > + clock-frequency = <24000000>; > + arm,cpu-registers-not-fw-configured; > + }; > + > + clocks { > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + osc24M: osc24M_clk { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <24000000>; > + clock-output-names = "osc24M"; > + }; > + > + osc32k: osc32k_clk { > + #clock-cells = <0>; > + compatible = "fixed-clock"; > + clock-frequency = <32768>; > + clock-output-names = "osc32k"; > + }; > + }; > + > + soc at 01c00000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + pio: pinctrl at 01c20800 { > + compatible = "allwinner,sun8i-a83t-pinctrl"; > + interrupts = , > + , > + ; > + /* compatible gets set in SoC specific dtsi file */ Which DTSI? > + reg = <0x01c20800 0x400>; > + /* interrupts get set in SoC specific dtsi file */ Ditto > + clocks = <&osc24M>; > + gpio-controller; > + interrupt-controller; > + #interrupt-cells = <3>; > + #gpio-cells = <3>; > + > + uart0_pins_a: uart0 at 0 { > + allwinner,pins = "PF2", "PF4"; > + allwinner,function = "uart0"; > + allwinner,drive = ; > + allwinner,pull = ; > + }; > + > + mmc0_pins_a: mmc0 at 0 { > + allwinner,pins = "PF0", "PF1", "PF2", > + "PF3", "PF4", "PF5"; > + allwinner,function = "mmc0"; > + allwinner,drive = ; > + allwinner,pull = ; > + }; > + > + mmc1_pins_a: mmc1 at 0 { > + allwinner,pins = "PG0", "PG1", "PG2", > + "PG3", "PG4", "PG5"; > + allwinner,function = "mmc1"; > + allwinner,drive = ; > + allwinner,pull = ; > + }; > + > + mmc2_8bit_pins: mmc2_8bit { > + allwinner,pins = "PC5", "PC6", "PC8", > + "PC9", "PC10", "PC11", > + "PC12", "PC13", "PC14", > + "PC15"; > + allwinner,function = "mmc2"; > + allwinner,drive = ; > + allwinner,pull = ; > + }; > + > + i2c0_pins_a: i2c0 at 0 { > + allwinner,pins = "PH0", "PH1"; > + allwinner,function = "i2c0"; > + allwinner,drive = ; > + allwinner,pull = ; > + }; > + > + i2c1_pins_a: i2c1 at 0 { > + allwinner,pins = "PH2", "PH3"; > + allwinner,function = "i2c1"; > + allwinner,drive = ; > + allwinner,pull = ; > + }; > + > + i2c2_pins_a: i2c2 at 0 { > + allwinner,pins = "PH4", "PH5"; > + allwinner,function = "i2c2"; > + allwinner,drive = ; > + allwinner,pull = ; > + }; Please order those by alphabetical order. > + }; > + > + uart0: serial at 01c28000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28000 0x400>; > + interrupts = ; > + reg-shift = <2>; > + reg-io-width = <4>; > + clocks = <&osc24M>; > + status = "disabled"; > + }; > + > + gic: interrupt-controller at 01c81000 { > + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; > + reg = <0x01c81000 0x1000>, > + <0x01c82000 0x1000>, > + <0x01c84000 0x2000>, > + <0x01c86000 0x2000>; > + interrupt-controller; > + #interrupt-cells = <3>; > + interrupts = ; > + }; > + > + }; > +}; > -- > 1.9.1 > Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933818AbbIVP5J (ORCPT ); Tue, 22 Sep 2015 11:57:09 -0400 Received: from down.free-electrons.com ([37.187.137.238]:52417 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S933801AbbIVP5D (ORCPT ); Tue, 22 Sep 2015 11:57:03 -0400 Date: Tue, 22 Sep 2015 17:54:50 +0200 From: Maxime Ripard To: Vishnu Patekar Cc: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, emilio@elopez.com.ar, linus.walleij@linaro.org, jenskuske@gmail.com, hdegoede@redhat.com, wens@csie.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, linux-gpio@vger.kernel.org Subject: Re: [PATCH 3/4] ARM: dts: sun8i: Add Allwinner A83T dtsi Message-ID: <20150922155450.GL4684@lukather> References: <1442936337-3104-1-git-send-email-vishnupatekar0510@gmail.com> <1442936337-3104-4-git-send-email-vishnupatekar0510@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="tuMntWBhi9NC2Hav" Content-Disposition: inline In-Reply-To: <1442936337-3104-4-git-send-email-vishnupatekar0510@gmail.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --tuMntWBhi9NC2Hav Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Sep 22, 2015 at 11:38:56PM +0800, Vishnu Patekar wrote: > Allwinner A83T is new octa-core cortex-a7 SOC. > This adds the basic dtsi, the clocks differs from > earlier sun8i SOCs. >=20 > Signed-off-by: Vishnu Patekar > --- > arch/arm/boot/dts/sun8i-a83t.dtsi | 243 ++++++++++++++++++++++++++++++++= ++++++ > 1 file changed, 243 insertions(+) > create mode 100644 arch/arm/boot/dts/sun8i-a83t.dtsi >=20 > diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-= a83t.dtsi > new file mode 100644 > index 0000000..f6ddd9c > --- /dev/null > +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi > @@ -0,0 +1,243 @@ > +/* > + * Copyright 2015 Vishnu Patekar > + * > + * Vishnu Patekar > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual > + * licensing only applies to this file, and not this project as a > + * whole. > + * > + * a) This file is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of the > + * License, or (at your option) any later version. > + * > + * This file is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * Or, alternatively, > + * > + * b) Permission is hereby granted, free of charge, to any person > + * obtaining a copy of this software and associated documentation > + * files (the "Software"), to deal in the Software without > + * restriction, including without limitation the rights to use, > + * copy, modify, merge, publish, distribute, sublicense, and/or > + * sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following > + * conditions: > + * > + * The above copyright notice and this permission notice shall be > + * included in all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + > + */ > + > +#include "skeleton.dtsi" > + > +#include > + > +#include > + > +/ { > + interrupt-parent =3D <&gic>; > + > + chosen { > + #address-cells =3D <1>; > + #size-cells =3D <1>; > + ranges; > + }; > + > + cpus { > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + > + cpu@0 { > + compatible =3D "arm,cortex-a7"; > + device_type =3D "cpu"; > + reg =3D <0>; > + }; > + > + cpu@1 { > + compatible =3D "arm,cortex-a7"; > + device_type =3D "cpu"; > + reg =3D <1>; > + }; > + > + cpu@2 { > + compatible =3D "arm,cortex-a7"; > + device_type =3D "cpu"; > + reg =3D <2>; > + }; > + > + cpu@3 { > + compatible =3D "arm,cortex-a7"; > + device_type =3D "cpu"; > + reg =3D <3>; > + }; > + cpu@4 { > + compatible =3D "arm,cortex-a7"; > + device_type =3D "cpu"; > + reg =3D <4>; > + }; > + > + cpu@5 { > + compatible =3D "arm,cortex-a7"; > + device_type =3D "cpu"; > + reg =3D <5>; > + }; > + cpu@6 { > + compatible =3D "arm,cortex-a7"; > + device_type =3D "cpu"; > + reg =3D <6>; > + }; > + > + cpu@7 { > + compatible =3D "arm,cortex-a7"; > + device_type =3D "cpu"; > + reg =3D <7>; > + }; > + }; > + > + memory { > + reg =3D <0x40000000 0x80000000>; > + }; > + > + timer { > + compatible =3D "arm,armv7-timer"; > + interrupts =3D , > + , > + , > + ; > + clock-frequency =3D <24000000>; > + arm,cpu-registers-not-fw-configured; > + }; > + > + clocks { > + #address-cells =3D <1>; > + #size-cells =3D <1>; > + ranges; > + > + osc24M: osc24M_clk { > + #clock-cells =3D <0>; > + compatible =3D "fixed-clock"; > + clock-frequency =3D <24000000>; > + clock-output-names =3D "osc24M"; > + }; > + > + osc32k: osc32k_clk { > + #clock-cells =3D <0>; > + compatible =3D "fixed-clock"; > + clock-frequency =3D <32768>; > + clock-output-names =3D "osc32k"; > + }; > + }; > + > + soc@01c00000 { > + compatible =3D "simple-bus"; > + #address-cells =3D <1>; > + #size-cells =3D <1>; > + ranges; > + > + pio: pinctrl@01c20800 { > + compatible =3D "allwinner,sun8i-a83t-pinctrl"; > + interrupts =3D , > + , > + ; > + /* compatible gets set in SoC specific dtsi file */ Which DTSI? > + reg =3D <0x01c20800 0x400>; > + /* interrupts get set in SoC specific dtsi file */ Ditto > + clocks =3D <&osc24M>; > + gpio-controller; > + interrupt-controller; > + #interrupt-cells =3D <3>; > + #gpio-cells =3D <3>; > + > + uart0_pins_a: uart0@0 { > + allwinner,pins =3D "PF2", "PF4"; > + allwinner,function =3D "uart0"; > + allwinner,drive =3D ; > + allwinner,pull =3D ; > + }; > + > + mmc0_pins_a: mmc0@0 { > + allwinner,pins =3D "PF0", "PF1", "PF2", > + "PF3", "PF4", "PF5"; > + allwinner,function =3D "mmc0"; > + allwinner,drive =3D ; > + allwinner,pull =3D ; > + }; > + > + mmc1_pins_a: mmc1@0 { > + allwinner,pins =3D "PG0", "PG1", "PG2", > + "PG3", "PG4", "PG5"; > + allwinner,function =3D "mmc1"; > + allwinner,drive =3D ; > + allwinner,pull =3D ; > + }; > + > + mmc2_8bit_pins: mmc2_8bit { > + allwinner,pins =3D "PC5", "PC6", "PC8", > + "PC9", "PC10", "PC11", > + "PC12", "PC13", "PC14", > + "PC15"; > + allwinner,function =3D "mmc2"; > + allwinner,drive =3D ; > + allwinner,pull =3D ; > + }; > + > + i2c0_pins_a: i2c0@0 { > + allwinner,pins =3D "PH0", "PH1"; > + allwinner,function =3D "i2c0"; > + allwinner,drive =3D ; > + allwinner,pull =3D ; > + }; > + > + i2c1_pins_a: i2c1@0 { > + allwinner,pins =3D "PH2", "PH3"; > + allwinner,function =3D "i2c1"; > + allwinner,drive =3D ; > + allwinner,pull =3D ; > + }; > + > + i2c2_pins_a: i2c2@0 { > + allwinner,pins =3D "PH4", "PH5"; > + allwinner,function =3D "i2c2"; > + allwinner,drive =3D ; > + allwinner,pull =3D ; > + }; Please order those by alphabetical order. > + }; > + > + uart0: serial@01c28000 { > + compatible =3D "snps,dw-apb-uart"; > + reg =3D <0x01c28000 0x400>; > + interrupts =3D ; > + reg-shift =3D <2>; > + reg-io-width =3D <4>; > + clocks =3D <&osc24M>; > + status =3D "disabled"; > + }; > + > + gic: interrupt-controller@01c81000 { > + compatible =3D "arm,cortex-a7-gic", "arm,cortex-a15-gic"; > + reg =3D <0x01c81000 0x1000>, > + <0x01c82000 0x1000>, > + <0x01c84000 0x2000>, > + <0x01c86000 0x2000>; > + interrupt-controller; > + #interrupt-cells =3D <3>; > + interrupts =3D ; > + }; > + > + }; > +}; > --=20 > 1.9.1 >=20 Thanks! Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --tuMntWBhi9NC2Hav Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJWAXnKAAoJEBx+YmzsjxAg6KIP/R9xQcNloEhsrUl+uIx3BnHX yHMYpbgygDAJHlPcvmxcVI7qCQVelOKU/3BnQuyzJOl4SQQRe5nDmiDiQrivp4g+ dD7p7A4Fk8sTjLwpwHA5mzCjl1WP/M6VtnfYyLDMGDACkXjwcmWqKR0Yrn0c+9UH Ibbrx0V5NvtmavMUsHHkbrXVrlVjIP7Dxk3B5bAmiX1WRgSVZqkAyd0R0oEFSJd1 8mrL9EOFMv5MbqUyX3LmZbOLbZGn2Kg3yJVoHn8lsPlzqC7jthmkAN9YE6heX/Dn 0bFUvR8KZfT2ExiKdWrYxYJULQOKPTp0Z7fPXA6gYg78sEczs6I3fAWmBXaH66N1 ycvmB0j1M0lDk3bKvpZOYQn05iANBLSudZ7xKYfWpFB+nYA8p4ovYmE65NahRoSV jj/5ZrYFD2td/oECbTGyVxxS8Pn3Qxbauz0b3X8U67NJ/s4FRJ6M4/F+iJVee8Br o+jdLxiai+8ux5KV4zyqH4a92fh0s8FK3I85zuOLbo9cP3A28AunqTgEKzMgWXl4 I4MBuORVgWXsHQmXCjzTRMnFCcQrE8nS5WcB4OmiCEOeoqGQEG25Csxj/JEe6W6m zUThA3gDZzp3r1/ZSbkoIB7JKt+4zqKa2XPHIakMkNW7HOGI8Y9Y8UyxMhLndBcl HWmdt54DXEKZn8sUH7Lj =fYij -----END PGP SIGNATURE----- --tuMntWBhi9NC2Hav--