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From: Lee Jones <lee.jones@linaro.org>
To: Barry Song <21cnbao@gmail.com>
Cc: Mark Brown <broonie@kernel.org>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	sameo <sameo@linux.intel.com>,
	LKML <linux-kernel@vger.kernel.org>,
	DL-SHA-WorkGroupLinux <workgroup.linux@csr.com>,
	Guo Zeng <Guo.Zeng@csr.com>, Barry Song <Baohua.Song@csr.com>
Subject: Re: [PATCH v2 3/3] mfd: add CSR SiRFSoC on-chip power management module driver
Date: Mon, 5 Oct 2015 09:21:09 +0100	[thread overview]
Message-ID: <20151005082109.GA3243@x1> (raw)
In-Reply-To: <CAGsJ_4xXFhq=OeAJC7=ZZvTuF=EkRiaLuUSuqZO9jNPQm3Oa8w@mail.gmail.com>

On Sun, 04 Oct 2015, Barry Song wrote:
> 2015-09-29 16:55 GMT+08:00 Lee Jones <lee.jones@linaro.org>:
> > On Tue, 29 Sep 2015, Barry Song wrote:
> >
> >> 2015-09-29 15:16 GMT+08:00 Lee Jones <lee.jones@linaro.org>:
> >> > On Tue, 29 Sep 2015, Barry Song wrote:
> >> >> >> >> +static int sirfsoc_pwrc_probe(struct platform_device *pdev)
> >> >> >> >> +{
> >> >> >> >> +     struct device_node *np = pdev->dev.of_node;
> >> >> >> >> +     const struct of_device_id *match;
> >> >> >> >> +     struct sirfsoc_pwrc_info *pwrcinfo;
> >> >> >> >> +     struct regmap_irq_chip *regmap_irq_chip;
> >> >> >> >> +     struct sirfsoc_pwrc_register *pwrc_reg;
> >> >> >> >> +     struct regmap *map;
> >> >> >> >> +     int ret;
> >> >> >> >> +     u32 base;
> >> >> >> >> +
> >> >> >> >> +     if (of_property_read_u32(np, "reg", &base))
> >> >> >> >> +             panic("unable to find base address of pwrc node in dtb\n");
> >> >> >> >
> >> >> >> > It looks like this driver should depend on OF.
> >> >> >> >
> >> >> >> > Why are you obtaining the base address manually? Use:
> >> >> >> >
> >> >> >> >   res = platform_get_resource();
> >> >> >> >   devm_ioremap_resource(res);
> >> >> >> >
> >> >> >> > ... instead.
> >> >> >>
> >> >> >> this was explained as they are not in memory space, they are behind a
> >> >> >> bus bridge.
> >> >> >
> >> >> > Use 'ranges' in the DT, then you can pull out the proper address
> >> >> > without hand rolling your own method.
> >> >>
> >> >> it seems it is not a "ranges" thing,  things behind rtciobrg is much
> >> >> like things behind USB or sdio. we need to use a rtciobrg protocol to
> >> >> do read/write.
> >> >> they can not be randomly accessed by load/store, and can't be XIP.
> >> >> they don't have any ranges in CPU memory space.
> >> >
> >> > So what's the point of 'base' then?  I assumed this was the base of
> >> > the IP registers which where memory mapped?
> >>
> >> just think we have a i2c device, and this i2c device has multi-functions.
> >> each function has a base of its register offset.
> >> actually, the base is the offset of 1st register.
> >
> > Does it every change, from device to device?

What I mean is ...

> yes. Lee. e.g:
> 
>                         rtc-iobg@18840000 {
>                                 reg = <0x18840000 0x1000>;
> 
>                                 sysrtc@2000 {

Is sysrtc always @2000, or might it be @4000 on some devices?

>                                         compatible = "sirf,prima2-sysrtc";
>                                         reg = <0x2000 0x100>;
>                                         interrupts = <0 52 0>;
>                                 };
>                                 pwrc@3000 {

Same for pwrc?

>                                         compatible = "sirf,atlas7-pwrc";
>                                         reg = <0x3000 0x100>;
>                                         interrupts = <0 32 0>;
>                                 };
> 
>                         }
> 
> 
> -barry

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

  reply	other threads:[~2015-10-05  8:21 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-09-17  5:23 [PATCH v2 1/3] regmap: irq: add support for chips who have separate unmask registers Barry Song
2015-09-17  5:23 ` [PATCH v2 2/3] regmap: irq: add ack_invert flag for chips using cleared bits as ack Barry Song
2015-09-17  5:23 ` [PATCH v2 3/3] mfd: add CSR SiRFSoC on-chip power management module driver Barry Song
2015-09-20  4:15   ` Lee Jones
2015-09-21  2:38     ` Barry Song
2015-09-24 18:13       ` Lee Jones
2015-09-29  6:18         ` Barry Song
2015-09-29  7:16           ` Lee Jones
2015-09-29  8:30             ` Barry Song
2015-09-29  8:55               ` Lee Jones
2015-10-04 10:02                 ` Barry Song
2015-10-05  8:21                   ` Lee Jones [this message]
2015-10-05 10:08                     ` Barry Song
2015-10-05 10:22                       ` Lee Jones
2015-09-17 10:53 ` [PATCH v2 1/3] regmap: irq: add support for chips who have separate unmask registers Mark Brown
2015-09-17 14:20   ` Barry Song

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