From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH] drm/i915: Set mode->crtc_clock during hardware state readout Date: Wed, 7 Oct 2015 16:26:03 +0200 Message-ID: <20151007142603.GM3383@phenom.ffwll.local> References: <1444148791-4913-1-git-send-email-matthew.d.roper@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mail-wi0-f174.google.com (mail-wi0-f174.google.com [209.85.212.174]) by gabe.freedesktop.org (Postfix) with ESMTPS id 36E116EBAB for ; Wed, 7 Oct 2015 07:23:10 -0700 (PDT) Received: by wicfx3 with SMTP id fx3so215175991wic.1 for ; Wed, 07 Oct 2015 07:23:09 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1444148791-4913-1-git-send-email-matthew.d.roper@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Matt Roper Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org T24gVHVlLCBPY3QgMDYsIDIwMTUgYXQgMDk6MjY6MzFBTSAtMDcwMCwgTWF0dCBSb3BlciB3cm90 ZToKPiBpbnRlbF9tb2RlX2Zyb21fcGlwZV9jb25maWcoKSBmaWxscyBpbiBhIG1vZGUgc3RydWN0 dXJlIGZyb20gdGhlIENSVEMKPiBzdGF0ZSB0aGF0IHdhcyByZWFkIG91dCBvZiB0aGUgaGFyZHdh cmUsIGJ1dCBkb2VzIG5vdCBzZXQgdGhlCj4gLmNydGNfY2xvY2sgZmllbGQgKGl0IG9ubHkgc2V0 cyB0aGUgLmNsb2NrKS4gIFRoaXMgY2F1c2VzIHRoZSBzdWJzZXF1ZW50Cj4gY2FsbCB0byBkcm1f Y2FsY190aW1lc3RhbXBpbmdfY29uc3RhbnRzKCkgdG8gY29tcGxhaW4gd2l0aCBtZXNzYWdlcyBs aWtlCj4gIipFUlJPUiogY3J0YyAyMTogQ2FuJ3QgY2FsY3VsYXRlIGNvbnN0YW50cywgZG90Y2xv Y2sgPSAwISIgIEVuc3VyaW5nCj4gLmNydGNfY2xvY2sgaXMgc2V0IGFzIHdlbGwgZWxpbWluYXRl cyB0aGlzIGVycm9yLgo+IAo+IFNpZ25lZC1vZmYtYnk6IE1hdHQgUm9wZXIgPG1hdHRoZXcuZC5y b3BlckBpbnRlbC5jb20+CgpJcyB0aGlzIGZpeGluZyB0aGUgYnVnIFBhdWxvIHJlcG9ydGVkPyBX aHkgaXMgaGUgbm90IG9uIENDPyBXaHkgaXMgdGhlcmUKbm8gY2l0YXRpb24gb2YgdGhlIGNvbW1p dCB3aGljaCBicm9rZSB0aGlzPwotRGFuaWVsCgo+IC0tLQo+ICBkcml2ZXJzL2dwdS9kcm0vaTkx NS9pbnRlbF9kaXNwbGF5LmMgfCAxICsKPiAgMSBmaWxlIGNoYW5nZWQsIDEgaW5zZXJ0aW9uKCsp Cj4gCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2Rpc3BsYXkuYyBi L2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2Rpc3BsYXkuYwo+IGluZGV4IGJiZWI2ZDMuLjRl NDgxZTMgMTAwNjQ0Cj4gLS0tIGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfZGlzcGxheS5j Cj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfZGlzcGxheS5jCj4gQEAgLTc3NTIs NiArNzc1Miw3IEBAIHZvaWQgaW50ZWxfbW9kZV9mcm9tX3BpcGVfY29uZmlnKHN0cnVjdCBkcm1f ZGlzcGxheV9tb2RlICptb2RlLAo+ICAJbW9kZS0+dHlwZSA9IERSTV9NT0RFX1RZUEVfRFJJVkVS Owo+ICAKPiAgCW1vZGUtPmNsb2NrID0gcGlwZV9jb25maWctPmJhc2UuYWRqdXN0ZWRfbW9kZS5j cnRjX2Nsb2NrOwo+ICsJbW9kZS0+Y3J0Y19jbG9jayA9IHBpcGVfY29uZmlnLT5iYXNlLmFkanVz dGVkX21vZGUuY3J0Y19jbG9jazsKPiAgCW1vZGUtPmZsYWdzIHw9IHBpcGVfY29uZmlnLT5iYXNl LmFkanVzdGVkX21vZGUuZmxhZ3M7Cj4gIAo+ICAJbW9kZS0+aHN5bmMgPSBkcm1fbW9kZV9oc3lu Yyhtb2RlKTsKPiAtLSAKPiAyLjEuNAo+IAo+IF9fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fCj4gSW50ZWwtZ2Z4IG1haWxpbmcgbGlzdAo+IEludGVsLWdmeEBs aXN0cy5mcmVlZGVza3RvcC5vcmcKPiBodHRwOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxt YW4vbGlzdGluZm8vaW50ZWwtZ2Z4CgotLSAKRGFuaWVsIFZldHRlcgpTb2Z0d2FyZSBFbmdpbmVl ciwgSW50ZWwgQ29ycG9yYXRpb24KaHR0cDovL2Jsb2cuZmZ3bGwuY2gKX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4IG1haWxpbmcgbGlzdApJ bnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHA6Ly9saXN0cy5mcmVlZGVza3RvcC5v cmcvbWFpbG1hbi9saXN0aW5mby9pbnRlbC1nZngK