Re: [Xenomai] Interrupt latency close to 1ms on powerpc Xenomai 2.6.4

[Gilles Chanteperdrix <gilles.chanteperdrix@xenomai.org>]

On Thu, Oct 08, 2015 at 05:41:41PM +0200, Philippe Gerum wrote:
> On 10/08/2015 05:17 PM, Lennart Sorensen wrote:
> > On Thu, Oct 08, 2015 at 04:54:07PM +0200, Philippe Gerum wrote:
> >> I could not find one that would not look weird. That logic is deeply
> >> buried in kernel space, and introducing a dynamic dependency on whether
> >> e.g. the PCI layer has to be traversed for carrying out such ops would
> >> be rather confusing for the end user, especially when porting the
> >> application code over different SoCs.
> > 
> > Yep, that sounds ugly.
> > 
> >> Likely, yes. The relevant handlers dealing with the interrupt controller
> >> of the QUICC Engine do not tread on problematic code, so this should be
> >> ok for this platform.
> > 
> > Then I have the icky situation that we want the same kernel source to
> > run on arm.  I wonder if the am572x would care.  I guess I could #ifdef
> > it for powerpc only and leave the new way on arm.
> > 
> 
> No guarantee, I only had a quick look at this, but AFAICS:
> 
> - the irqchip from the PCA953X gpio extender module does not seem to
> have any requirement for running over a regular kernel context
> 
> - the main GIC IRQ controller is fine, since the fast ack code we use
> over the head domain is shared with the IRQ enabling/disabling support.
> 
> So this should be ok (famous last words).

The GIC has some board/SOC specific callbacks, so, you have to check
these callbacks too, to be sure that the code does not use some
linux services.

-- 
					    Gilles.
https://click-hack.org