diff for duplicates of <20151020101536.20687.93727@quantum> diff --git a/a/1.txt b/N1/1.txt index 0179b81..50d5154 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -4,23 +4,19 @@ Quoting Geert Uytterhoeven (2015-10-16 05:49:16) > On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse > Generator) and MSSR (Module Standby and Software Reset) blocks are > intimately connected, and share the same register block. -> = - +> > Hence it makes sense to describe these two blocks using a > single device node in DT, instead of using a hierarchical structure with > multiple nodes, using a mix of generic and SoC-specific bindings. -> = - +> > These new DT bindings are intended to replace the existing DT bindings > for CPG core clocks ("renesas,*-cpg-clocks", "renesas,cpg-div6-clock") > and module clocks ("renesas,*-mstp-clocks"), at least for new SoCs. -> = - +> > This will make it easier to add module reset support later, which is > currently not implemented, and difficult to achieve using the existing > bindings due to the intertwined register layout. -> = - +> > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Thanks for re-working the binding per our discussion at ELC-E. Please @@ -32,26 +28,20 @@ Mike > --- > v4: > - No changes, -> = - +> > v3: > - Integrate CPG and MSSR, -> = - +> > v2: > - Switch from MSTP to MSSR. > --- -> .../devicetree/bindings/clock/renesas,cpg-mssr.txt | 71 ++++++++++++++++= -++++++ +> .../devicetree/bindings/clock/renesas,cpg-mssr.txt | 71 ++++++++++++++++++++++ > include/dt-bindings/clock/renesas-cpg-mssr.h | 15 +++++ > 2 files changed, 86 insertions(+) -> create mode 100644 Documentation/devicetree/bindings/clock/renesas,cpg-m= -ssr.txt +> create mode 100644 Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt > create mode 100644 include/dt-bindings/clock/renesas-cpg-mssr.h -> = - -> diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt= - b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt +> +> diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt > new file mode 100644 > index 0000000000000000..a56836aa2131a8db > --- /dev/null @@ -59,32 +49,26 @@ ssr.txt > @@ -0,0 +1,71 @@ > +* Renesas Clock Pulse Generator / Module Standby and Software Reset > + -> +On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Gener= -ator) -> +and MSSR (Module Standby and Software Reset) blocks are intimately conne= -cted, +> +On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator) +> +and MSSR (Module Standby and Software Reset) blocks are intimately connected, > +and share the same register block. > + > +They provide the following functionalities: > + - The CPG block generates various core clocks, > + - The MSSR block provides two functions: -> + 1. Module Standby, providing a Clock Domain to control the clock s= -upply +> + 1. Module Standby, providing a Clock Domain to control the clock supply > + to individual SoC devices, -> + 2. Reset Control, to perform a software reset of individual SoC de= -vices. +> + 2. Reset Control, to perform a software reset of individual SoC devices. > + > +Required Properties: > + - compatible: Must be one of: > + - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC > + - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC > + -> + - reg: Base address and length of the memory resource used by the CPG/= -MSSR +> + - reg: Base address and length of the memory resource used by the CPG/MSSR > + block > + -> + - clocks: References to external parent clocks, one entry for each ent= -ry in +> + - clocks: References to external parent clocks, one entry for each entry in > + clock-names > + - clock-names: List of external parent clock names. Valid names are: > + - "extal" (r8a7791, r8a7795) @@ -92,20 +76,16 @@ ry in > + - "usb_extal" (r8a7791) > + > + - #clock-cells: Must be 2 -> + - For CPG core clocks, the two clock specifier cells must be "CPG_= -CORE" +> + - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" > + and a core clock reference, as defined in > + <dt-bindings/clock/*-cpg-mssr.h>. -> + - For module clocks, the two clock specifier cells must be "CPG_MO= -D" and +> + - For module clocks, the two clock specifier cells must be "CPG_MOD" and > + a module number, as defined in the datasheet. > + > + - #power-domain-cells: Must be 0 > + - SoC devices that are part of the CPG/MSSR Clock Domain and can be -> + power-managed through Module Standby should refer to the CPG devi= -ce -> + node in their "power-domains" property, as documented by the gene= -ric PM +> + power-managed through Module Standby should refer to the CPG device +> + node in their "power-domains" property, as documented by the generic PM > + Domain bindings in > + Documentation/devicetree/bindings/power/power_domain.txt. > + @@ -116,30 +96,29 @@ ric PM > + - CPG device node: > + > + cpg: clock-controller@e6150000 { -> + compatible =3D "renesas,r8a7795-cpg-mssr"; -> + reg =3D <0 0xe6150000 0 0x1000>; -> + clocks =3D <&extal_clk>, <&extalr_clk>; -> + clock-names =3D "extal", "extalr"; -> + #clock-cells =3D <2>; -> + #power-domain-cells =3D <0>; +> + compatible = "renesas,r8a7795-cpg-mssr"; +> + reg = <0 0xe6150000 0 0x1000>; +> + clocks = <&extal_clk>, <&extalr_clk>; +> + clock-names = "extal", "extalr"; +> + #clock-cells = <2>; +> + #power-domain-cells = <0>; > + }; > + > + > + - CPG/MSSR Clock Domain member device node: > + > + scif2: serial@e6e88000 { -> + compatible =3D "renesas,scif-r8a7795", "renesas,scif"; -> + reg =3D <0 0xe6e88000 0 64>; -> + interrupts =3D <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; -> + clocks =3D <&cpg CPG_MOD 310>; -> + clock-names =3D "sci_ick"; -> + dmas =3D <&dmac1 0x13>, <&dmac1 0x12>; -> + dma-names =3D "tx", "rx"; -> + power-domains =3D <&cpg>; -> + status =3D "disabled"; +> + compatible = "renesas,scif-r8a7795", "renesas,scif"; +> + reg = <0 0xe6e88000 0 64>; +> + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; +> + clocks = <&cpg CPG_MOD 310>; +> + clock-names = "sci_ick"; +> + dmas = <&dmac1 0x13>, <&dmac1 0x12>; +> + dma-names = "tx", "rx"; +> + power-domains = <&cpg>; +> + status = "disabled"; > + }; -> diff --git a/include/dt-bindings/clock/renesas-cpg-mssr.h b/include/dt-bi= -ndings/clock/renesas-cpg-mssr.h +> diff --git a/include/dt-bindings/clock/renesas-cpg-mssr.h b/include/dt-bindings/clock/renesas-cpg-mssr.h > new file mode 100644 > index 0000000000000000..569a3cc33ffb5bc7 > --- /dev/null @@ -160,7 +139,6 @@ ndings/clock/renesas-cpg-mssr.h > +#define CPG_MOD 1 /* Module Clock */ > + > +#endif /* __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ */ -> -- = - +> -- > 1.9.1 ->=20 +> diff --git a/a/content_digest b/N1/content_digest index 689f51a..a9f14fa 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -2,7 +2,7 @@ "ref\01444999760-15750-2-git-send-email-geert+renesas@glider.be\0" "From\0Michael Turquette <mturquette@baylibre.com>\0" "Subject\0Re: [PATCH v4 1/5] [RFC] clk: shmobile: Add new Renesas CPG/MSSR DT bindings\0" - "Date\0Tue, 20 Oct 2015 03:15:36 -0700\0" + "Date\0Tue, 20 Oct 2015 10:15:36 +0000\0" "To\0Geert Uytterhoeven <geert+renesas@glider.be>" Stephen Boyd <sboyd@codeaurora.org> Laurent Pinchart <laurent.pinchart@ideasonboard.com> @@ -15,8 +15,7 @@ " Kumar Gala <galak@codeaurora.org>\0" "Cc\0linux-clk@vger.kernel.org" devicetree@vger.kernel.org - linux-sh@vger.kernel.org - " Geert Uytterhoeven <geert+renesas@glider.be>\0" + " linux-sh@vger.kernel.org\0" "\00:1\0" "b\0" "Hi Geert,\n" @@ -25,23 +24,19 @@ "> On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse\n" "> Generator) and MSSR (Module Standby and Software Reset) blocks are\n" "> intimately connected, and share the same register block.\n" - "> =\n" - "\n" + "> \n" "> Hence it makes sense to describe these two blocks using a\n" "> single device node in DT, instead of using a hierarchical structure with\n" "> multiple nodes, using a mix of generic and SoC-specific bindings.\n" - "> =\n" - "\n" + "> \n" "> These new DT bindings are intended to replace the existing DT bindings\n" "> for CPG core clocks (\"renesas,*-cpg-clocks\", \"renesas,cpg-div6-clock\")\n" "> and module clocks (\"renesas,*-mstp-clocks\"), at least for new SoCs.\n" - "> =\n" - "\n" + "> \n" "> This will make it easier to add module reset support later, which is\n" "> currently not implemented, and difficult to achieve using the existing\n" "> bindings due to the intertwined register layout.\n" - "> =\n" - "\n" + "> \n" "> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>\n" "\n" "Thanks for re-working the binding per our discussion at ELC-E. Please\n" @@ -53,26 +48,20 @@ "> ---\n" "> v4:\n" "> - No changes,\n" - "> =\n" - "\n" + "> \n" "> v3:\n" "> - Integrate CPG and MSSR,\n" - "> =\n" - "\n" + "> \n" "> v2:\n" "> - Switch from MSTP to MSSR.\n" "> ---\n" - "> .../devicetree/bindings/clock/renesas,cpg-mssr.txt | 71 ++++++++++++++++=\n" - "++++++\n" + "> .../devicetree/bindings/clock/renesas,cpg-mssr.txt | 71 ++++++++++++++++++++++\n" "> include/dt-bindings/clock/renesas-cpg-mssr.h | 15 +++++\n" "> 2 files changed, 86 insertions(+)\n" - "> create mode 100644 Documentation/devicetree/bindings/clock/renesas,cpg-m=\n" - "ssr.txt\n" + "> create mode 100644 Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt\n" "> create mode 100644 include/dt-bindings/clock/renesas-cpg-mssr.h\n" - "> =\n" - "\n" - "> diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt=\n" - " b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt\n" + "> \n" + "> diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt\n" "> new file mode 100644\n" "> index 0000000000000000..a56836aa2131a8db\n" "> --- /dev/null\n" @@ -80,32 +69,26 @@ "> @@ -0,0 +1,71 @@\n" "> +* Renesas Clock Pulse Generator / Module Standby and Software Reset\n" "> +\n" - "> +On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Gener=\n" - "ator)\n" - "> +and MSSR (Module Standby and Software Reset) blocks are intimately conne=\n" - "cted,\n" + "> +On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)\n" + "> +and MSSR (Module Standby and Software Reset) blocks are intimately connected,\n" "> +and share the same register block.\n" "> +\n" "> +They provide the following functionalities:\n" "> + - The CPG block generates various core clocks,\n" "> + - The MSSR block provides two functions:\n" - "> + 1. Module Standby, providing a Clock Domain to control the clock s=\n" - "upply\n" + "> + 1. Module Standby, providing a Clock Domain to control the clock supply\n" "> + to individual SoC devices,\n" - "> + 2. Reset Control, to perform a software reset of individual SoC de=\n" - "vices.\n" + "> + 2. Reset Control, to perform a software reset of individual SoC devices.\n" "> +\n" "> +Required Properties:\n" "> + - compatible: Must be one of:\n" "> + - \"renesas,r8a7791-cpg-mssr\" for the r8a7791 SoC\n" "> + - \"renesas,r8a7795-cpg-mssr\" for the r8a7795 SoC\n" "> +\n" - "> + - reg: Base address and length of the memory resource used by the CPG/=\n" - "MSSR\n" + "> + - reg: Base address and length of the memory resource used by the CPG/MSSR\n" "> + block\n" "> +\n" - "> + - clocks: References to external parent clocks, one entry for each ent=\n" - "ry in\n" + "> + - clocks: References to external parent clocks, one entry for each entry in\n" "> + clock-names\n" "> + - clock-names: List of external parent clock names. Valid names are:\n" "> + - \"extal\" (r8a7791, r8a7795)\n" @@ -113,20 +96,16 @@ "> + - \"usb_extal\" (r8a7791)\n" "> +\n" "> + - #clock-cells: Must be 2\n" - "> + - For CPG core clocks, the two clock specifier cells must be \"CPG_=\n" - "CORE\"\n" + "> + - For CPG core clocks, the two clock specifier cells must be \"CPG_CORE\"\n" "> + and a core clock reference, as defined in\n" "> + <dt-bindings/clock/*-cpg-mssr.h>.\n" - "> + - For module clocks, the two clock specifier cells must be \"CPG_MO=\n" - "D\" and\n" + "> + - For module clocks, the two clock specifier cells must be \"CPG_MOD\" and\n" "> + a module number, as defined in the datasheet.\n" "> +\n" "> + - #power-domain-cells: Must be 0\n" "> + - SoC devices that are part of the CPG/MSSR Clock Domain and can be\n" - "> + power-managed through Module Standby should refer to the CPG devi=\n" - "ce\n" - "> + node in their \"power-domains\" property, as documented by the gene=\n" - "ric PM\n" + "> + power-managed through Module Standby should refer to the CPG device\n" + "> + node in their \"power-domains\" property, as documented by the generic PM\n" "> + Domain bindings in\n" "> + Documentation/devicetree/bindings/power/power_domain.txt.\n" "> +\n" @@ -137,30 +116,29 @@ "> + - CPG device node:\n" "> +\n" "> + cpg: clock-controller@e6150000 {\n" - "> + compatible =3D \"renesas,r8a7795-cpg-mssr\";\n" - "> + reg =3D <0 0xe6150000 0 0x1000>;\n" - "> + clocks =3D <&extal_clk>, <&extalr_clk>;\n" - "> + clock-names =3D \"extal\", \"extalr\";\n" - "> + #clock-cells =3D <2>;\n" - "> + #power-domain-cells =3D <0>;\n" + "> + compatible = \"renesas,r8a7795-cpg-mssr\";\n" + "> + reg = <0 0xe6150000 0 0x1000>;\n" + "> + clocks = <&extal_clk>, <&extalr_clk>;\n" + "> + clock-names = \"extal\", \"extalr\";\n" + "> + #clock-cells = <2>;\n" + "> + #power-domain-cells = <0>;\n" "> + };\n" "> +\n" "> +\n" "> + - CPG/MSSR Clock Domain member device node:\n" "> +\n" "> + scif2: serial@e6e88000 {\n" - "> + compatible =3D \"renesas,scif-r8a7795\", \"renesas,scif\";\n" - "> + reg =3D <0 0xe6e88000 0 64>;\n" - "> + interrupts =3D <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;\n" - "> + clocks =3D <&cpg CPG_MOD 310>;\n" - "> + clock-names =3D \"sci_ick\";\n" - "> + dmas =3D <&dmac1 0x13>, <&dmac1 0x12>;\n" - "> + dma-names =3D \"tx\", \"rx\";\n" - "> + power-domains =3D <&cpg>;\n" - "> + status =3D \"disabled\";\n" + "> + compatible = \"renesas,scif-r8a7795\", \"renesas,scif\";\n" + "> + reg = <0 0xe6e88000 0 64>;\n" + "> + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;\n" + "> + clocks = <&cpg CPG_MOD 310>;\n" + "> + clock-names = \"sci_ick\";\n" + "> + dmas = <&dmac1 0x13>, <&dmac1 0x12>;\n" + "> + dma-names = \"tx\", \"rx\";\n" + "> + power-domains = <&cpg>;\n" + "> + status = \"disabled\";\n" "> + };\n" - "> diff --git a/include/dt-bindings/clock/renesas-cpg-mssr.h b/include/dt-bi=\n" - "ndings/clock/renesas-cpg-mssr.h\n" + "> diff --git a/include/dt-bindings/clock/renesas-cpg-mssr.h b/include/dt-bindings/clock/renesas-cpg-mssr.h\n" "> new file mode 100644\n" "> index 0000000000000000..569a3cc33ffb5bc7\n" "> --- /dev/null\n" @@ -181,9 +159,8 @@ "> +#define CPG_MOD 1 /* Module Clock */\n" "> +\n" "> +#endif /* __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ */\n" - "> -- =\n" - "\n" + "> -- \n" "> 1.9.1\n" - >=20 + > -f3237bc40a7c10fbd22568b6270aaf36d26538f75c89fd3f48ed833724ff664d +e7515f09dbf45b542765f4df6a917dc9c0a8cbfbd630e860704e7afff44eea93
diff --git a/a/1.txt b/N2/1.txt index 0179b81..50d5154 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -4,23 +4,19 @@ Quoting Geert Uytterhoeven (2015-10-16 05:49:16) > On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse > Generator) and MSSR (Module Standby and Software Reset) blocks are > intimately connected, and share the same register block. -> = - +> > Hence it makes sense to describe these two blocks using a > single device node in DT, instead of using a hierarchical structure with > multiple nodes, using a mix of generic and SoC-specific bindings. -> = - +> > These new DT bindings are intended to replace the existing DT bindings > for CPG core clocks ("renesas,*-cpg-clocks", "renesas,cpg-div6-clock") > and module clocks ("renesas,*-mstp-clocks"), at least for new SoCs. -> = - +> > This will make it easier to add module reset support later, which is > currently not implemented, and difficult to achieve using the existing > bindings due to the intertwined register layout. -> = - +> > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Thanks for re-working the binding per our discussion at ELC-E. Please @@ -32,26 +28,20 @@ Mike > --- > v4: > - No changes, -> = - +> > v3: > - Integrate CPG and MSSR, -> = - +> > v2: > - Switch from MSTP to MSSR. > --- -> .../devicetree/bindings/clock/renesas,cpg-mssr.txt | 71 ++++++++++++++++= -++++++ +> .../devicetree/bindings/clock/renesas,cpg-mssr.txt | 71 ++++++++++++++++++++++ > include/dt-bindings/clock/renesas-cpg-mssr.h | 15 +++++ > 2 files changed, 86 insertions(+) -> create mode 100644 Documentation/devicetree/bindings/clock/renesas,cpg-m= -ssr.txt +> create mode 100644 Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt > create mode 100644 include/dt-bindings/clock/renesas-cpg-mssr.h -> = - -> diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt= - b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt +> +> diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt > new file mode 100644 > index 0000000000000000..a56836aa2131a8db > --- /dev/null @@ -59,32 +49,26 @@ ssr.txt > @@ -0,0 +1,71 @@ > +* Renesas Clock Pulse Generator / Module Standby and Software Reset > + -> +On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Gener= -ator) -> +and MSSR (Module Standby and Software Reset) blocks are intimately conne= -cted, +> +On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator) +> +and MSSR (Module Standby and Software Reset) blocks are intimately connected, > +and share the same register block. > + > +They provide the following functionalities: > + - The CPG block generates various core clocks, > + - The MSSR block provides two functions: -> + 1. Module Standby, providing a Clock Domain to control the clock s= -upply +> + 1. Module Standby, providing a Clock Domain to control the clock supply > + to individual SoC devices, -> + 2. Reset Control, to perform a software reset of individual SoC de= -vices. +> + 2. Reset Control, to perform a software reset of individual SoC devices. > + > +Required Properties: > + - compatible: Must be one of: > + - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC > + - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC > + -> + - reg: Base address and length of the memory resource used by the CPG/= -MSSR +> + - reg: Base address and length of the memory resource used by the CPG/MSSR > + block > + -> + - clocks: References to external parent clocks, one entry for each ent= -ry in +> + - clocks: References to external parent clocks, one entry for each entry in > + clock-names > + - clock-names: List of external parent clock names. Valid names are: > + - "extal" (r8a7791, r8a7795) @@ -92,20 +76,16 @@ ry in > + - "usb_extal" (r8a7791) > + > + - #clock-cells: Must be 2 -> + - For CPG core clocks, the two clock specifier cells must be "CPG_= -CORE" +> + - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" > + and a core clock reference, as defined in > + <dt-bindings/clock/*-cpg-mssr.h>. -> + - For module clocks, the two clock specifier cells must be "CPG_MO= -D" and +> + - For module clocks, the two clock specifier cells must be "CPG_MOD" and > + a module number, as defined in the datasheet. > + > + - #power-domain-cells: Must be 0 > + - SoC devices that are part of the CPG/MSSR Clock Domain and can be -> + power-managed through Module Standby should refer to the CPG devi= -ce -> + node in their "power-domains" property, as documented by the gene= -ric PM +> + power-managed through Module Standby should refer to the CPG device +> + node in their "power-domains" property, as documented by the generic PM > + Domain bindings in > + Documentation/devicetree/bindings/power/power_domain.txt. > + @@ -116,30 +96,29 @@ ric PM > + - CPG device node: > + > + cpg: clock-controller@e6150000 { -> + compatible =3D "renesas,r8a7795-cpg-mssr"; -> + reg =3D <0 0xe6150000 0 0x1000>; -> + clocks =3D <&extal_clk>, <&extalr_clk>; -> + clock-names =3D "extal", "extalr"; -> + #clock-cells =3D <2>; -> + #power-domain-cells =3D <0>; +> + compatible = "renesas,r8a7795-cpg-mssr"; +> + reg = <0 0xe6150000 0 0x1000>; +> + clocks = <&extal_clk>, <&extalr_clk>; +> + clock-names = "extal", "extalr"; +> + #clock-cells = <2>; +> + #power-domain-cells = <0>; > + }; > + > + > + - CPG/MSSR Clock Domain member device node: > + > + scif2: serial@e6e88000 { -> + compatible =3D "renesas,scif-r8a7795", "renesas,scif"; -> + reg =3D <0 0xe6e88000 0 64>; -> + interrupts =3D <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; -> + clocks =3D <&cpg CPG_MOD 310>; -> + clock-names =3D "sci_ick"; -> + dmas =3D <&dmac1 0x13>, <&dmac1 0x12>; -> + dma-names =3D "tx", "rx"; -> + power-domains =3D <&cpg>; -> + status =3D "disabled"; +> + compatible = "renesas,scif-r8a7795", "renesas,scif"; +> + reg = <0 0xe6e88000 0 64>; +> + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; +> + clocks = <&cpg CPG_MOD 310>; +> + clock-names = "sci_ick"; +> + dmas = <&dmac1 0x13>, <&dmac1 0x12>; +> + dma-names = "tx", "rx"; +> + power-domains = <&cpg>; +> + status = "disabled"; > + }; -> diff --git a/include/dt-bindings/clock/renesas-cpg-mssr.h b/include/dt-bi= -ndings/clock/renesas-cpg-mssr.h +> diff --git a/include/dt-bindings/clock/renesas-cpg-mssr.h b/include/dt-bindings/clock/renesas-cpg-mssr.h > new file mode 100644 > index 0000000000000000..569a3cc33ffb5bc7 > --- /dev/null @@ -160,7 +139,6 @@ ndings/clock/renesas-cpg-mssr.h > +#define CPG_MOD 1 /* Module Clock */ > + > +#endif /* __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ */ -> -- = - +> -- > 1.9.1 ->=20 +> diff --git a/a/content_digest b/N2/content_digest index 689f51a..4bd41f2 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -3,8 +3,7 @@ "From\0Michael Turquette <mturquette@baylibre.com>\0" "Subject\0Re: [PATCH v4 1/5] [RFC] clk: shmobile: Add new Renesas CPG/MSSR DT bindings\0" "Date\0Tue, 20 Oct 2015 03:15:36 -0700\0" - "To\0Geert Uytterhoeven <geert+renesas@glider.be>" - Stephen Boyd <sboyd@codeaurora.org> + "To\0Stephen Boyd <sboyd@codeaurora.org>" Laurent Pinchart <laurent.pinchart@ideasonboard.com> Magnus Damm <damm+renesas@opensource.se> Simon Horman <horms+renesas@verge.net.au> @@ -25,23 +24,19 @@ "> On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse\n" "> Generator) and MSSR (Module Standby and Software Reset) blocks are\n" "> intimately connected, and share the same register block.\n" - "> =\n" - "\n" + "> \n" "> Hence it makes sense to describe these two blocks using a\n" "> single device node in DT, instead of using a hierarchical structure with\n" "> multiple nodes, using a mix of generic and SoC-specific bindings.\n" - "> =\n" - "\n" + "> \n" "> These new DT bindings are intended to replace the existing DT bindings\n" "> for CPG core clocks (\"renesas,*-cpg-clocks\", \"renesas,cpg-div6-clock\")\n" "> and module clocks (\"renesas,*-mstp-clocks\"), at least for new SoCs.\n" - "> =\n" - "\n" + "> \n" "> This will make it easier to add module reset support later, which is\n" "> currently not implemented, and difficult to achieve using the existing\n" "> bindings due to the intertwined register layout.\n" - "> =\n" - "\n" + "> \n" "> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>\n" "\n" "Thanks for re-working the binding per our discussion at ELC-E. Please\n" @@ -53,26 +48,20 @@ "> ---\n" "> v4:\n" "> - No changes,\n" - "> =\n" - "\n" + "> \n" "> v3:\n" "> - Integrate CPG and MSSR,\n" - "> =\n" - "\n" + "> \n" "> v2:\n" "> - Switch from MSTP to MSSR.\n" "> ---\n" - "> .../devicetree/bindings/clock/renesas,cpg-mssr.txt | 71 ++++++++++++++++=\n" - "++++++\n" + "> .../devicetree/bindings/clock/renesas,cpg-mssr.txt | 71 ++++++++++++++++++++++\n" "> include/dt-bindings/clock/renesas-cpg-mssr.h | 15 +++++\n" "> 2 files changed, 86 insertions(+)\n" - "> create mode 100644 Documentation/devicetree/bindings/clock/renesas,cpg-m=\n" - "ssr.txt\n" + "> create mode 100644 Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt\n" "> create mode 100644 include/dt-bindings/clock/renesas-cpg-mssr.h\n" - "> =\n" - "\n" - "> diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt=\n" - " b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt\n" + "> \n" + "> diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt\n" "> new file mode 100644\n" "> index 0000000000000000..a56836aa2131a8db\n" "> --- /dev/null\n" @@ -80,32 +69,26 @@ "> @@ -0,0 +1,71 @@\n" "> +* Renesas Clock Pulse Generator / Module Standby and Software Reset\n" "> +\n" - "> +On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Gener=\n" - "ator)\n" - "> +and MSSR (Module Standby and Software Reset) blocks are intimately conne=\n" - "cted,\n" + "> +On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)\n" + "> +and MSSR (Module Standby and Software Reset) blocks are intimately connected,\n" "> +and share the same register block.\n" "> +\n" "> +They provide the following functionalities:\n" "> + - The CPG block generates various core clocks,\n" "> + - The MSSR block provides two functions:\n" - "> + 1. Module Standby, providing a Clock Domain to control the clock s=\n" - "upply\n" + "> + 1. Module Standby, providing a Clock Domain to control the clock supply\n" "> + to individual SoC devices,\n" - "> + 2. Reset Control, to perform a software reset of individual SoC de=\n" - "vices.\n" + "> + 2. Reset Control, to perform a software reset of individual SoC devices.\n" "> +\n" "> +Required Properties:\n" "> + - compatible: Must be one of:\n" "> + - \"renesas,r8a7791-cpg-mssr\" for the r8a7791 SoC\n" "> + - \"renesas,r8a7795-cpg-mssr\" for the r8a7795 SoC\n" "> +\n" - "> + - reg: Base address and length of the memory resource used by the CPG/=\n" - "MSSR\n" + "> + - reg: Base address and length of the memory resource used by the CPG/MSSR\n" "> + block\n" "> +\n" - "> + - clocks: References to external parent clocks, one entry for each ent=\n" - "ry in\n" + "> + - clocks: References to external parent clocks, one entry for each entry in\n" "> + clock-names\n" "> + - clock-names: List of external parent clock names. Valid names are:\n" "> + - \"extal\" (r8a7791, r8a7795)\n" @@ -113,20 +96,16 @@ "> + - \"usb_extal\" (r8a7791)\n" "> +\n" "> + - #clock-cells: Must be 2\n" - "> + - For CPG core clocks, the two clock specifier cells must be \"CPG_=\n" - "CORE\"\n" + "> + - For CPG core clocks, the two clock specifier cells must be \"CPG_CORE\"\n" "> + and a core clock reference, as defined in\n" "> + <dt-bindings/clock/*-cpg-mssr.h>.\n" - "> + - For module clocks, the two clock specifier cells must be \"CPG_MO=\n" - "D\" and\n" + "> + - For module clocks, the two clock specifier cells must be \"CPG_MOD\" and\n" "> + a module number, as defined in the datasheet.\n" "> +\n" "> + - #power-domain-cells: Must be 0\n" "> + - SoC devices that are part of the CPG/MSSR Clock Domain and can be\n" - "> + power-managed through Module Standby should refer to the CPG devi=\n" - "ce\n" - "> + node in their \"power-domains\" property, as documented by the gene=\n" - "ric PM\n" + "> + power-managed through Module Standby should refer to the CPG device\n" + "> + node in their \"power-domains\" property, as documented by the generic PM\n" "> + Domain bindings in\n" "> + Documentation/devicetree/bindings/power/power_domain.txt.\n" "> +\n" @@ -137,30 +116,29 @@ "> + - CPG device node:\n" "> +\n" "> + cpg: clock-controller@e6150000 {\n" - "> + compatible =3D \"renesas,r8a7795-cpg-mssr\";\n" - "> + reg =3D <0 0xe6150000 0 0x1000>;\n" - "> + clocks =3D <&extal_clk>, <&extalr_clk>;\n" - "> + clock-names =3D \"extal\", \"extalr\";\n" - "> + #clock-cells =3D <2>;\n" - "> + #power-domain-cells =3D <0>;\n" + "> + compatible = \"renesas,r8a7795-cpg-mssr\";\n" + "> + reg = <0 0xe6150000 0 0x1000>;\n" + "> + clocks = <&extal_clk>, <&extalr_clk>;\n" + "> + clock-names = \"extal\", \"extalr\";\n" + "> + #clock-cells = <2>;\n" + "> + #power-domain-cells = <0>;\n" "> + };\n" "> +\n" "> +\n" "> + - CPG/MSSR Clock Domain member device node:\n" "> +\n" "> + scif2: serial@e6e88000 {\n" - "> + compatible =3D \"renesas,scif-r8a7795\", \"renesas,scif\";\n" - "> + reg =3D <0 0xe6e88000 0 64>;\n" - "> + interrupts =3D <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;\n" - "> + clocks =3D <&cpg CPG_MOD 310>;\n" - "> + clock-names =3D \"sci_ick\";\n" - "> + dmas =3D <&dmac1 0x13>, <&dmac1 0x12>;\n" - "> + dma-names =3D \"tx\", \"rx\";\n" - "> + power-domains =3D <&cpg>;\n" - "> + status =3D \"disabled\";\n" + "> + compatible = \"renesas,scif-r8a7795\", \"renesas,scif\";\n" + "> + reg = <0 0xe6e88000 0 64>;\n" + "> + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;\n" + "> + clocks = <&cpg CPG_MOD 310>;\n" + "> + clock-names = \"sci_ick\";\n" + "> + dmas = <&dmac1 0x13>, <&dmac1 0x12>;\n" + "> + dma-names = \"tx\", \"rx\";\n" + "> + power-domains = <&cpg>;\n" + "> + status = \"disabled\";\n" "> + };\n" - "> diff --git a/include/dt-bindings/clock/renesas-cpg-mssr.h b/include/dt-bi=\n" - "ndings/clock/renesas-cpg-mssr.h\n" + "> diff --git a/include/dt-bindings/clock/renesas-cpg-mssr.h b/include/dt-bindings/clock/renesas-cpg-mssr.h\n" "> new file mode 100644\n" "> index 0000000000000000..569a3cc33ffb5bc7\n" "> --- /dev/null\n" @@ -181,9 +159,8 @@ "> +#define CPG_MOD 1 /* Module Clock */\n" "> +\n" "> +#endif /* __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ */\n" - "> -- =\n" - "\n" + "> -- \n" "> 1.9.1\n" - >=20 + > -f3237bc40a7c10fbd22568b6270aaf36d26538f75c89fd3f48ed833724ff664d +ff1c7e50f8bd42ddd0645622f9a7e44c5ea459634ada6f5ff3c40eaff05e9b0e
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