diff for duplicates of <20151021094154.20687.68970@quantum> diff --git a/a/1.txt b/N1/1.txt index 09bc18c..01a0dbf 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,13 +1,11 @@ Quoting Ray Jui (2015-10-19 15:27:19) > From: Simran Rai <ssimran@broadcom.com> -> = - +> > This patch affects the clocks that use fractional ndivider in their > PLL output frequency calculation. Instead of 2^20 divide factor, the > clock's ndiv integer shift was used. Fixed the bug by replacing ndiv > integer shift with 2^20 factor. -> = - +> > Signed-off-by: Simran Rai <ssimran@broadcom.com> > Signed-off-by: Ray Jui <rjui@broadcom.com> > Reviewed-by: Scott Branden <sbranden@broadcom.com> @@ -21,58 +19,48 @@ Mike > --- > drivers/clk/bcm/clk-iproc-pll.c | 13 +++++-------- > 1 file changed, 5 insertions(+), 8 deletions(-) -> = - -> diff --git a/drivers/clk/bcm/clk-iproc-pll.c b/drivers/clk/bcm/clk-iproc-= -pll.c +> +> diff --git a/drivers/clk/bcm/clk-iproc-pll.c b/drivers/clk/bcm/clk-iproc-pll.c > index 2dda4e8..d679ab8 100644 > --- a/drivers/clk/bcm/clk-iproc-pll.c > +++ b/drivers/clk/bcm/clk-iproc-pll.c -> @@ -345,8 +345,8 @@ static unsigned long iproc_pll_recalc_rate(struct clk= -_hw *hw, -> struct iproc_pll *pll =3D clk->pll; -> const struct iproc_pll_ctrl *ctrl =3D pll->ctrl; +> @@ -345,8 +345,8 @@ static unsigned long iproc_pll_recalc_rate(struct clk_hw *hw, +> struct iproc_pll *pll = clk->pll; +> const struct iproc_pll_ctrl *ctrl = pll->ctrl; > u32 val; > - u64 ndiv; > - unsigned int ndiv_int, ndiv_frac, pdiv; > + u64 ndiv, ndiv_int, ndiv_frac; > + unsigned int pdiv; -> = - -> if (parent_rate =3D=3D 0) +> +> if (parent_rate == 0) > return 0; -> @@ -366,22 +366,19 @@ static unsigned long iproc_pll_recalc_rate(struct c= -lk_hw *hw, -> val =3D readl(pll->pll_base + ctrl->ndiv_int.offset); -> ndiv_int =3D (val >> ctrl->ndiv_int.shift) & +> @@ -366,22 +366,19 @@ static unsigned long iproc_pll_recalc_rate(struct clk_hw *hw, +> val = readl(pll->pll_base + ctrl->ndiv_int.offset); +> ndiv_int = (val >> ctrl->ndiv_int.shift) & > bit_mask(ctrl->ndiv_int.width); -> - ndiv =3D (u64)ndiv_int << ctrl->ndiv_int.shift; -> + ndiv =3D ndiv_int << 20; -> = - +> - ndiv = (u64)ndiv_int << ctrl->ndiv_int.shift; +> + ndiv = ndiv_int << 20; +> > if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) { -> val =3D readl(pll->pll_base + ctrl->ndiv_frac.offset); -> ndiv_frac =3D (val >> ctrl->ndiv_frac.shift) & +> val = readl(pll->pll_base + ctrl->ndiv_frac.offset); +> ndiv_frac = (val >> ctrl->ndiv_frac.shift) & > bit_mask(ctrl->ndiv_frac.width); > - -> - if (ndiv_frac !=3D 0) -> - ndiv =3D ((u64)ndiv_int << ctrl->ndiv_int.shift) | +> - if (ndiv_frac != 0) +> - ndiv = ((u64)ndiv_int << ctrl->ndiv_int.shift) | > - ndiv_frac; -> + ndiv +=3D ndiv_frac; +> + ndiv += ndiv_frac; > } -> = - -> val =3D readl(pll->pll_base + ctrl->pdiv.offset); -> pdiv =3D (val >> ctrl->pdiv.shift) & bit_mask(ctrl->pdiv.width); -> = - -> - clk->rate =3D (ndiv * parent_rate) >> ctrl->ndiv_int.shift; -> + clk->rate =3D (ndiv * parent_rate) >> 20; -> = - -> if (pdiv =3D=3D 0) -> clk->rate *=3D 2; -> -- = - +> +> val = readl(pll->pll_base + ctrl->pdiv.offset); +> pdiv = (val >> ctrl->pdiv.shift) & bit_mask(ctrl->pdiv.width); +> +> - clk->rate = (ndiv * parent_rate) >> ctrl->ndiv_int.shift; +> + clk->rate = (ndiv * parent_rate) >> 20; +> +> if (pdiv == 0) +> clk->rate *= 2; +> -- > 1.9.1 ->=20 +> diff --git a/a/content_digest b/N1/content_digest index 6d65f28..cf043ad 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -15,14 +15,12 @@ "b\0" "Quoting Ray Jui (2015-10-19 15:27:19)\n" "> From: Simran Rai <ssimran@broadcom.com>\n" - "> =\n" - "\n" + "> \n" "> This patch affects the clocks that use fractional ndivider in their\n" "> PLL output frequency calculation. Instead of 2^20 divide factor, the\n" "> clock's ndiv integer shift was used. Fixed the bug by replacing ndiv\n" "> integer shift with 2^20 factor.\n" - "> =\n" - "\n" + "> \n" "> Signed-off-by: Simran Rai <ssimran@broadcom.com>\n" "> Signed-off-by: Ray Jui <rjui@broadcom.com>\n" "> Reviewed-by: Scott Branden <sbranden@broadcom.com>\n" @@ -36,60 +34,50 @@ "> ---\n" "> drivers/clk/bcm/clk-iproc-pll.c | 13 +++++--------\n" "> 1 file changed, 5 insertions(+), 8 deletions(-)\n" - "> =\n" - "\n" - "> diff --git a/drivers/clk/bcm/clk-iproc-pll.c b/drivers/clk/bcm/clk-iproc-=\n" - "pll.c\n" + "> \n" + "> diff --git a/drivers/clk/bcm/clk-iproc-pll.c b/drivers/clk/bcm/clk-iproc-pll.c\n" "> index 2dda4e8..d679ab8 100644\n" "> --- a/drivers/clk/bcm/clk-iproc-pll.c\n" "> +++ b/drivers/clk/bcm/clk-iproc-pll.c\n" - "> @@ -345,8 +345,8 @@ static unsigned long iproc_pll_recalc_rate(struct clk=\n" - "_hw *hw,\n" - "> struct iproc_pll *pll =3D clk->pll;\n" - "> const struct iproc_pll_ctrl *ctrl =3D pll->ctrl;\n" + "> @@ -345,8 +345,8 @@ static unsigned long iproc_pll_recalc_rate(struct clk_hw *hw,\n" + "> struct iproc_pll *pll = clk->pll;\n" + "> const struct iproc_pll_ctrl *ctrl = pll->ctrl;\n" "> u32 val;\n" "> - u64 ndiv;\n" "> - unsigned int ndiv_int, ndiv_frac, pdiv;\n" "> + u64 ndiv, ndiv_int, ndiv_frac;\n" "> + unsigned int pdiv;\n" - "> =\n" - "\n" - "> if (parent_rate =3D=3D 0)\n" + "> \n" + "> if (parent_rate == 0)\n" "> return 0;\n" - "> @@ -366,22 +366,19 @@ static unsigned long iproc_pll_recalc_rate(struct c=\n" - "lk_hw *hw,\n" - "> val =3D readl(pll->pll_base + ctrl->ndiv_int.offset);\n" - "> ndiv_int =3D (val >> ctrl->ndiv_int.shift) &\n" + "> @@ -366,22 +366,19 @@ static unsigned long iproc_pll_recalc_rate(struct clk_hw *hw,\n" + "> val = readl(pll->pll_base + ctrl->ndiv_int.offset);\n" + "> ndiv_int = (val >> ctrl->ndiv_int.shift) &\n" "> bit_mask(ctrl->ndiv_int.width);\n" - "> - ndiv =3D (u64)ndiv_int << ctrl->ndiv_int.shift;\n" - "> + ndiv =3D ndiv_int << 20;\n" - "> =\n" - "\n" + "> - ndiv = (u64)ndiv_int << ctrl->ndiv_int.shift;\n" + "> + ndiv = ndiv_int << 20;\n" + "> \n" "> if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) {\n" - "> val =3D readl(pll->pll_base + ctrl->ndiv_frac.offset);\n" - "> ndiv_frac =3D (val >> ctrl->ndiv_frac.shift) &\n" + "> val = readl(pll->pll_base + ctrl->ndiv_frac.offset);\n" + "> ndiv_frac = (val >> ctrl->ndiv_frac.shift) &\n" "> bit_mask(ctrl->ndiv_frac.width);\n" "> -\n" - "> - if (ndiv_frac !=3D 0)\n" - "> - ndiv =3D ((u64)ndiv_int << ctrl->ndiv_int.shift) |\n" + "> - if (ndiv_frac != 0)\n" + "> - ndiv = ((u64)ndiv_int << ctrl->ndiv_int.shift) |\n" "> - ndiv_frac;\n" - "> + ndiv +=3D ndiv_frac;\n" + "> + ndiv += ndiv_frac;\n" "> }\n" - "> =\n" - "\n" - "> val =3D readl(pll->pll_base + ctrl->pdiv.offset);\n" - "> pdiv =3D (val >> ctrl->pdiv.shift) & bit_mask(ctrl->pdiv.width);\n" - "> =\n" - "\n" - "> - clk->rate =3D (ndiv * parent_rate) >> ctrl->ndiv_int.shift;\n" - "> + clk->rate =3D (ndiv * parent_rate) >> 20;\n" - "> =\n" - "\n" - "> if (pdiv =3D=3D 0)\n" - "> clk->rate *=3D 2;\n" - "> -- =\n" - "\n" + "> \n" + "> val = readl(pll->pll_base + ctrl->pdiv.offset);\n" + "> pdiv = (val >> ctrl->pdiv.shift) & bit_mask(ctrl->pdiv.width);\n" + "> \n" + "> - clk->rate = (ndiv * parent_rate) >> ctrl->ndiv_int.shift;\n" + "> + clk->rate = (ndiv * parent_rate) >> 20;\n" + "> \n" + "> if (pdiv == 0)\n" + "> clk->rate *= 2;\n" + "> -- \n" "> 1.9.1\n" - >=20 + > -4688847a1330558bafea3ec9ac18d709b6fcac3606286ff44cce8325f484560e +6412da9d974984c4b3dc2a99f033aa08396a639347c438c6bb43ca444f452861
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