diff for duplicates of <20151022080508.GN10947@lukather> diff --git a/a/1.txt b/N1/1.txt index 0ace8d7..dba731b 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -4,7 +4,7 @@ On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > The Allwinner H3 is a home entertainment system oriented SoC with > four Cortex-A7 cores and a Mali-400MP2 GPU. > -> Signed-off-by: Jens Kuske <jenskuske@gmail.com> +> Signed-off-by: Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> > --- > arch/arm/boot/dts/sun8i-h3.dtsi | 499 ++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 499 insertions(+) @@ -17,7 +17,7 @@ On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > +++ b/arch/arm/boot/dts/sun8i-h3.dtsi > @@ -0,0 +1,499 @@ > +/* -> + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> +> + * Copyright (C) 2015 Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual @@ -70,25 +70,25 @@ On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > + #address-cells = <1>; > + #size-cells = <0>; > + -> + cpu at 0 { +> + cpu@0 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <0>; > + }; > + -> + cpu at 1 { +> + cpu@1 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <1>; > + }; > + -> + cpu at 2 { +> + cpu@2 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <2>; > + }; > + -> + cpu at 3 { +> + cpu@3 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <3>; @@ -128,7 +128,7 @@ On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > + clock-output-names = "osc32k"; > + }; > + -> + pll1: clk at 01c20000 { +> + pll1: clk@01c20000 { > + #clock-cells = <0>; > + compatible = "allwinner,sun8i-a23-pll1-clk"; > + reg = <0x01c20000 0x4>; @@ -144,7 +144,7 @@ On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > + clock-output-names = "pll5"; > + }; > + -> + pll6: clk at 01c20028 { +> + pll6: clk@01c20028 { > + #clock-cells = <1>; > + compatible = "allwinner,sun6i-a31-pll6-clk"; > + reg = <0x01c20028 0x4>; @@ -152,7 +152,7 @@ On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > + clock-output-names = "pll6", "pll6x2", "pll6d2"; > + }; > + -> + pll8: clk at 01c20044 { +> + pll8: clk@01c20044 { > + #clock-cells = <0>; > + compatible = "allwinner,sun6i-a31-pll6-clk"; > + reg = <0x01c20044 0x4>; @@ -160,7 +160,7 @@ On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > + clock-output-names = "pll8", "pll8x2"; > + }; > + -> + cpu: cpu_clk at 01c20050 { +> + cpu: cpu_clk@01c20050 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-cpu-clk"; > + reg = <0x01c20050 0x4>; @@ -168,7 +168,7 @@ On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > + clock-output-names = "cpu"; > + }; > + -> + axi: axi_clk at 01c20050 { +> + axi: axi_clk@01c20050 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-axi-clk"; > + reg = <0x01c20050 0x4>; @@ -176,7 +176,7 @@ On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > + clock-output-names = "axi"; > + }; > + -> + ahb1: ahb1_clk at 01c20054 { +> + ahb1: ahb1_clk@01c20054 { > + #clock-cells = <0>; > + compatible = "allwinner,sun6i-a31-ahb1-clk"; > + reg = <0x01c20054 0x4>; @@ -184,7 +184,7 @@ On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > + clock-output-names = "ahb1"; > + }; > + -> + ahb2: ahb2_clk at 01c2005c { +> + ahb2: ahb2_clk@01c2005c { > + #clock-cells = <0>; > + compatible = "allwinner,sun8i-h3-ahb2-clk"; > + reg = <0x01c2005c 0x4>; @@ -192,7 +192,7 @@ On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > + clock-output-names = "ahb2"; > + }; > + -> + apb1: apb1_clk at 01c20054 { +> + apb1: apb1_clk@01c20054 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-apb0-clk"; > + reg = <0x01c20054 0x4>; @@ -200,7 +200,7 @@ On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > + clock-output-names = "apb1"; > + }; > + -> + apb2: apb2_clk at 01c20058 { +> + apb2: apb2_clk@01c20058 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-apb1-clk"; > + reg = <0x01c20058 0x4>; @@ -208,7 +208,7 @@ On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > + clock-output-names = "apb2"; > + }; > + -> + bus_gates: clk at 01c20060 { +> + bus_gates: clk@01c20060 { > + #clock-cells = <1>; > + compatible = "allwinner,sun8i-h3-bus-gates-clk"; > + reg = <0x01c20060 0x14>; @@ -271,7 +271,7 @@ On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > + "ahb1_ephy", "ahb1_dbg"; > + }; > + -> + mmc0_clk: clk at 01c20088 { +> + mmc0_clk: clk@01c20088 { > + #clock-cells = <1>; > + compatible = "allwinner,sun4i-a10-mmc-clk"; > + reg = <0x01c20088 0x4>; @@ -281,7 +281,7 @@ On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > + "mmc0_sample"; > + }; > + -> + mmc1_clk: clk at 01c2008c { +> + mmc1_clk: clk@01c2008c { > + #clock-cells = <1>; > + compatible = "allwinner,sun4i-a10-mmc-clk"; > + reg = <0x01c2008c 0x4>; @@ -291,7 +291,7 @@ On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > + "mmc1_sample"; > + }; > + -> + mmc2_clk: clk at 01c20090 { +> + mmc2_clk: clk@01c20090 { > + #clock-cells = <1>; > + compatible = "allwinner,sun4i-a10-mmc-clk"; > + reg = <0x01c20090 0x4>; @@ -301,7 +301,7 @@ On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > + "mmc2_sample"; > + }; > + -> + mbus_clk: clk at 01c2015c { +> + mbus_clk: clk@01c2015c { > + #clock-cells = <0>; > + compatible = "allwinner,sun8i-a23-mbus-clk"; > + reg = <0x01c2015c 0x4>; @@ -310,13 +310,13 @@ On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > + }; > + }; > + -> + soc at 01c00000 { +> + soc@01c00000 { We had some issues with this in the past, especially since it's wrong and the SoC registers definitions start at 0, with the SRAMs. It would be better if you removed it entirely like we did in the A80 DTSI. -> + uart0: serial at 01c28000 { +> + uart0: serial@01c28000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28000 0x400>; > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; @@ -338,10 +338,3 @@ Maxime Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --------------- next part -------------- -A non-text attachment was scrubbed... -Name: signature.asc -Type: application/pgp-signature -Size: 819 bytes -Desc: Digital signature -URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20151022/32e72439/attachment-0001.sig> diff --git a/a/content_digest b/N1/content_digest index 53a9081..2c64e60 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,10 +1,23 @@ "ref\01445444428-4652-1-git-send-email-jenskuske@gmail.com\0" "ref\01445444428-4652-2-git-send-email-jenskuske@gmail.com\0" - "From\0maxime.ripard@free-electrons.com (Maxime Ripard)\0" - "Subject\0[PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI\0" + "ref\01445444428-4652-2-git-send-email-jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org\0" + "From\0Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>\0" + "Subject\0Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI\0" "Date\0Thu, 22 Oct 2015 10:05:08 +0200\0" - "To\0linux-arm-kernel@lists.infradead.org\0" - "\00:1\0" + "To\0Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0" + "Cc\0Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>" + Michael Turquette <mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> + Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> + Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> + Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> + " Emilio L\303\263pez <emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org>" + Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> + Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + " linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org\0" + "\01:1\0" "b\0" "Hi,\n" "\n" @@ -12,7 +25,7 @@ "> The Allwinner H3 is a home entertainment system oriented SoC with\n" "> four Cortex-A7 cores and a Mali-400MP2 GPU.\n" "> \n" - "> Signed-off-by: Jens Kuske <jenskuske@gmail.com>\n" + "> Signed-off-by: Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\n" "> ---\n" "> arch/arm/boot/dts/sun8i-h3.dtsi | 499 ++++++++++++++++++++++++++++++++++++++++\n" "> 1 file changed, 499 insertions(+)\n" @@ -25,7 +38,7 @@ "> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi\n" "> @@ -0,0 +1,499 @@\n" "> +/*\n" - "> + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>\n" + "> + * Copyright (C) 2015 Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\n" "> + *\n" "> + * This file is dual-licensed: you can use it either under the terms\n" "> + * of the GPL or the X11 license, at your option. Note that this dual\n" @@ -78,25 +91,25 @@ "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\tcpu at 0 {\n" + "> +\t\tcpu@0 {\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 1 {\n" + "> +\t\tcpu@1 {\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 2 {\n" + "> +\t\tcpu@2 {\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 3 {\n" + "> +\t\tcpu@3 {\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <3>;\n" @@ -136,7 +149,7 @@ "> +\t\t\tclock-output-names = \"osc32k\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tpll1: clk at 01c20000 {\n" + "> +\t\tpll1: clk@01c20000 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun8i-a23-pll1-clk\";\n" "> +\t\t\treg = <0x01c20000 0x4>;\n" @@ -152,7 +165,7 @@ "> +\t\t\tclock-output-names = \"pll5\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tpll6: clk at 01c20028 {\n" + "> +\t\tpll6: clk@01c20028 {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-pll6-clk\";\n" "> +\t\t\treg = <0x01c20028 0x4>;\n" @@ -160,7 +173,7 @@ "> +\t\t\tclock-output-names = \"pll6\", \"pll6x2\", \"pll6d2\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tpll8: clk at 01c20044 {\n" + "> +\t\tpll8: clk@01c20044 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-pll6-clk\";\n" "> +\t\t\treg = <0x01c20044 0x4>;\n" @@ -168,7 +181,7 @@ "> +\t\t\tclock-output-names = \"pll8\", \"pll8x2\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu: cpu_clk at 01c20050 {\n" + "> +\t\tcpu: cpu_clk@01c20050 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-cpu-clk\";\n" "> +\t\t\treg = <0x01c20050 0x4>;\n" @@ -176,7 +189,7 @@ "> +\t\t\tclock-output-names = \"cpu\";\n" "> +\t\t};\n" "> +\n" - "> +\t\taxi: axi_clk at 01c20050 {\n" + "> +\t\taxi: axi_clk@01c20050 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-axi-clk\";\n" "> +\t\t\treg = <0x01c20050 0x4>;\n" @@ -184,7 +197,7 @@ "> +\t\t\tclock-output-names = \"axi\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tahb1: ahb1_clk at 01c20054 {\n" + "> +\t\tahb1: ahb1_clk@01c20054 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-ahb1-clk\";\n" "> +\t\t\treg = <0x01c20054 0x4>;\n" @@ -192,7 +205,7 @@ "> +\t\t\tclock-output-names = \"ahb1\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tahb2: ahb2_clk at 01c2005c {\n" + "> +\t\tahb2: ahb2_clk@01c2005c {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun8i-h3-ahb2-clk\";\n" "> +\t\t\treg = <0x01c2005c 0x4>;\n" @@ -200,7 +213,7 @@ "> +\t\t\tclock-output-names = \"ahb2\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb1: apb1_clk at 01c20054 {\n" + "> +\t\tapb1: apb1_clk@01c20054 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-apb0-clk\";\n" "> +\t\t\treg = <0x01c20054 0x4>;\n" @@ -208,7 +221,7 @@ "> +\t\t\tclock-output-names = \"apb1\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb2: apb2_clk at 01c20058 {\n" + "> +\t\tapb2: apb2_clk@01c20058 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-apb1-clk\";\n" "> +\t\t\treg = <0x01c20058 0x4>;\n" @@ -216,7 +229,7 @@ "> +\t\t\tclock-output-names = \"apb2\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tbus_gates: clk at 01c20060 {\n" + "> +\t\tbus_gates: clk@01c20060 {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun8i-h3-bus-gates-clk\";\n" "> +\t\t\treg = <0x01c20060 0x14>;\n" @@ -279,7 +292,7 @@ "> +\t\t\t\t\t\"ahb1_ephy\", \"ahb1_dbg\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc0_clk: clk at 01c20088 {\n" + "> +\t\tmmc0_clk: clk@01c20088 {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" "> +\t\t\treg = <0x01c20088 0x4>;\n" @@ -289,7 +302,7 @@ "> +\t\t\t\t\t \"mmc0_sample\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc1_clk: clk at 01c2008c {\n" + "> +\t\tmmc1_clk: clk@01c2008c {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" "> +\t\t\treg = <0x01c2008c 0x4>;\n" @@ -299,7 +312,7 @@ "> +\t\t\t\t\t \"mmc1_sample\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc2_clk: clk at 01c20090 {\n" + "> +\t\tmmc2_clk: clk@01c20090 {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" "> +\t\t\treg = <0x01c20090 0x4>;\n" @@ -309,7 +322,7 @@ "> +\t\t\t\t\t \"mmc2_sample\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tmbus_clk: clk at 01c2015c {\n" + "> +\t\tmbus_clk: clk@01c2015c {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun8i-a23-mbus-clk\";\n" "> +\t\t\treg = <0x01c2015c 0x4>;\n" @@ -318,13 +331,13 @@ "> +\t\t};\n" "> +\t};\n" "> +\n" - "> +\tsoc at 01c00000 {\n" + "> +\tsoc@01c00000 {\n" "\n" "We had some issues with this in the past, especially since it's wrong\n" "and the SoC registers definitions start at 0, with the SRAMs. It would\n" "be better if you removed it entirely like we did in the A80 DTSI.\n" "\n" - "> +\t\tuart0: serial at 01c28000 {\n" + "> +\t\tuart0: serial@01c28000 {\n" "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\treg = <0x01c28000 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -345,13 +358,6 @@ "-- \n" "Maxime Ripard, Free Electrons\n" "Embedded Linux, Kernel and Android engineering\n" - "http://free-electrons.com\n" - "-------------- next part --------------\n" - "A non-text attachment was scrubbed...\n" - "Name: signature.asc\n" - "Type: application/pgp-signature\n" - "Size: 819 bytes\n" - "Desc: Digital signature\n" - URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20151022/32e72439/attachment-0001.sig> + http://free-electrons.com -79c22badab5fc10a67140c928ef31c73381c97d78f2c67dd55f6c3bfb1fb7699 +e8c450858ebc89ee368b6e750fe1fa630dfee05bf91c1fac5f9a3a5e6a97b1d3
diff --git a/a/1.txt b/N2/1.txt index 0ace8d7..b1cb4ee 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -70,25 +70,25 @@ On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > + #address-cells = <1>; > + #size-cells = <0>; > + -> + cpu at 0 { +> + cpu@0 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <0>; > + }; > + -> + cpu at 1 { +> + cpu@1 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <1>; > + }; > + -> + cpu at 2 { +> + cpu@2 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <2>; > + }; > + -> + cpu at 3 { +> + cpu@3 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <3>; @@ -128,7 +128,7 @@ On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > + clock-output-names = "osc32k"; > + }; > + -> + pll1: clk at 01c20000 { +> + pll1: clk@01c20000 { > + #clock-cells = <0>; > + compatible = "allwinner,sun8i-a23-pll1-clk"; > + reg = <0x01c20000 0x4>; @@ -144,7 +144,7 @@ On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > + clock-output-names = "pll5"; > + }; > + -> + pll6: clk at 01c20028 { +> + pll6: clk@01c20028 { > + #clock-cells = <1>; > + compatible = "allwinner,sun6i-a31-pll6-clk"; > + reg = <0x01c20028 0x4>; @@ -152,7 +152,7 @@ On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > + clock-output-names = "pll6", "pll6x2", "pll6d2"; > + }; > + -> + pll8: clk at 01c20044 { +> + pll8: clk@01c20044 { > + #clock-cells = <0>; > + compatible = "allwinner,sun6i-a31-pll6-clk"; > + reg = <0x01c20044 0x4>; @@ -160,7 +160,7 @@ On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > + clock-output-names = "pll8", "pll8x2"; > + }; > + -> + cpu: cpu_clk at 01c20050 { +> + cpu: cpu_clk@01c20050 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-cpu-clk"; > + reg = <0x01c20050 0x4>; @@ -168,7 +168,7 @@ On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > + clock-output-names = "cpu"; > + }; > + -> + axi: axi_clk at 01c20050 { +> + axi: axi_clk@01c20050 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-axi-clk"; > + reg = <0x01c20050 0x4>; @@ -176,7 +176,7 @@ On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > + clock-output-names = "axi"; > + }; > + -> + ahb1: ahb1_clk at 01c20054 { +> + ahb1: ahb1_clk@01c20054 { > + #clock-cells = <0>; > + compatible = "allwinner,sun6i-a31-ahb1-clk"; > + reg = <0x01c20054 0x4>; @@ -184,7 +184,7 @@ On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > + clock-output-names = "ahb1"; > + }; > + -> + ahb2: ahb2_clk at 01c2005c { +> + ahb2: ahb2_clk@01c2005c { > + #clock-cells = <0>; > + compatible = "allwinner,sun8i-h3-ahb2-clk"; > + reg = <0x01c2005c 0x4>; @@ -192,7 +192,7 @@ On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > + clock-output-names = "ahb2"; > + }; > + -> + apb1: apb1_clk at 01c20054 { +> + apb1: apb1_clk@01c20054 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-apb0-clk"; > + reg = <0x01c20054 0x4>; @@ -200,7 +200,7 @@ On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > + clock-output-names = "apb1"; > + }; > + -> + apb2: apb2_clk at 01c20058 { +> + apb2: apb2_clk@01c20058 { > + #clock-cells = <0>; > + compatible = "allwinner,sun4i-a10-apb1-clk"; > + reg = <0x01c20058 0x4>; @@ -208,7 +208,7 @@ On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > + clock-output-names = "apb2"; > + }; > + -> + bus_gates: clk at 01c20060 { +> + bus_gates: clk@01c20060 { > + #clock-cells = <1>; > + compatible = "allwinner,sun8i-h3-bus-gates-clk"; > + reg = <0x01c20060 0x14>; @@ -271,7 +271,7 @@ On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > + "ahb1_ephy", "ahb1_dbg"; > + }; > + -> + mmc0_clk: clk at 01c20088 { +> + mmc0_clk: clk@01c20088 { > + #clock-cells = <1>; > + compatible = "allwinner,sun4i-a10-mmc-clk"; > + reg = <0x01c20088 0x4>; @@ -281,7 +281,7 @@ On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > + "mmc0_sample"; > + }; > + -> + mmc1_clk: clk at 01c2008c { +> + mmc1_clk: clk@01c2008c { > + #clock-cells = <1>; > + compatible = "allwinner,sun4i-a10-mmc-clk"; > + reg = <0x01c2008c 0x4>; @@ -291,7 +291,7 @@ On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > + "mmc1_sample"; > + }; > + -> + mmc2_clk: clk at 01c20090 { +> + mmc2_clk: clk@01c20090 { > + #clock-cells = <1>; > + compatible = "allwinner,sun4i-a10-mmc-clk"; > + reg = <0x01c20090 0x4>; @@ -301,7 +301,7 @@ On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > + "mmc2_sample"; > + }; > + -> + mbus_clk: clk at 01c2015c { +> + mbus_clk: clk@01c2015c { > + #clock-cells = <0>; > + compatible = "allwinner,sun8i-a23-mbus-clk"; > + reg = <0x01c2015c 0x4>; @@ -310,13 +310,13 @@ On Wed, Oct 21, 2015 at 06:20:27PM +0200, Jens Kuske wrote: > + }; > + }; > + -> + soc at 01c00000 { +> + soc@01c00000 { We had some issues with this in the past, especially since it's wrong and the SoC registers definitions start at 0, with the SRAMs. It would be better if you removed it entirely like we did in the A80 DTSI. -> + uart0: serial at 01c28000 { +> + uart0: serial@01c28000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x01c28000 0x400>; > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; @@ -338,10 +338,3 @@ Maxime Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --------------- next part -------------- -A non-text attachment was scrubbed... -Name: signature.asc -Type: application/pgp-signature -Size: 819 bytes -Desc: Digital signature -URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20151022/32e72439/attachment-0001.sig> diff --git a/N2/2.bin b/N2/2.bin new file mode 100644 index 0000000..4394070 --- /dev/null +++ b/N2/2.bin @@ -0,0 +1,17 @@ +-----BEGIN PGP SIGNATURE----- +Version: GnuPG v1 + +iQIcBAEBAgAGBQJWKJi0AAoJEBx+YmzsjxAgYZYP/Ricp8N5F2wAXYhgNtCbmYBD +gkoqyDgT/oEHU5k0RKrLPiBkL3NrUL5FOxdjGe7Hj6UlcMzrSfFKQpQq9wpVDIHL +Tw4625rl4yQnX7i007NKSYI+orFitTsxLu+896NTspmF/+dMou2T+JReVnC42+i6 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"ref\01445444428-4652-1-git-send-email-jenskuske@gmail.com\0" "ref\01445444428-4652-2-git-send-email-jenskuske@gmail.com\0" - "From\0maxime.ripard@free-electrons.com (Maxime Ripard)\0" - "Subject\0[PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI\0" + "From\0Maxime Ripard <maxime.ripard@free-electrons.com>\0" + "Subject\0Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI\0" "Date\0Thu, 22 Oct 2015 10:05:08 +0200\0" - "To\0linux-arm-kernel@lists.infradead.org\0" - "\00:1\0" + "To\0Jens Kuske <jenskuske@gmail.com>\0" + "Cc\0Chen-Yu Tsai <wens@csie.org>" + Michael Turquette <mturquette@baylibre.com> + Linus Walleij <linus.walleij@linaro.org> + Rob Herring <robh+dt@kernel.org> + Philipp Zabel <p.zabel@pengutronix.de> + " Emilio L\303\263pez <emilio@elopez.com.ar>" + Vishnu Patekar <vishnupatekar0510@gmail.com> + Hans de Goede <hdegoede@redhat.com> + devicetree@vger.kernel.org + linux-arm-kernel@lists.infradead.org + linux-kernel@vger.kernel.org + " linux-sunxi@googlegroups.com\0" + "\01:1\0" "b\0" "Hi,\n" "\n" @@ -78,25 +90,25 @@ "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\tcpu at 0 {\n" + "> +\t\tcpu@0 {\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <0>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 1 {\n" + "> +\t\tcpu@1 {\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 2 {\n" + "> +\t\tcpu@2 {\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu at 3 {\n" + "> +\t\tcpu@3 {\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\treg = <3>;\n" @@ -136,7 +148,7 @@ "> +\t\t\tclock-output-names = \"osc32k\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tpll1: clk at 01c20000 {\n" + "> +\t\tpll1: clk@01c20000 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun8i-a23-pll1-clk\";\n" "> +\t\t\treg = <0x01c20000 0x4>;\n" @@ -152,7 +164,7 @@ "> +\t\t\tclock-output-names = \"pll5\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tpll6: clk at 01c20028 {\n" + "> +\t\tpll6: clk@01c20028 {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-pll6-clk\";\n" "> +\t\t\treg = <0x01c20028 0x4>;\n" @@ -160,7 +172,7 @@ "> +\t\t\tclock-output-names = \"pll6\", \"pll6x2\", \"pll6d2\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tpll8: clk at 01c20044 {\n" + "> +\t\tpll8: clk@01c20044 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-pll6-clk\";\n" "> +\t\t\treg = <0x01c20044 0x4>;\n" @@ -168,7 +180,7 @@ "> +\t\t\tclock-output-names = \"pll8\", \"pll8x2\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu: cpu_clk at 01c20050 {\n" + "> +\t\tcpu: cpu_clk@01c20050 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-cpu-clk\";\n" "> +\t\t\treg = <0x01c20050 0x4>;\n" @@ -176,7 +188,7 @@ "> +\t\t\tclock-output-names = \"cpu\";\n" "> +\t\t};\n" "> +\n" - "> +\t\taxi: axi_clk at 01c20050 {\n" + "> +\t\taxi: axi_clk@01c20050 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-axi-clk\";\n" "> +\t\t\treg = <0x01c20050 0x4>;\n" @@ -184,7 +196,7 @@ "> +\t\t\tclock-output-names = \"axi\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tahb1: ahb1_clk at 01c20054 {\n" + "> +\t\tahb1: ahb1_clk@01c20054 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun6i-a31-ahb1-clk\";\n" "> +\t\t\treg = <0x01c20054 0x4>;\n" @@ -192,7 +204,7 @@ "> +\t\t\tclock-output-names = \"ahb1\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tahb2: ahb2_clk at 01c2005c {\n" + "> +\t\tahb2: ahb2_clk@01c2005c {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun8i-h3-ahb2-clk\";\n" "> +\t\t\treg = <0x01c2005c 0x4>;\n" @@ -200,7 +212,7 @@ "> +\t\t\tclock-output-names = \"ahb2\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb1: apb1_clk at 01c20054 {\n" + "> +\t\tapb1: apb1_clk@01c20054 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-apb0-clk\";\n" "> +\t\t\treg = <0x01c20054 0x4>;\n" @@ -208,7 +220,7 @@ "> +\t\t\tclock-output-names = \"apb1\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb2: apb2_clk at 01c20058 {\n" + "> +\t\tapb2: apb2_clk@01c20058 {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-apb1-clk\";\n" "> +\t\t\treg = <0x01c20058 0x4>;\n" @@ -216,7 +228,7 @@ "> +\t\t\tclock-output-names = \"apb2\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tbus_gates: clk at 01c20060 {\n" + "> +\t\tbus_gates: clk@01c20060 {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun8i-h3-bus-gates-clk\";\n" "> +\t\t\treg = <0x01c20060 0x14>;\n" @@ -279,7 +291,7 @@ "> +\t\t\t\t\t\"ahb1_ephy\", \"ahb1_dbg\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc0_clk: clk at 01c20088 {\n" + "> +\t\tmmc0_clk: clk@01c20088 {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" "> +\t\t\treg = <0x01c20088 0x4>;\n" @@ -289,7 +301,7 @@ "> +\t\t\t\t\t \"mmc0_sample\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc1_clk: clk at 01c2008c {\n" + "> +\t\tmmc1_clk: clk@01c2008c {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" "> +\t\t\treg = <0x01c2008c 0x4>;\n" @@ -299,7 +311,7 @@ "> +\t\t\t\t\t \"mmc1_sample\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tmmc2_clk: clk at 01c20090 {\n" + "> +\t\tmmc2_clk: clk@01c20090 {\n" "> +\t\t\t#clock-cells = <1>;\n" "> +\t\t\tcompatible = \"allwinner,sun4i-a10-mmc-clk\";\n" "> +\t\t\treg = <0x01c20090 0x4>;\n" @@ -309,7 +321,7 @@ "> +\t\t\t\t\t \"mmc2_sample\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tmbus_clk: clk at 01c2015c {\n" + "> +\t\tmbus_clk: clk@01c2015c {\n" "> +\t\t\t#clock-cells = <0>;\n" "> +\t\t\tcompatible = \"allwinner,sun8i-a23-mbus-clk\";\n" "> +\t\t\treg = <0x01c2015c 0x4>;\n" @@ -318,13 +330,13 @@ "> +\t\t};\n" "> +\t};\n" "> +\n" - "> +\tsoc at 01c00000 {\n" + "> +\tsoc@01c00000 {\n" "\n" "We had some issues with this in the past, especially since it's wrong\n" "and the SoC registers definitions start at 0, with the SRAMs. It would\n" "be better if you removed it entirely like we did in the A80 DTSI.\n" "\n" - "> +\t\tuart0: serial at 01c28000 {\n" + "> +\t\tuart0: serial@01c28000 {\n" "> +\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\treg = <0x01c28000 0x400>;\n" "> +\t\t\tinterrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -345,13 +357,27 @@ "-- \n" "Maxime Ripard, Free Electrons\n" "Embedded Linux, Kernel and Android engineering\n" - "http://free-electrons.com\n" - "-------------- next part --------------\n" - "A non-text attachment was scrubbed...\n" - "Name: signature.asc\n" - "Type: application/pgp-signature\n" - "Size: 819 bytes\n" - "Desc: Digital signature\n" - URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20151022/32e72439/attachment-0001.sig> + http://free-electrons.com + "\01:2\0" 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