From mboxrd@z Thu Jan 1 00:00:00 1970 From: moinejf@free.fr (Jean-Francois Moine) Date: Thu, 22 Oct 2015 10:57:45 +0200 Subject: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI In-Reply-To: <20151022084735.GR10947@lukather> References: <1445444428-4652-1-git-send-email-jenskuske@gmail.com> <1445444428-4652-2-git-send-email-jenskuske@gmail.com> <20151022080508.GN10947@lukather> <20151022102959.09f0a1f4@OPI2> <20151022084735.GR10947@lukather> Message-ID: <20151022105745.2cc158a3@OPI2> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Thu, 22 Oct 2015 10:47:35 +0200 Maxime Ripard wrote: > Not really. The uart0 reset is the bit 16, in the reset register 4. > > 4 * 32 + 16 = 44. > > Not 112, but still not 208 either. The registers are numbered 1..5, then (4 - 1) * 32 + 16 = 112 -- Ken ar c'henta? | ** Breizh ha Linux atav! ** Jef | http://moinejf.free.fr/ From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jean-Francois Moine Subject: Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI Date: Thu, 22 Oct 2015 10:57:45 +0200 Message-ID: <20151022105745.2cc158a3@OPI2> References: <1445444428-4652-1-git-send-email-jenskuske@gmail.com> <1445444428-4652-2-git-send-email-jenskuske@gmail.com> <20151022080508.GN10947@lukather> <20151022102959.09f0a1f4@OPI2> <20151022084735.GR10947@lukather> Reply-To: moinejf-GANU6spQydw@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <20151022084735.GR10947@lukather> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Maxime Ripard Cc: Jens Kuske , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Vishnu Patekar , Emilio =?UTF-8?B?TMOzcGV6?= , Michael Turquette , linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Hans de Goede , Chen-Yu Tsai , Rob Herring , Philipp Zabel , Linus Walleij , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: devicetree@vger.kernel.org On Thu, 22 Oct 2015 10:47:35 +0200 Maxime Ripard wrote: > Not really. The uart0 reset is the bit 16, in the reset register 4. >=20 > 4 * 32 + 16 =3D 44. >=20 > Not 112, but still not 208 either. The registers are numbered 1..5, then (4 - 1) * 32 + 16 =3D 112 --=20 Ken ar c'henta=C3=B1 | ** Breizh ha Linux atav! ** Jef | http://moinejf.free.fr/ --=20 You received this message because you are subscribed to the Google Groups "= linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an e= mail to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org For more options, visit https://groups.google.com/d/optout. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757000AbbJVI6L (ORCPT ); Thu, 22 Oct 2015 04:58:11 -0400 Received: from smtp3-g21.free.fr ([212.27.42.3]:31531 "EHLO smtp3-g21.free.fr" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756961AbbJVI6E convert rfc822-to-8bit (ORCPT ); Thu, 22 Oct 2015 04:58:04 -0400 Date: Thu, 22 Oct 2015 10:57:45 +0200 From: Jean-Francois Moine To: Maxime Ripard Cc: Jens Kuske , devicetree@vger.kernel.org, Vishnu Patekar , Emilio =?UTF-8?B?TMOzcGV6?= , Michael Turquette , linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org, Hans de Goede , Chen-Yu Tsai , Rob Herring , Philipp Zabel , Linus Walleij , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI Message-ID: <20151022105745.2cc158a3@OPI2> In-Reply-To: <20151022084735.GR10947@lukather> References: <1445444428-4652-1-git-send-email-jenskuske@gmail.com> <1445444428-4652-2-git-send-email-jenskuske@gmail.com> <20151022080508.GN10947@lukather> <20151022102959.09f0a1f4@OPI2> <20151022084735.GR10947@lukather> X-Mailer: Claws Mail 3.13.0 (GTK+ 2.24.28; arm-unknown-linux-gnueabihf) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 22 Oct 2015 10:47:35 +0200 Maxime Ripard wrote: > Not really. The uart0 reset is the bit 16, in the reset register 4. > > 4 * 32 + 16 = 44. > > Not 112, but still not 208 either. The registers are numbered 1..5, then (4 - 1) * 32 + 16 = 112 -- Ken ar c'hentañ | ** Breizh ha Linux atav! ** Jef | http://moinejf.free.fr/