diff for duplicates of <20151022120326.20687.80247@quantum> diff --git a/a/1.txt b/N1/1.txt index 4e50bb5..36147ae 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,13 +1,11 @@ Quoting Heiko Stuebner (2015-09-30 07:07:37) > From: Douglas Anderson <dianders@chromium.org> -> = - +> > Because of the inexact nature of the extra MMC delay elements (it's > not possible to keep the phase monotonic and to also make phases (mod > 90) > 70), we previously only allowed phases (mod 90) of 22.5, 45, > and 67.5. -> = - +> > But it's not the end of the world if the MMC clock phase goes > non-monotonic. At most we'll be 25 degrees off. It's way better to > test more phases to look for bad ones than to be 25 degrees off, because @@ -16,11 +14,9 @@ Quoting Heiko Stuebner (2015-09-30 07:07:37) > slightly non-monotonic then that might be fine. Worst case we would > end up at a phases that's slight differnt than the one we wanted, but > at least we'd still be quite far away from the a bad phase. -> = - +> > Signed-off-by: Douglas Anderson <dianders@chromium.org> -> = - +> > Fold in more precise variance-values of 44-77 instead of 40-80. > Fold in the actual removal of the monotonic requirement and adapt > patch message accordingly. @@ -32,50 +28,38 @@ Regards, Mike > --- -> drivers/clk/rockchip/clk-mmc-phase.c | 45 ++++++++++++++++++++++++------= ------- +> drivers/clk/rockchip/clk-mmc-phase.c | 45 ++++++++++++++++++++++++------------ > 1 file changed, 30 insertions(+), 15 deletions(-) -> = - -> diff --git a/drivers/clk/rockchip/clk-mmc-phase.c b/drivers/clk/rockchip/= -clk-mmc-phase.c +> +> diff --git a/drivers/clk/rockchip/clk-mmc-phase.c b/drivers/clk/rockchip/clk-mmc-phase.c > index 9b61342..a797d86 100644 > --- a/drivers/clk/rockchip/clk-mmc-phase.c > +++ b/drivers/clk/rockchip/clk-mmc-phase.c -> @@ -45,8 +45,8 @@ static unsigned long rockchip_mmc_recalc(struct clk_hw = -*hw, +> @@ -45,8 +45,8 @@ static unsigned long rockchip_mmc_recalc(struct clk_hw *hw, > #define PSECS_PER_SEC 1000000000000LL -> = - +> > /* -> - * Each fine delay is between 40ps-80ps. Assume each fine delay is 60ps = -to -> - * simplify calculations. So 45degs could be anywhere between 33deg and = -66deg. -> + * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps = -to -> + * simplify calculations. So 45degs could be anywhere between 33deg and = -57.8deg. +> - * Each fine delay is between 40ps-80ps. Assume each fine delay is 60ps to +> - * simplify calculations. So 45degs could be anywhere between 33deg and 66deg. +> + * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to +> + * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg. > */ > #define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60 -> = - -> @@ -84,22 +84,37 @@ static int rockchip_mmc_set_phase(struct clk_hw *hw, = -int degrees) +> +> @@ -84,22 +84,37 @@ static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees) > u32 raw_value; > u64 delay; -> = - +> > - /* allow 22 to be 22.5 */ > - degrees++; > - /* floor to 22.5 increment */ -> - degrees -=3D ((degrees) * 10 % 225) / 10; +> - degrees -= ((degrees) * 10 % 225) / 10; > - -> nineties =3D degrees / 90; +> nineties = degrees / 90; > - /* 22.5 multiples */ -> - remainder =3D (degrees % 90) / 22; +> - remainder = (degrees % 90) / 22; > - -> + remainder =3D (degrees % 90); +> + remainder = (degrees % 90); > + > + /* > + * Due to the inexact nature of the "fine" delay, we might @@ -100,22 +84,19 @@ int degrees) > + * Convert to delay; do a little extra work to make sure we > + * don't overflow 32-bit / 64-bit numbers. > + */ -> delay =3D PSECS_PER_SEC; +> delay = PSECS_PER_SEC; > - do_div(delay, rate); > - /* / 360 / 22.5 */ > - do_div(delay, 16); > - do_div(delay, ROCKCHIP_MMC_DELAY_ELEMENT_PSEC); > - -> delay *=3D remainder; +> delay *= remainder; > + do_div(delay, 10000); -> + do_div(delay, (rate / 1000) * 36 * ROCKCHIP_MMC_DELAY_ELEMENT_PSE= -C); +> + do_div(delay, (rate / 1000) * 36 * ROCKCHIP_MMC_DELAY_ELEMENT_PSEC); > + -> delay_num =3D (u8) min(delay, 255ULL); -> = - -> raw_value =3D delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0; -> -- = - +> delay_num = (u8) min(delay, 255ULL); +> +> raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0; +> -- > 2.5.1 ->=20 +> diff --git a/a/content_digest b/N1/content_digest index 2cafab9..25242b6 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -3,8 +3,7 @@ "From\0Michael Turquette <mturquette@baylibre.com>\0" "Subject\0Re: [PATCH v2 1/8] clk: rockchip: Allow more precision for some mmc clock phases\0" "Date\0Thu, 22 Oct 2015 05:03:26 -0700\0" - "To\0Heiko Stuebner <heiko@sntech.de>" - ulf.hansson@linaro.org + "To\0ulf.hansson@linaro.org" sboyd@codeaurora.org tgih.jun@samsung.com " jh80.chung@samsung.com\0" @@ -19,14 +18,12 @@ "b\0" "Quoting Heiko Stuebner (2015-09-30 07:07:37)\n" "> From: Douglas Anderson <dianders@chromium.org>\n" - "> =\n" - "\n" + "> \n" "> Because of the inexact nature of the extra MMC delay elements (it's\n" "> not possible to keep the phase monotonic and to also make phases (mod\n" "> 90) > 70), we previously only allowed phases (mod 90) of 22.5, 45,\n" "> and 67.5.\n" - "> =\n" - "\n" + "> \n" "> But it's not the end of the world if the MMC clock phase goes\n" "> non-monotonic. At most we'll be 25 degrees off. It's way better to\n" "> test more phases to look for bad ones than to be 25 degrees off, because\n" @@ -35,11 +32,9 @@ "> slightly non-monotonic then that might be fine. Worst case we would\n" "> end up at a phases that's slight differnt than the one we wanted, but\n" "> at least we'd still be quite far away from the a bad phase.\n" - "> =\n" - "\n" + "> \n" "> Signed-off-by: Douglas Anderson <dianders@chromium.org>\n" - "> =\n" - "\n" + "> \n" "> Fold in more precise variance-values of 44-77 instead of 40-80.\n" "> Fold in the actual removal of the monotonic requirement and adapt\n" "> patch message accordingly.\n" @@ -51,50 +46,38 @@ "Mike\n" "\n" "> ---\n" - "> drivers/clk/rockchip/clk-mmc-phase.c | 45 ++++++++++++++++++++++++------=\n" - "------\n" + "> drivers/clk/rockchip/clk-mmc-phase.c | 45 ++++++++++++++++++++++++------------\n" "> 1 file changed, 30 insertions(+), 15 deletions(-)\n" - "> =\n" - "\n" - "> diff --git a/drivers/clk/rockchip/clk-mmc-phase.c b/drivers/clk/rockchip/=\n" - "clk-mmc-phase.c\n" + "> \n" + "> diff --git a/drivers/clk/rockchip/clk-mmc-phase.c b/drivers/clk/rockchip/clk-mmc-phase.c\n" "> index 9b61342..a797d86 100644\n" "> --- a/drivers/clk/rockchip/clk-mmc-phase.c\n" "> +++ b/drivers/clk/rockchip/clk-mmc-phase.c\n" - "> @@ -45,8 +45,8 @@ static unsigned long rockchip_mmc_recalc(struct clk_hw =\n" - "*hw,\n" + "> @@ -45,8 +45,8 @@ static unsigned long rockchip_mmc_recalc(struct clk_hw *hw,\n" "> #define PSECS_PER_SEC 1000000000000LL\n" - "> =\n" - "\n" + "> \n" "> /*\n" - "> - * Each fine delay is between 40ps-80ps. Assume each fine delay is 60ps =\n" - "to\n" - "> - * simplify calculations. So 45degs could be anywhere between 33deg and =\n" - "66deg.\n" - "> + * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps =\n" - "to\n" - "> + * simplify calculations. So 45degs could be anywhere between 33deg and =\n" - "57.8deg.\n" + "> - * Each fine delay is between 40ps-80ps. Assume each fine delay is 60ps to\n" + "> - * simplify calculations. So 45degs could be anywhere between 33deg and 66deg.\n" + "> + * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to\n" + "> + * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg.\n" "> */\n" "> #define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60\n" - "> =\n" - "\n" - "> @@ -84,22 +84,37 @@ static int rockchip_mmc_set_phase(struct clk_hw *hw, =\n" - "int degrees)\n" + "> \n" + "> @@ -84,22 +84,37 @@ static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees)\n" "> u32 raw_value;\n" "> u64 delay;\n" - "> =\n" - "\n" + "> \n" "> - /* allow 22 to be 22.5 */\n" "> - degrees++;\n" "> - /* floor to 22.5 increment */\n" - "> - degrees -=3D ((degrees) * 10 % 225) / 10;\n" + "> - degrees -= ((degrees) * 10 % 225) / 10;\n" "> -\n" - "> nineties =3D degrees / 90;\n" + "> nineties = degrees / 90;\n" "> - /* 22.5 multiples */\n" - "> - remainder =3D (degrees % 90) / 22;\n" + "> - remainder = (degrees % 90) / 22;\n" "> -\n" - "> + remainder =3D (degrees % 90);\n" + "> + remainder = (degrees % 90);\n" "> +\n" "> + /*\n" "> + * Due to the inexact nature of the \"fine\" delay, we might\n" @@ -119,24 +102,21 @@ "> + * Convert to delay; do a little extra work to make sure we\n" "> + * don't overflow 32-bit / 64-bit numbers.\n" "> + */\n" - "> delay =3D PSECS_PER_SEC;\n" + "> delay = PSECS_PER_SEC;\n" "> - do_div(delay, rate);\n" "> - /* / 360 / 22.5 */\n" "> - do_div(delay, 16);\n" "> - do_div(delay, ROCKCHIP_MMC_DELAY_ELEMENT_PSEC);\n" "> -\n" - "> delay *=3D remainder;\n" + "> delay *= remainder;\n" "> + do_div(delay, 10000);\n" - "> + do_div(delay, (rate / 1000) * 36 * ROCKCHIP_MMC_DELAY_ELEMENT_PSE=\n" - "C);\n" + "> + do_div(delay, (rate / 1000) * 36 * ROCKCHIP_MMC_DELAY_ELEMENT_PSEC);\n" "> +\n" - "> delay_num =3D (u8) min(delay, 255ULL);\n" - "> =\n" - "\n" - "> raw_value =3D delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0;\n" - "> -- =\n" - "\n" + "> delay_num = (u8) min(delay, 255ULL);\n" + "> \n" + "> raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0;\n" + "> -- \n" "> 2.5.1\n" - >=20 + > -baf7704763a513c8ce61f749b27545456821e9189affb1641a727a267719bf75 +a469d13de9e4f49cec42b63bea2ea8913599f20c037ea07c3aaf156f8127af63
diff --git a/a/1.txt b/N2/1.txt index 4e50bb5..36147ae 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,13 +1,11 @@ Quoting Heiko Stuebner (2015-09-30 07:07:37) > From: Douglas Anderson <dianders@chromium.org> -> = - +> > Because of the inexact nature of the extra MMC delay elements (it's > not possible to keep the phase monotonic and to also make phases (mod > 90) > 70), we previously only allowed phases (mod 90) of 22.5, 45, > and 67.5. -> = - +> > But it's not the end of the world if the MMC clock phase goes > non-monotonic. At most we'll be 25 degrees off. It's way better to > test more phases to look for bad ones than to be 25 degrees off, because @@ -16,11 +14,9 @@ Quoting Heiko Stuebner (2015-09-30 07:07:37) > slightly non-monotonic then that might be fine. Worst case we would > end up at a phases that's slight differnt than the one we wanted, but > at least we'd still be quite far away from the a bad phase. -> = - +> > Signed-off-by: Douglas Anderson <dianders@chromium.org> -> = - +> > Fold in more precise variance-values of 44-77 instead of 40-80. > Fold in the actual removal of the monotonic requirement and adapt > patch message accordingly. @@ -32,50 +28,38 @@ Regards, Mike > --- -> drivers/clk/rockchip/clk-mmc-phase.c | 45 ++++++++++++++++++++++++------= ------- +> drivers/clk/rockchip/clk-mmc-phase.c | 45 ++++++++++++++++++++++++------------ > 1 file changed, 30 insertions(+), 15 deletions(-) -> = - -> diff --git a/drivers/clk/rockchip/clk-mmc-phase.c b/drivers/clk/rockchip/= -clk-mmc-phase.c +> +> diff --git a/drivers/clk/rockchip/clk-mmc-phase.c b/drivers/clk/rockchip/clk-mmc-phase.c > index 9b61342..a797d86 100644 > --- a/drivers/clk/rockchip/clk-mmc-phase.c > +++ b/drivers/clk/rockchip/clk-mmc-phase.c -> @@ -45,8 +45,8 @@ static unsigned long rockchip_mmc_recalc(struct clk_hw = -*hw, +> @@ -45,8 +45,8 @@ static unsigned long rockchip_mmc_recalc(struct clk_hw *hw, > #define PSECS_PER_SEC 1000000000000LL -> = - +> > /* -> - * Each fine delay is between 40ps-80ps. Assume each fine delay is 60ps = -to -> - * simplify calculations. So 45degs could be anywhere between 33deg and = -66deg. -> + * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps = -to -> + * simplify calculations. So 45degs could be anywhere between 33deg and = -57.8deg. +> - * Each fine delay is between 40ps-80ps. Assume each fine delay is 60ps to +> - * simplify calculations. So 45degs could be anywhere between 33deg and 66deg. +> + * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to +> + * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg. > */ > #define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60 -> = - -> @@ -84,22 +84,37 @@ static int rockchip_mmc_set_phase(struct clk_hw *hw, = -int degrees) +> +> @@ -84,22 +84,37 @@ static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees) > u32 raw_value; > u64 delay; -> = - +> > - /* allow 22 to be 22.5 */ > - degrees++; > - /* floor to 22.5 increment */ -> - degrees -=3D ((degrees) * 10 % 225) / 10; +> - degrees -= ((degrees) * 10 % 225) / 10; > - -> nineties =3D degrees / 90; +> nineties = degrees / 90; > - /* 22.5 multiples */ -> - remainder =3D (degrees % 90) / 22; +> - remainder = (degrees % 90) / 22; > - -> + remainder =3D (degrees % 90); +> + remainder = (degrees % 90); > + > + /* > + * Due to the inexact nature of the "fine" delay, we might @@ -100,22 +84,19 @@ int degrees) > + * Convert to delay; do a little extra work to make sure we > + * don't overflow 32-bit / 64-bit numbers. > + */ -> delay =3D PSECS_PER_SEC; +> delay = PSECS_PER_SEC; > - do_div(delay, rate); > - /* / 360 / 22.5 */ > - do_div(delay, 16); > - do_div(delay, ROCKCHIP_MMC_DELAY_ELEMENT_PSEC); > - -> delay *=3D remainder; +> delay *= remainder; > + do_div(delay, 10000); -> + do_div(delay, (rate / 1000) * 36 * ROCKCHIP_MMC_DELAY_ELEMENT_PSE= -C); +> + do_div(delay, (rate / 1000) * 36 * ROCKCHIP_MMC_DELAY_ELEMENT_PSEC); > + -> delay_num =3D (u8) min(delay, 255ULL); -> = - -> raw_value =3D delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0; -> -- = - +> delay_num = (u8) min(delay, 255ULL); +> +> raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0; +> -- > 2.5.1 ->=20 +> diff --git a/a/content_digest b/N2/content_digest index 2cafab9..9b35ef8 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,32 +1,19 @@ "ref\01443622064-14362-1-git-send-email-heiko@sntech.de\0" "ref\01443622064-14362-2-git-send-email-heiko@sntech.de\0" - "From\0Michael Turquette <mturquette@baylibre.com>\0" - "Subject\0Re: [PATCH v2 1/8] clk: rockchip: Allow more precision for some mmc clock phases\0" + "From\0mturquette@baylibre.com (Michael Turquette)\0" + "Subject\0[PATCH v2 1/8] clk: rockchip: Allow more precision for some mmc clock phases\0" "Date\0Thu, 22 Oct 2015 05:03:26 -0700\0" - "To\0Heiko Stuebner <heiko@sntech.de>" - ulf.hansson@linaro.org - sboyd@codeaurora.org - tgih.jun@samsung.com - " jh80.chung@samsung.com\0" - "Cc\0linux-mmc@vger.kernel.org" - linux-clk@vger.kernel.org - linux-arm-kernel@lists.infradead.org - linux-rockchip@lists.infradead.org - dianders@chromium.org - amstan@chromium.org - " Heiko Stuebner <heiko@sntech.de>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Quoting Heiko Stuebner (2015-09-30 07:07:37)\n" "> From: Douglas Anderson <dianders@chromium.org>\n" - "> =\n" - "\n" + "> \n" "> Because of the inexact nature of the extra MMC delay elements (it's\n" "> not possible to keep the phase monotonic and to also make phases (mod\n" "> 90) > 70), we previously only allowed phases (mod 90) of 22.5, 45,\n" "> and 67.5.\n" - "> =\n" - "\n" + "> \n" "> But it's not the end of the world if the MMC clock phase goes\n" "> non-monotonic. At most we'll be 25 degrees off. It's way better to\n" "> test more phases to look for bad ones than to be 25 degrees off, because\n" @@ -35,11 +22,9 @@ "> slightly non-monotonic then that might be fine. Worst case we would\n" "> end up at a phases that's slight differnt than the one we wanted, but\n" "> at least we'd still be quite far away from the a bad phase.\n" - "> =\n" - "\n" + "> \n" "> Signed-off-by: Douglas Anderson <dianders@chromium.org>\n" - "> =\n" - "\n" + "> \n" "> Fold in more precise variance-values of 44-77 instead of 40-80.\n" "> Fold in the actual removal of the monotonic requirement and adapt\n" "> patch message accordingly.\n" @@ -51,50 +36,38 @@ "Mike\n" "\n" "> ---\n" - "> drivers/clk/rockchip/clk-mmc-phase.c | 45 ++++++++++++++++++++++++------=\n" - "------\n" + "> drivers/clk/rockchip/clk-mmc-phase.c | 45 ++++++++++++++++++++++++------------\n" "> 1 file changed, 30 insertions(+), 15 deletions(-)\n" - "> =\n" - "\n" - "> diff --git a/drivers/clk/rockchip/clk-mmc-phase.c b/drivers/clk/rockchip/=\n" - "clk-mmc-phase.c\n" + "> \n" + "> diff --git a/drivers/clk/rockchip/clk-mmc-phase.c b/drivers/clk/rockchip/clk-mmc-phase.c\n" "> index 9b61342..a797d86 100644\n" "> --- a/drivers/clk/rockchip/clk-mmc-phase.c\n" "> +++ b/drivers/clk/rockchip/clk-mmc-phase.c\n" - "> @@ -45,8 +45,8 @@ static unsigned long rockchip_mmc_recalc(struct clk_hw =\n" - "*hw,\n" + "> @@ -45,8 +45,8 @@ static unsigned long rockchip_mmc_recalc(struct clk_hw *hw,\n" "> #define PSECS_PER_SEC 1000000000000LL\n" - "> =\n" - "\n" + "> \n" "> /*\n" - "> - * Each fine delay is between 40ps-80ps. Assume each fine delay is 60ps =\n" - "to\n" - "> - * simplify calculations. So 45degs could be anywhere between 33deg and =\n" - "66deg.\n" - "> + * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps =\n" - "to\n" - "> + * simplify calculations. So 45degs could be anywhere between 33deg and =\n" - "57.8deg.\n" + "> - * Each fine delay is between 40ps-80ps. Assume each fine delay is 60ps to\n" + "> - * simplify calculations. So 45degs could be anywhere between 33deg and 66deg.\n" + "> + * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to\n" + "> + * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg.\n" "> */\n" "> #define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60\n" - "> =\n" - "\n" - "> @@ -84,22 +84,37 @@ static int rockchip_mmc_set_phase(struct clk_hw *hw, =\n" - "int degrees)\n" + "> \n" + "> @@ -84,22 +84,37 @@ static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees)\n" "> u32 raw_value;\n" "> u64 delay;\n" - "> =\n" - "\n" + "> \n" "> - /* allow 22 to be 22.5 */\n" "> - degrees++;\n" "> - /* floor to 22.5 increment */\n" - "> - degrees -=3D ((degrees) * 10 % 225) / 10;\n" + "> - degrees -= ((degrees) * 10 % 225) / 10;\n" "> -\n" - "> nineties =3D degrees / 90;\n" + "> nineties = degrees / 90;\n" "> - /* 22.5 multiples */\n" - "> - remainder =3D (degrees % 90) / 22;\n" + "> - remainder = (degrees % 90) / 22;\n" "> -\n" - "> + remainder =3D (degrees % 90);\n" + "> + remainder = (degrees % 90);\n" "> +\n" "> + /*\n" "> + * Due to the inexact nature of the \"fine\" delay, we might\n" @@ -119,24 +92,21 @@ "> + * Convert to delay; do a little extra work to make sure we\n" "> + * don't overflow 32-bit / 64-bit numbers.\n" "> + */\n" - "> delay =3D PSECS_PER_SEC;\n" + "> delay = PSECS_PER_SEC;\n" "> - do_div(delay, rate);\n" "> - /* / 360 / 22.5 */\n" "> - do_div(delay, 16);\n" "> - do_div(delay, ROCKCHIP_MMC_DELAY_ELEMENT_PSEC);\n" "> -\n" - "> delay *=3D remainder;\n" + "> delay *= remainder;\n" "> + do_div(delay, 10000);\n" - "> + do_div(delay, (rate / 1000) * 36 * ROCKCHIP_MMC_DELAY_ELEMENT_PSE=\n" - "C);\n" + "> + do_div(delay, (rate / 1000) * 36 * ROCKCHIP_MMC_DELAY_ELEMENT_PSEC);\n" "> +\n" - "> delay_num =3D (u8) min(delay, 255ULL);\n" - "> =\n" - "\n" - "> raw_value =3D delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0;\n" - "> -- =\n" - "\n" + "> delay_num = (u8) min(delay, 255ULL);\n" + "> \n" + "> raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0;\n" + "> -- \n" "> 2.5.1\n" - >=20 + > -baf7704763a513c8ce61f749b27545456821e9189affb1641a727a267719bf75 +9d383591623dea2b671caf7cc7cd02c4f58a3245eb2711cbfecaaa6d7ee87db1
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