From mboxrd@z Thu Jan 1 00:00:00 1970 From: maxime.ripard@free-electrons.com (Maxime Ripard) Date: Fri, 23 Oct 2015 20:09:27 +0200 Subject: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI In-Reply-To: <5628C8E2.6040703@gmail.com> References: <1445444428-4652-1-git-send-email-jenskuske@gmail.com> <1445444428-4652-2-git-send-email-jenskuske@gmail.com> <20151022080508.GN10947@lukather> <20151022102959.09f0a1f4@OPI2> <20151022084735.GR10947@lukather> <20151022105745.2cc158a3@OPI2> <20151022091410.GW10947@lukather> <5628C8E2.6040703@gmail.com> Message-ID: <20151023180927.GJ10947@lukather> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Thu, Oct 22, 2015 at 01:30:42PM +0200, Jens Kuske wrote: > On 22/10/15 11:14, Maxime Ripard wrote: > > On Thu, Oct 22, 2015 at 10:57:45AM +0200, Jean-Francois Moine wrote: > >> On Thu, 22 Oct 2015 10:47:35 +0200 > >> Maxime Ripard wrote: > >> > >>> Not really. The uart0 reset is the bit 16, in the reset register 4. > >>> > >>> 4 * 32 + 16 = 44. > >>> > >>> Not 112, but still not 208 either. > >> > >> The registers are numbered 1..5, then > >> > >> (4 - 1) * 32 + 16 = 112 > > > > Not on my version, and even then, UARTs are on the last reset > > register, which would still make 144. > > > > Maxime > > > > There are holes between reg2 and reg3 and reg4 for some reason, but even > if we would correct that with some of_xlate() function they won't > completely line up with the gates. Indeed. Still, dealing with the holes and sticking to what the datasheet says seems like the right solution. Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI Date: Fri, 23 Oct 2015 20:09:27 +0200 Message-ID: <20151023180927.GJ10947@lukather> References: <1445444428-4652-1-git-send-email-jenskuske@gmail.com> <1445444428-4652-2-git-send-email-jenskuske@gmail.com> <20151022080508.GN10947@lukather> <20151022102959.09f0a1f4@OPI2> <20151022084735.GR10947@lukather> <20151022105745.2cc158a3@OPI2> <20151022091410.GW10947@lukather> <5628C8E2.6040703@gmail.com> Reply-To: maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="xcivb/T/gnJQjo5J" Return-path: Content-Disposition: inline In-Reply-To: <5628C8E2.6040703-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Jens Kuske Cc: Jean-Francois Moine , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Vishnu Patekar , Emilio =?iso-8859-1?Q?L=F3pez?= , Michael Turquette , linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Hans de Goede , Chen-Yu Tsai , Rob Herring , Philipp Zabel , Linus Walleij , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: devicetree@vger.kernel.org --xcivb/T/gnJQjo5J Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline On Thu, Oct 22, 2015 at 01:30:42PM +0200, Jens Kuske wrote: > On 22/10/15 11:14, Maxime Ripard wrote: > > On Thu, Oct 22, 2015 at 10:57:45AM +0200, Jean-Francois Moine wrote: > >> On Thu, 22 Oct 2015 10:47:35 +0200 > >> Maxime Ripard wrote: > >> > >>> Not really. The uart0 reset is the bit 16, in the reset register 4. > >>> > >>> 4 * 32 + 16 = 44. > >>> > >>> Not 112, but still not 208 either. > >> > >> The registers are numbered 1..5, then > >> > >> (4 - 1) * 32 + 16 = 112 > > > > Not on my version, and even then, UARTs are on the last reset > > register, which would still make 144. > > > > Maxime > > > > There are holes between reg2 and reg3 and reg4 for some reason, but even > if we would correct that with some of_xlate() function they won't > completely line up with the gates. Indeed. Still, dealing with the holes and sticking to what the datasheet says seems like the right solution. Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --xcivb/T/gnJQjo5J-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754407AbbJWSJd (ORCPT ); Fri, 23 Oct 2015 14:09:33 -0400 Received: from down.free-electrons.com ([37.187.137.238]:42730 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753370AbbJWSJa (ORCPT ); Fri, 23 Oct 2015 14:09:30 -0400 Date: Fri, 23 Oct 2015 20:09:27 +0200 From: Maxime Ripard To: Jens Kuske Cc: Jean-Francois Moine , devicetree@vger.kernel.org, Vishnu Patekar , Emilio =?iso-8859-1?Q?L=F3pez?= , Michael Turquette , linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org, Hans de Goede , Chen-Yu Tsai , Rob Herring , Philipp Zabel , Linus Walleij , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH 5/6] ARM: dts: sunxi: Add Allwinner H3 DTSI Message-ID: <20151023180927.GJ10947@lukather> References: <1445444428-4652-1-git-send-email-jenskuske@gmail.com> <1445444428-4652-2-git-send-email-jenskuske@gmail.com> <20151022080508.GN10947@lukather> <20151022102959.09f0a1f4@OPI2> <20151022084735.GR10947@lukather> <20151022105745.2cc158a3@OPI2> <20151022091410.GW10947@lukather> <5628C8E2.6040703@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="xcivb/T/gnJQjo5J" Content-Disposition: inline In-Reply-To: <5628C8E2.6040703@gmail.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --xcivb/T/gnJQjo5J Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Oct 22, 2015 at 01:30:42PM +0200, Jens Kuske wrote: > On 22/10/15 11:14, Maxime Ripard wrote: > > On Thu, Oct 22, 2015 at 10:57:45AM +0200, Jean-Francois Moine wrote: > >> On Thu, 22 Oct 2015 10:47:35 +0200 > >> Maxime Ripard wrote: > >> > >>> Not really. The uart0 reset is the bit 16, in the reset register 4. > >>> > >>> 4 * 32 + 16 =3D 44. > >>> > >>> Not 112, but still not 208 either. > >> > >> The registers are numbered 1..5, then > >> > >> (4 - 1) * 32 + 16 =3D 112 > >=20 > > Not on my version, and even then, UARTs are on the last reset > > register, which would still make 144. > >=20 > > Maxime > >=20 >=20 > There are holes between reg2 and reg3 and reg4 for some reason, but even > if we would correct that with some of_xlate() function they won't > completely line up with the gates. Indeed. Still, dealing with the holes and sticking to what the datasheet says seems like the right solution. Maxime --=20 Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com --xcivb/T/gnJQjo5J Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJWKnfXAAoJEBx+YmzsjxAg+DsQAK/pYiIOUAnc6DtuvCPrW7f2 O/xsbv+wdWO7IWy+/LfJZw+a7tkwZJpvJau3Nb2o+2GvW8PHaoEeczwV0kL2A66i 55tmJWGY34x0KZV8zv990T/+0sySksJ4LtDPd2LvHd7dgg3g575MuENa66WOjPXd 0my/40EvBOHlUc9FzMOhhjBwJa5y+1njcK6A5x+HzSFVeTPrnCDLa6yRLvWlycKM NzQbBmuPp3GNIVLV0qRF8zZcXKA/ptQ0M46LOSuEe2BR59NFWjDPr4vzDEyJ9dDu wT2ipMZQBJ3TAhS0l3cemYI5iDqeUl8O/y3h6PQ0iCkZr7ShDC4vjAzw16tiHn6e 6swsoABNec8Hd/J5ffMp6kBDdaPRSxmTwduM/s6b5ueD45gyYlAN4k/0AnNQfS+j +YCfiBPB+CYPYEDn67Y4yPIdWwGZPYTIB5+9y/caRUQsxLHrYvniMQ2g05Da8jar s9C8RjyCdUHyWOdQdr91aqZN3Nj7Nim4XDaTrVblAuWygSIZ5okST6NOaVygGU3b 0WbO/P4/ZqWmHMMiNvO06O+4xKZK1CnHbd09NUxx/fdN9NxycBxsH3WtM+l5wtXa hhl24LrfpmB/GwTg6TsexkwVG4uvZc+3oofTUHkcRTdb1Gi4aAesZEVN7YBHUvG2 Z3jtt8q8255QoeqSICG6 =rAIW -----END PGP SIGNATURE----- --xcivb/T/gnJQjo5J--